TWI736791B - 半導體結構及其形成方法 - Google Patents

半導體結構及其形成方法 Download PDF

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TWI736791B
TWI736791B TW107128373A TW107128373A TWI736791B TW I736791 B TWI736791 B TW I736791B TW 107128373 A TW107128373 A TW 107128373A TW 107128373 A TW107128373 A TW 107128373A TW I736791 B TWI736791 B TW I736791B
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Taiwan
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substrate
protective layer
die
wafer
bonded
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TW107128373A
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TW202005037A (zh
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余振華
郭宏瑞
蔡惠榕
張晁綸
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台灣積體電路製造股份有限公司
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Abstract

公開半導體結構及其形成方法。所述半導體結構包括第 一晶粒、第二晶粒、第一包封材料及保護層。第一晶粒包括第一基底。第二晶粒接合到第一晶粒且包括第二基底。第一包封材料包封第一晶粒。保護層設置在第一基底的側壁上且設置在所述第一基底與第一包封材料之間，其中所述保護層的材料不同於第二基底的材料及所述第一包封材料的材料。

Description

半導體結構及其形成方法
本發明實施例是有關於一種半導體結構。
目前正在發展晶圓級封裝(wafer level packaging)的三維積體技術以滿足對高密度積體封裝的尺寸減小、高性能互連及異構集成(heterogeneous integration)的需求。
本發明實施例的半導體結構包括第一晶粒、第二晶粒、第一包封材料及保護層。第一晶粒包括第一基底。第二晶粒接合到第一晶粒且包括第二基底。第一包封材料包封第一晶粒。保護層設置在第一基底的側壁上且設置在所述第一基底與第一包封材料之間，其中所述保護層的材料不同於第二基底的材料及所述第一包封材料的材料。
110:基底
110a、310a:側壁
110b:表面
112:介電層
114:開口
116:焊墊
116a:內側壁
118:凹陷
120:擴散障壁層
122、216、312、412、420、426、430、508:介電層
124、218:導電層
126:間隙
130、330、330a:保護層
210:基底
212:介電層
214:焊墊
220、318:凸塊
230:介電材料
310、410:基底
310b:表面
314、414:焊墊
316、416:導電柱
410a:晶片區域
418:穿孔
422、424:導電圖案
428、504:載板
500、512:包封材料
502:經接合單元
506:剝離層
510:導電杆
514:重佈線路結構
516:導電端子
518:接觸開口
C1:晶片
C2:晶片
EP:蝕刻製程
S10、S20、S30、S40、S50、S100、S110、S120:步驟
W:晶圓
圖1是繪示根據一些實施例的形成半導體結構的方法的流程圖。
圖2A到圖2E是繪示根據一些實施例的形成半導體結構的方法的示意圖。
圖3是繪示根據一些實施例的形成半導體結構的方法的流程圖。
圖4A到圖4C是繪示根據一些實施例的形成半導體結構的方法的示意圖。
圖5A到圖5H是繪示根據一些實施例的形成半導體結構的方法的示意圖。
圖6A到圖6E是繪示根據一些實施例的形成半導體結構的方法的示意圖。
圖7A到圖7D是繪示根據一些實施例的形成半導體結構的方法的示意圖。
圖8是繪示根據一些實施例的半導體結構的示意圖。
圖9A到圖9G是繪示根據一些實施例的形成半導體結構的方法的示意圖。
以下公開內容提供用於實作所提供主題的不同特徵的許多不同的實施例或實例。以下闡述元件及排列的具體實例以簡化本發明。當然，這些僅為實例且不旨在進行限制。舉例來說，以 下說明中將第二特徵形成在第一特徵“之上”或第一特徵“上”可包括其中第二特徵及第一特徵被形成為直接接觸的實施例，且也可包括其中第二特徵與第一特徵之間可形成有附加特徵、進而使得所述第二特徵與所述第一特徵可能不直接接觸的實施例。另外，本發明可能在各種實例中重複使用元件符號及/或字母。此種重複是出於簡潔及清晰的目的，而不是自身指示所論述的各種實施例及/或配置之間的關係。
此外，為易於說明，本文中可能使用例如“頂部(top)”、“下面(below)”、“下部的(lower)”、“上方(above)“上部的(upper)”等空間相對性用語來闡述圖中所示的一個元件或特徵與另一(其他)元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的取向外還囊括元件在使用或操作中的不同取向。裝置可具有其他取向(旋轉90度或處於其他取向)且本文中所使用的空間相對性描述語可同樣相應地進行解釋。
也可包括其他特徵及製程。舉例來說，可包括測試結構，以說明對三維(three dimensional，3D)封裝或三維積體電路(3D integrated circuit，3DIC)元件進行驗證測試。所述測試結構可例如包括在重佈線層中或在基底上形成的測試墊，以容許對3D封裝或3DIC進行測試、對探針及/或探針卡(probe card)進行使用等。可對中間結構以及最終結構執行驗證測試。另外，本文中所公開的結構及方法可結合包含對已知良好晶粒的中間驗證的測試方法一起使用，以提高良率(yield)及降低成本。
圖1是繪示根據一些實施例的形成半導體結構的方法的流程圖。圖2A到圖2E是繪示根據一些實施例的形成半導體結構的方法的示意圖。
參照圖1及圖2A，在步驟S10中，提供第一基底110。在一些實施例中，第一基底110可包括：元素半導體，例如具有晶體結構、多晶結構、非晶結構及/或其他適合結構的矽或鍺；化合物半導體，包括碳化矽(silicon carbide)、砷化鎵(gallium arsenic)、磷化鎵(gallium phosphide)、磷化銦(indium phosphide)、砷化銦(indium arsenide)及/或銻化銦(indium antimonide)；合金半導體，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP；任何其他適合的材料；及/或它們的組合。在一些實施例中，半導體的組合可呈混合物形式或梯度形式，例如Si與Ge的比率跨越各個位置而變化的基底。在一些實施例中，當使用蝕刻劑蝕刻第二基底210(繪示在圖2C中)時，第一基底110的材料相對於第二基底210的材料具有低的蝕刻選擇性(etching selectivity)。換句話說，可通過相同的蝕刻劑移除第一基底110的材料及第二基底210的材料。在一些實施例中，第一基底110與第二基底210可包含相同的材料。在一些實施例中，舉例來說，第一基底110及第二基底210是矽基底。然而，本發明並非僅限於此。在一些替代實施例中，舉例來說，第一基底110與第二基底210可具有不同的材料。
在一些實施例中，第一基底110包括第一介電層112及 位於第一介電層112之上的第一焊墊116。提供第一介電層112及第一焊墊116中的至少一者以用於接合。在一些實施例中，第一介電層112包含例如氧化矽(SiOx)、氮氧化矽(SiOxNy)、摻雜氟的氮氧化矽(SiOxNyFz)、任何其他適合的材料及/或它們的組合。在一些實施例中，第一介電層112包括單一介電層或多個介電層。在一些實施例中，舉例來說，第一介電層112的厚度介於0.7微米(um)到1um之間。
在一些實施例中，在第一介電層112的開口114中形成第一焊墊116。在一些實施例中，第一焊墊116中具有凹陷118，換句話說，開口114不被第一焊墊116填滿。在一些實施例中，舉例來說，第一焊墊116為U形。然而，在一些替代實施例中，第一焊墊116可填滿開口114或從開口114突出。在一些實施例中，可通過在開口114的側壁與底表面上共形地形成導電材料來形成具有凹陷118的第一焊墊116。在一些替代實施例中，可通過在開口114中填充導電材料且移除導電圖案的一部分來形成具有凹陷118的第一焊墊116。在一些實施例中，第一焊墊116是由例如銅(Cu)、銅合金、鋁(Al)、鋁合金、鎳(Ni)、鎳合金、任何其他適合的材料及/或它們的組合等導電材料製成。第一焊墊116包括單一金屬層或多個金屬層。在一些實施例中，可通過沉積製程(deposition process)、電鍍製程(electroplating process)、任何其他適合的製程及/或它們的組合來形成第一焊墊116。在一些實施例中，可在第一焊墊116旁邊形成擴散障壁層120。在一些實施 例中，第一焊墊116的頂表面與第一介電層112的頂表面實質上共面。在一些實施例中，舉例來說，第一焊墊116的厚度介於0.1um到0.3um之間，且凹陷118的深度介於0.4um到0.9um之間。
在一些實施例中，在第一基底110與第一介電層112之間進一步形成介電層122及導電層124。在一些實施例中，舉例來說，介電層122包含例如氧化矽(SiO2)、氮化矽(SiNx)、任何其他適合的材料及/或它們的組合等低介電常數(低k)材料。介電層122包括單一介電層或多個介電層。舉例來說，介電層122及導電層124的厚度介於0.7um到1um之間。導電層124形成在介電層122中，且第一焊墊116電連接到導電層124。在一些實施例中，導電層124的頂表面與介電層122的頂表面實質上共面。在一些實施例中，舉例來說，第一焊墊116的寬度小於導電層124的寬度。然而，在一些替代實施例中，舉例來說，第一焊墊116的寬度可等於或大於導電層124的寬度。導電層124是由例如銅(Cu)、銅合金、鋁(Al)、鋁合金、任何其他適合的材料及/或它們的組合等導電材料製成。在一些替代實施例中，可在導電層124旁邊形成擴散障壁層(未繪示)。
在一些實施例中，第一基底110可包括位於其上的更多個介電層及更多個導電層。另外，第一基底110可包括例如邏輯元件等多個積體主動元件。邏輯元件包括應用處理器(application processor，AP)、系統晶片(system on chip，SoC)或類似物。在一些實施例中，系統晶片(SoC)包括數據機模組。基於製程要求， 可使用例如記憶體元件、金屬氧化物半導體場效電晶體(metal oxide semiconductor field effect transistor，MOSFET)元件、互補金屬氧化物半導體(complementary metal oxide semiconductor，CMOS)元件及/或雙載子接面電晶體(bipolar junction transistor，BJT)元件等其他類型的主動元件。
參照圖1及圖2B，在步驟S20中，形成保護層130以覆蓋第一基底110的暴露表面。在一些實施例中，舉例來說，在第一基底110的側壁110a及表面110b上形成保護層130。在一些實施例中，在第一基底110的相對兩表面上形成第一介電層112與保護層130。舉例來說，在第一基底110的頂表面上形成第一介電層112，且在第一基底110的底表面上形成保護層130。在一些實施例中，第一基底110的暴露表面被保護層130完全覆蓋，即第一基底110不被暴露出。在一些實施例中，保護層130直接接觸第一基底110。舉例來說，保護層130為U形。在一些實施例中，位於側壁110a上的保護層130的頂表面與第一基底110的頂表面及介電層122的底表面實質上齊平。然而，本發明並非僅限於此。在一些替代實施例中，保護層130的頂表面可低於或高於第一基底110的頂表面。換句話說，第一基底110的側壁110a的一部分可被暴露出，或者介電層112、122中的至少一者的一部分可被保護層130覆蓋。在一些替代實施例中，可僅在第一基底110的側壁110a或底表面110b上形成保護層130。
在一些實施例中，保護層130的材料不同於第二基底210 的材料。在一些實施例中，舉例來說，當使用蝕刻劑蝕刻第二基底210時，第二基底210的材料相對於保護層130的材料的蝕刻選擇性大於20。在一些實施例中，舉例來說，當使用蝕刻劑蝕刻矽時，保護層130的材料相對於矽具有蝕刻選擇性。在一些實施例中，保護層130可包含氧化矽(SiO2)、氮化矽(SiNx)、氮氧化矽(SiOxNy)、碳化矽(SiC)、任何其他適合的材料或它們的組合。在一些實施例中，保護層130可包含氧化矽(SiO2)或氮化矽(SiNx)，且可通過例如物理氣相沉積(physical vapor deposition，PVD)製程、化學氣相沉積(chemical vapor deposition，CVD)製程、電漿增強型化學氣相沉積(plasma-enhanced chemical vapor deposition，PECVD)製程、電化學沉積(electrochemical deposition，ECD)製程、分子束磊晶(molecular beam epitaxy，MBE)製程或原子層沉積(atomic layer deposition，ALD)製程等沉積製程形成保護層130。在一些替代實施例中，保護層130可包含模塑化合物(molding compound)，且可通過模塑製程(molding process)形成保護層130。在一些替代實施例中，保護層130可為玻璃基底，且可通過黏合劑將第一基底110黏合到保護層130。在一些實施例中，舉例來說，保護層130的厚度介於502奈米(nm)到2um之間。
參照圖1及圖2C，在步驟S30中，提供第二基底210，且保護層130的材料不同於第二基底210的材料。在一些實施例中，如以上所提及，當使用蝕刻劑蝕刻第二基底210時，第一基 底110的材料相對於第二基底210的材料具有低的蝕刻選擇性。在一些實施例中，第二基底210包括第二介電層212及位於第二介電層212之上的第二焊墊214。提供第二介電層212及第二焊墊214中的至少一者以用於接合。在一些實施例中，舉例來說，第二焊墊214填滿第二介電層212的開口，且因此第二介電層212的頂表面與第二焊墊214的頂表面共面。在一些實施例中，舉例來說，第二介電層212及第二焊墊214的厚度介於0.7um到1um之間。在一些實施例中，在第二基底210與第二介電層212之間進一步設置介電層216及導電層218。導電層218設置在介電層216中且電連接至第二焊墊214。第二基底210的材料、第二介電層212的材料、第二焊墊214的材料、介電層216的材料及導電層218的材料可分別相似於第一基底110的材料、第一介電層112的材料、第一焊墊116的材料、介電層122的材料及導電層124的材料，且因此本文中不再予以贅述。在一些實施例中，第二基底210的材料、第二介電層212的材料、第二焊墊214的材料、介電層216的材料及導電層218的材料可各自相同於或不同於第一基底110的材料、第一介電層112的材料、第一焊墊116的材料、介電層122的材料及導電層124的材料。在一些實施例中，舉例來說，第一介電層112的材料可不同於第二介電層212的材料。然而，在一些替代實施例中，第一介電層112的材料可相同於第二介電層212的材料。
在一些實施例中，在第二焊墊214上進一步形成凸塊220 以進行接合。在一些實施例中，凸塊220在第二基底210之上設置在第二介電層212上且從第二介電層212突出。在一些實施例中，舉例來說，凸塊220的寬度小於第一焊墊116的凹陷118的寬度。在一些實施例中，凸塊220是例如錫-銀(SnAg)焊料凸塊等無鉛(lead free，LF)凸塊。在一些替代實施例中，舉例來說，可在凸塊220與第二焊墊214之間形成例如鎳(Ni)層等至少一個導電層。
參照圖1及圖2D，在步驟S40中，對第一基底110與第二基底210進行接合。在一些實施例中，將第二基底210翻轉，且通過第一介電層112與第二介電層212對第一基底110與第二基底210進行接合。在一些實施例中，第一基底110與第二基底210面對面地對準，其中第一基底110的前側(例如，第一介電層112側)面對第二基底210的前側(例如，第二介電層212側)。在一些實施例中，在第一基底110的相對兩側上形成保護層130與第二基底210。在一些實施例中，舉例來說，第一基底110及第二基底210是晶片對晶片接合(chip to chip bonding)。在一些替代實施例中，舉例來說，第一基底110及第二基底210是晶片對晶圓接合(chip to wafer bonding)或晶圓對晶圓接合(wafer to wafer bonding)。
在一些實施例中，第一基底110的第一焊墊116還接合到第二基底210的凸塊220。換句話說，可通過例如混合式接合(hybrid bonding)對第一基底110與第二基底210進行接合。在 一些實施例中，將突出凸塊220插入第一焊墊116的凹陷118中以接觸第一焊墊116，且可在凸塊220與第一焊墊116之間形成金屬間化合物(intermetallic compound，IMC)層(未繪示)。在一些實施例中，由於凸塊220的尺寸被設計成小於第一焊墊116的凹陷118的尺寸，因此在對第一基底110與第二基底210進行接合之後在凸塊220與第一焊墊116的內側壁116a之間會形成間隙126。在一些實施例中，間隙126可被IMC層局部填充或者被IMC層填滿。在一些實施例中，由於存在尺寸差異，因此凸塊220可輕易地接合到第一焊墊116，且凸塊220與第一焊墊116的對準製程的裕度(window)增大。另外，第一基底110的第一焊墊116凹陷且第二基底210的凸塊220突出，且因此它們可更緊地接合在一起。應注意，第一基底110與第二基底210被例示成具有相同的直徑，但本發明並非僅限於此。在一些替代實施例(未繪示)中，第一基底110與第二基底210可具有不同的直徑。在一些實施例中，舉例來說，保護層130的側壁可與第二基底210的側壁在水平方向上分離開一距離。在一些替代實施例中，舉例來說，保護層130的側壁可與第二基底210的側壁對齊。
參照圖1及圖2E，在步驟S50中，在由保護層130保護第一基底110的同時，通過蝕刻製程EP來薄化第二基底210。在一些實施例中，第一基底110的材料與第二基底210的材料對於蝕刻製程EP的蝕刻劑具有相似的材料特性。在一些實施例中，當使用蝕刻劑蝕刻第二基底210時，第一基底110的材料相對於第 二基底210的材料實質上不具有蝕刻選擇性。然而，由於第一基底110由保護層130保護，因此第一基底110免於受到損傷。在一些實施例中，舉例來說，蝕刻製程EP為濕式蝕刻製程(wet etching process)。在一些實施例中，舉例來說，蝕刻製程EP為矽濕式蝕刻製程(silicon wet etching process)。在矽濕式蝕刻製程中，舉例來說，蝕刻劑是氫氧化鉀(KOH)或四甲基氫氧化銨(tetramethylammonium hydroxide，TMAH)的混合物，且可在介於80℃到100℃之間的溫度下執行所述蝕刻製程。在一些實施例中，在薄化製程之後，第二基底210的厚度可介於10um到40um之間。在一些實施例中，不需要在薄化第二基底210之後移除保護層130。換句話說，保護層130被保留下來。
在薄化製程之後，可對圖2E所示結構執行例如包封製程(encapsulating process)及電連接形成製程(forming process of electrical connection)等封裝製程以形成封裝。在一些替代實施例中，如果第一基底110及第二基底210中的至少一者是晶圓，則可在封裝製程之前執行切割製程(dicing process)或單體化製程(singulation process)。
一般來說，使用例如化學機械研磨(chemical mechanical polishing，CMP)等研磨製程(grinding process)來薄化經接合結構的頂部基底。然而，研磨製程可能對例如經接合結構的焊墊等內部結構造成損傷。在一些實施例中，通過形成保護層130以覆蓋經接合結構的底部基底(即，第一基底110)，例如濕式蝕刻製 程等蝕刻製程僅移除經接合結構的頂部基底(即，第二基底210)的一部分而不損傷所述底部基底的基底。換句話說，儘管濕式蝕刻製程是各向同性蝕刻製程(isotropic etching process)，然而通過使用保護層，非期望蝕刻得到防止，且蝕刻方向被控制成朝向頂部基底的一個方向。換句話說，通過形成保護層以及利用所述保護層及基底相對於用於移除所述基底的蝕刻劑的蝕刻選擇性，可對經接合結構中的各基底中薄的一者應用化學方法，且可防止因研磨製程而施加機械力且因此損傷到所述經接合結構。另外，由於保護層可被保留在經接合結構中，因此不需要移除所述保護層。因此，保護層的形成將不會顯著地增加製造半導體結構的成本或時間。
圖3是繪示根據一些實施例的形成半導體結構的方法的流程圖。圖4A到圖4C是繪示根據一些實施例的形成半導體結構的方法的示意圖。
參照圖3及圖4A，在步驟S100中，通過第一焊墊116與第二焊墊214對第一基底110與第二基底210進行接合，且在第一基底110的暴露表面上設置保護層130。在一些實施例中，除提供第一基底110及第二基底210但不提供介電層112、122、212、216以外，經接合結構及保護層130相似於圖2D所示經接合結構及保護層130。換句話說，暴露出位於第一焊墊116、第二焊墊214、導電層124、218及凸塊220旁邊的擴散障壁層120的側壁。在一些實施例中，舉例來說，第一基底110及第二基底210是通過金 屬對金屬接合(metal to metal bonding)進行接合。在一些實施例中，在對第一焊墊116與第二焊墊214進行接合之後，在凸塊220與第一焊墊116的內側壁116a之間會形成間隙126。
參照圖3及圖4B，在步驟S110中，在第一基底110與第二基底210之間形成介電材料230以包封第一焊墊116及第二焊墊214。在一些實施例中，經接合結構包括第一基底110、第二基底210、保護層130及介電材料230。在一些實施例中，將介電材料230形成為包封第一焊墊116、第二焊墊214及導電層124、218。另外，間隙126被介電材料230填滿。在一些實施例中，介電材料230可包含氧化矽(SiOx)、氮氧化矽(SiOxNy)、摻雜氟的氮氧化矽(SiOxNyFz)、任何其他適合的材料及/或它們的組合。在一些實施例中，介電材料230可包括：模塑化合物，例如環氧模塑化合物(epoxy molding compound)；底部填充膠(underfill)；聚合物材料，例如苯環丁烷(benzocyclobutene，BCB)聚合物、聚醯亞胺(polyimide，PI)及聚苯并噁唑(polybenzoxazole，PBO)；任何其他適合的材料；或者它們的組合。在一些實施例中，可通過沉積製程、模塑製程、底部填充膠製程、任何其他適合的製程或它們的組合來形成介電材料230。
參照圖3及圖4C，在步驟S120中，在由保護層130保護第一基底110的同時，通過蝕刻製程EP來薄化第二基底210。在一些實施例中，蝕刻製程EP相似於圖2E中所述的蝕刻製程EP，且本文中不再予以贅述。
圖5A到圖5H是繪示根據一些實施例的形成半導體結構的方法的示意圖。參照圖5A，將包括基底310的晶片(或晶粒)C1接合到包括基底410的晶圓W。在一些實施例中，晶片C1還包括介電層312、位於介電層312中的多個焊墊314及位於焊墊314上的多個導電柱316。在一些實施例中，提供介電層312及焊墊314以用於接合。在一些實施例中，舉例來說，晶片C1可為例如動態隨機存取記憶體(dynamic random access memory，DRAM)等任何適合的記憶體晶片。在一些實施例中，舉例來說，晶片C1還可包括位於基底310與介電層312之間及基底310與焊墊314之間的介電層、導電層及/或積體主動元件。在一些實施例中，基底310、介電層312及焊墊314相似於基底110、介電層112及焊墊116，且本文中不再予以贅述。
在一些實施例中，晶圓W還包括介電層412及位於介電層412中的多個焊墊414。在一些實施例中，提供介電層412及焊墊414以用於接合。在一些實施例中，在晶圓W上形成多個導電柱416以電連接焊墊414。舉例來說，導電柱416可為銅柱。在一些實施例中，舉例來說，晶圓W還可包括位於基底410與介電層412之間及基底410與焊墊414之間的介電層、導電層及/或積體主動元件。在一些實施例中，基底410、介電層412及焊墊414相似於基底210、介電層212及焊墊214，且本文中不再予以贅述。
在一些實施例中，將晶片C1接合到晶圓W的晶片區域410a中的一者以形成經接合結構。通過焊墊314及焊墊414將晶 片C1接合到晶圓W。在一些實施例中，舉例來說，所述接合是晶片對晶圓接合，且會形成晶圓上晶片(chip-on-wafer，CoW)結構。在一些實施例中，將晶片C1設置在晶片區域410a中的各導電柱416之間。
參照圖5B，形成保護層330以包封晶片C1。在一些實施例中，保護層330設置在晶片C1的暴露表面上，所述暴露表面是基底310的側壁310a及表面310b。在一些實施例中，保護層330形成在晶片C1之間且在晶圓W之上覆蓋晶片C1及導電柱416。在一些實施例中，保護層330相似於保護層130，且本文中不再予以贅述。在一些實施例中，保護層330包含例如模塑化合物(例如，環氧模塑化合物(EMC))、模塑底部填充膠、樹脂、環氧樹脂及/或類似物等包封材料，且可通過模塑製程形成保護層330。
參照圖5C，在由保護層330保護晶片C1的基底310的同時，通過蝕刻製程EP來薄化晶圓W的基底410。在一些實施例中，舉例來說，晶片C1被保護層330完全覆蓋。在一些實施例中，儘管當使用蝕刻劑蝕刻基底410時晶片C1的基底310相對於晶圓W的基底410具有相似的蝕刻選擇性，然而由於基底310由保護層330保護，因此晶片C1的基底310不因蝕刻製程EP而受到損傷。
參照圖5D，切割圖5C所示經接合結構以形成經接合單元502。在一些實施例中，經接合單元502包括晶片C1、從晶圓W的晶片區域410a切割出的晶片(或晶粒)C2及位於晶片C1上 的保護層330。在一些實施例中，舉例來說，經接合單元502是小外廓積體電路(small outline integrated circuit，SOIC)封裝。
參照圖5E，將經接合單元502放置到載板504上。在一些實施例中，依序地在載板504之上堆疊剝離層506及介電層508，並在介電層508之上形成多個導電杆510。將經接合單元502安裝到上面形成有導電杆510的介電層508上。
參照圖5F，將經接合單元502包封在包封材料512中，且對包封材料512及保護層330進行研磨。在一些實施例中，在介電層508上形成包封材料512以包封導電杆510及經接合單元502。在一些實施例中，包封材料512的材料可相同於或不同於保護層330的材料。在一些實施例中，包封材料512可包含模塑化合物、模塑底部填充膠、樹脂、環氧樹脂及/或類似物。
在一些實施例中，對包封材料512及保護層330進行研磨直到導電柱316、416的頂表面及導電杆510的頂表面被暴露出為止。在一些實施例中，舉例來說，所述研磨製程可為機械研磨、化學機械研磨(CMP)或另一適合的機制。在一些實施例中，舉例來說，在研磨之後，保護層330的一些部分被移除，且剩餘的保護層330設置在晶片C1的基底310的側壁上且設置在基底310與包封材料512之間。
參照圖5G，在包封材料512及經接合單元502之上形成電連接到經接合單元502的重佈線路結構514。在一些實施例中，重佈線路結構514形成在導電杆510的頂表面、包封材料512的 頂表面、保護層330的頂表面及導電柱416的頂表面上以電連接經接合單元502的導電柱416與導電杆510。在一些實施例中，重佈線路結構514包括交替堆疊的多個層間介電層及多個重佈線導電圖案。在形成重佈線路結構514之後，在重佈線路結構514上形成多個導電端子516。在一些實施例中，舉例來說，導電端子516可為球柵陣列封裝(ball grid array，BGA)。
參照圖5H，將圖6G所示所形成結構從載板504剝離。在一些實施例中，將介電層508從剝離層506剝離，進而使得介電層508與載板504分離。在一些實施例中，將介電層508圖案化成使得形成多個接觸開口518以局部暴露出導電杆510。在此處，封裝的形成製程實質上完成。在一些替代實施例中，可在接觸開口518中放置多個導電端子(未繪示)以電連接重佈線路結構514與導電杆510。
在一些實施例中，在載板上安裝晶圓的基底之前，通過蝕刻製程而非研磨製程來薄化晶圓的所述基底。因此，防止因研磨製程而對經接合單元的內部結構造成損傷。因此，由經接合結構形成的封裝的性質可得到改善。另外，在一些實施例中，保護層可用作晶片(即，晶片C1)旁邊的包封體且因此所述包封體不是額外形成的，且製造半導體結構的成本或時間不會增加。
圖6A到圖6E是繪示根據一些實施例的形成半導體結構的方法的示意圖。圖6A到圖6E所示方法相似於圖5A到圖5H所示方法，主要差異在於在晶片的暴露表面上且在所述晶片與包封 材料之間額外形成保護層。參照圖6A，在晶片C1的暴露表面上形成保護層330a。在一些實施例中，在基底310的側壁310a及表面310b上設置保護層330a。接著，將晶片C1接合到晶圓W，且保護層330包封上面具有保護層330a的晶片C1。在一些實施例中，保護層330a的材料相似於圖2B所示保護層130的材料，且保護層330a的材料不同於保護層330的材料。在一些實施例中，保護層330包含例如模塑化合物(例如，環氧模塑化合物(EMC))、模塑底部填充膠、樹脂、環氧樹脂及/或類似物等包封材料，且可通過模塑製程形成保護層330。
參照圖6B，在由保護層330a及保護層330保護晶片C1的基底310的同時，通過蝕刻製程EP來薄化晶圓W的基底410。參照圖6C，切割圖6B所示經接合結構以形成經接合單元502，將經接合單元502放置在載板504上，且通過包封材料512包封經接合單元502。參照圖6D，對保護層330a、保護層330及包封材料512進行研磨直到導電柱316、416的頂表面及導電杆510的頂表面被暴露出為止。在一些實施例中，在研磨之後，保護層330a位於晶片C1的側壁上且位於晶片C1與保護層330之間。參照圖6E，在保護層330、330a的頂表面、包封材料512的頂表面及導電杆510的頂表面上形成重佈線路結構514。接著，將所形成結構從載板504剝離，且形成介電層508中的多個導電端子516及多個接觸開口518，以形成封裝。
圖7A到圖7D是繪示根據一些實施例的形成半導體結構 的方法的示意圖。參照圖7A，對第一晶片C1與第二晶片C2進行接合以形成經接合單元502，並在晶片C1上形成保護層330。在一些實施例中，晶片C1包括基底310、介電層312及位於介電層312中的多個焊墊314。在一些實施例中，晶片C2包括基底410、介電層412、位於介電層412中的多個焊墊414及電連接到焊墊414上的多個穿孔418。在一些實施例中，在基底310的側壁310a上形成保護層330，且暴露出基底310的表面310b。在一些實施例中，保護層330的材料相似於圖2B所示保護層130的材料。在一些實施例中，保護層330的材料包含例如模塑化合物(例如，環氧模塑化合物(EMC))、模塑底部填充膠、樹脂、環氧樹脂及/或類似物等包封材料，且可通過模塑製程形成保護層330。在一些實施例中，可通過以下方式形成具有保護層330的經接合單元502：將多個晶片C1接合到包括多個晶片C2的晶圓以形成經接合結構；形成保護材料以包封晶片C1；可選地研磨保護材料以形成保護層；以及切割經接合結構。
參照圖7B，將經接合單元502放置在上面形成有多個導電杆510的載板504上。在一些實施例中，將晶片C1設置在晶片C2與載板504之間。
參照圖7C，將經接合單元502包封(模塑)在包封材料512中。在一些實施例中，將保護層330在晶片C2下面設置在晶片C1與包封材料512之間。接著，通過蝕刻製程EP來薄化晶片C2的基底410直到穿孔418的頂表面被暴露出為止。在一些實施 例中，蝕刻製程EP為濕式蝕刻製程。在薄化製程期間，晶片C1的基底310由保護層330及包封材料512保護，且因此基底310不會因在蝕刻製程EP中所使用的蝕刻劑而受到損傷。在此之後，對包封材料512進行研磨直到導電杆510的頂表面被暴露出且與晶片C2的頂表面共面為止。
參照圖7D，在包封材料512的頂表面及導電杆510的頂表面上形成重佈線路結構514。接著，將所形成結構從載板504剝離，且形成介電層508中的多個導電端子516及多個接觸開口518，以形成封裝。
應注意，保護層330被例示成單層，但本發明並非僅限於此。在一些替代實施例中，如圖8中所示，在保護層330與晶片C1之間形成另一保護層330a。換句話說，所述保護層包括例如保護層330等第一層及例如保護層330a等第二層。在一些實施例中，在晶片C1中的每一者上形成保護層330a，且在接合到晶片C2(或包括多個晶片C2的晶圓)之後，形成保護層330以包封晶片C1，且可選地對保護層330及保護層330a進行研磨以形成所述保護層。在一些實施例中，保護層330a的材料相似於圖2B所示保護層130的材料，且保護層330a的材料不同於保護層330的材料。在一些實施例中，保護層330包含例如模塑化合物(例如，環氧模塑化合物(EMC))、模塑底部填充膠、樹脂、環氧樹脂及/或類似物等包封材料，且可通過模塑製程形成保護層330。
在一些實施例中，通過蝕刻製程而非研磨製程來薄化安 裝在載板上的晶片的基底。因此，防止因研磨製程而對經接合單元的內部結構造成損傷。因此，由經接合結構形成的封裝的性質可得到改善。另外，在一些實施例中，保護層可用作晶片(即，晶片C1)旁邊的包封體且因此所述包封體不是額外形成的，且製造半導體結構的成本或時間不會增加。
圖9A到圖9G是繪示根據一些實施例的形成半導體結構的方法的示意圖。參照圖9A，提供晶圓W。晶圓W包括基底410、介電層420、位於介電層420中的多個導電圖案422及形成在基底410中且電連接到導電圖案422的多個穿孔418。另外，晶圓W還包括多個導電圖案424及介電層426，且導電圖案424形成在介電層426中且被介電層426覆蓋以電連接到導電圖案422。
參照圖9B，將晶圓W放置在載板428上，且對基底410進行研磨直到穿孔418被暴露出為止。在一些實施例中，介電層426設置在載板428與基底410之間，且晶圓W的表面被載板428覆蓋。舉例來說，載板428是玻璃基底。接著，在穿孔418中的一些穿孔418上形成電連接到所述一些穿孔418的位於介電層430中的多個焊墊414，且在介電層430上形成介電層412。
參照圖9C，將晶片C1接合到晶圓W，且在晶圓W之上形成包封材料500以包封晶片C1。晶片C1包括基底310、介電層312及多個焊墊314。另外，晶片C1還包括凸塊318，凸塊318形成在焊墊314上且從介電層312突出。
參照圖9D，通過蝕刻製程EP來薄化晶片C1的基底310。 在一些實施例中，在蝕刻製程EP期間，晶圓W的表面被載板428覆蓋。在一些實施例中，儘管當使用蝕刻劑蝕刻晶片C1的基底310時晶圓W的基底410相對於晶片C1的基底310具有相似的蝕刻選擇性，然而由於基底410由載板428保護，因此晶圓W的基底410不因蝕刻製程EP而受到損傷。換句話說，在一些實施例中，在薄化製程期間，將載板428用作保護層。
參照圖9E，切割圖9D所示經接合結構以形成多個經接合單元502，並將所述多個經接合單元502從載板428剝離。經接合單元502包括晶片C1、覆蓋晶片C1的包封材料500及從晶圓W切割出的晶片C2。接著，將經接合單元502放置在上面形成有多個導電杆510的載板504上。在一些實施例中，將晶片C1設置在晶片C2與載板504之間。
參照圖9F，將經接合單元502包封(模塑)在包封材料512中，並對包封材料512及介電層426進行研磨直到導電圖案424的頂表面及導電杆510的頂表面被暴露出為止。
參照圖9G，在導電杆510的頂表面、包封材料512的頂表面及導電圖案424的頂表面上形成重佈線路結構514。接著，將所形成結構從載板504剝離，且形成介電層508中的多個導電端子516及多個接觸開口518，以形成封裝。
在一些實施例中，使用載板作為晶圓的基底的保護層，通過蝕刻製程而非研磨製程來薄化接合到所述晶圓的晶片的基底。因此，防止因研磨製程而對經接合結構的內部結構造成損傷。 因此，由經接合結構形成的封裝的性質可得到改善。另外，由於載板用作保護層，因此所述保護層不是額外形成的，且製造半導體結構的成本或時間不會增加。
一種半導體結構包括第一晶粒、第二晶粒、第一包封材料及保護層。第一晶粒包括第一基底。第二晶粒接合到第一晶粒且包括第二基底。第一包封材料包封第一晶粒。保護層設置在第一基底的側壁上且設置在所述第一基底與第一包封材料之間，其中所述保護層的材料不同於第二基底的材料及所述第一包封材料的材料。
根據一些實施例，其中所述第一基底及所述第二基底是矽基底。
根據一些實施例，其中所述保護層的所述材料包含氧化矽、氮化矽或它們的組合。
根據一些實施例，其中所述保護層還設置在所述第一基底的表面上，且所述表面與上面設置有所述第二晶粒的表面相對。
根據一些實施例，其中所述保護層直接接觸所述第一基底。
根據一些實施例，還包括包封所述第一晶粒及所述第二晶粒的第二包封材料，其中所述第一包封材料設置在所述第二包封材料與所述保護層之間。
一種形成半導體結構的方法包括以下步驟。提供第一基底。形成保護層，以覆蓋所述第一基底的暴露表面。提供第二基 底，其中所述保護層的材料不同於所述第二基底的材料。對所述第一基底與所述第二基底進行接合。在由所述保護層保護所述第一基底的同時，通過蝕刻製程來薄化所述第二基底。
根據一些實施例，其中所述蝕刻製程是濕式蝕刻製程。
根據一些實施例，其中形成所述保護層包括在所述第一基底的表面上形成所述保護層，且所述表面與上面設置有所述第二基底的表面相對。
根據一些實施例，其中所述保護層是載板。
根據一些實施例，其中所述保護層形成在所述第一基底的側壁上。
根據一些實施例，其中所述第一基底包括位於所述第一基底之上的第一焊墊，所述第二基底包括位於所述第二基底之上的第二焊墊，且所述第一基底與所述第二基底通過所述第一焊墊與所述第二焊墊進行接合。
根據一些實施例，在所述接合步驟之後，所述方法還包括：在所述第一基底與所述第二基底之間形成介電材料以包封所述第一焊墊及所述第二焊墊。
根據一些實施例，其中所述第一焊墊包括凹陷，所述第二基底還包括凸塊，所述凸塊電連接到所述第二焊墊，且在所述接合步驟中，所述方法還包括將所述凸塊插入到所述凹陷中以電連接到所述第一焊墊。
一種形成半導體結構的方法包括以下步驟。提供第一晶 粒，其中所述第一晶粒包括第一基底。在所述第一基底的暴露表面上形成保護層。提供晶圓，其中所述晶圓包括第二基底及多個晶粒區域，其中所述保護層的材料不同於所述第二基底的材料。將所述第一晶粒接合到所述晶圓的所述多個晶粒區域中的一者，以形成經接合結構。在由所述保護層保護所述第一基底的同時，通過蝕刻製程來薄化所述第二基底。切割所述經接合結構以形成經接合單元，其中所述經接合單元包括所述第一晶粒及從所述晶圓的所述多個晶粒區域中的一者切割出的第二晶粒。將所述經接合單元放置到載板上。形成包封材料以包封所述經接合單元。對所述包封材料及所述經接合單元執行平坦化製程。將所述經接合單元從所述載板剝離。
根據一些實施例，其中所述保護層形成在所述第一基底的側壁及表面上，且所述表面與上面設置有所述第二晶粒的表面相對。
根據一些實施例，其中所述第二晶粒設置在所述第一晶粒與所述載板之間，且執行所述平坦化製程包括移除所述經接合單元的所述第一基底的所述表面上的所述保護層。
根據一些實施例，其中所述第一晶粒設置在所述第二晶粒與所述載板之間，且所述平坦化製程與所述薄化製程是通過所述蝕刻製程對所述第二晶粒的所述第二基底的表面及所述包封材料的表面同時執行的。
根據一些實施例，其中所述保護層的材料包含包封材料。
根據一些實施例，其中所述保護層包括第一側及位於所述第一層與所述第一晶粒之間的第二層，且所述第一層的材料與所述第二層的材料不相同。
以上概述了若干實施例的特徵，以使所屬領域中的技術人員可更好地理解本發明的各個方面。所屬領域中的技術人員應知，其可容易地使用本發明作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或實現與本文中所介紹的實施例相同的優點。所屬領域中的技術人員還應認識到，這些等效構造並不背離本發明的精神及範圍，而且他們可在不背離本發明的精神及範圍的條件下對其作出各種改變、代替及變更。
110:基底
110a:側壁
110b:表面
112:介電層
116:焊墊
120:擴散障壁層
122、216:介電層
124、218:導電層
126:間隙
130:保護層
210:基底
212:介電層
214:焊墊
220:凸塊
EP:蝕刻製程

Claims (10)

  1. 一種半導體結構，包括：第一晶粒，包括第一基底；第二晶粒，接合到所述第一晶粒且包括第二基底；第一包封材料，包封所述第一晶粒；以及保護層，設置在所述第一基底的側壁上且設置在所述第一基底與所述第一包封材料之間，其中所述保護層的上表面與下表面分別與所述第一晶粒的上表面與下表面實質上齊平，所述保護層的材料不同於所述第二基底的材料及所述第一包封材料的材料。
  2. 如申請專利範圍第1項所述的半導體結構，其中所述保護層直接接觸所述第一基底。
  3. 如申請專利範圍第1項所述的半導體結構，還包括包封所述第一晶粒及所述第二晶粒的第二包封材料，其中所述第一包封材料設置在所述第二包封材料與所述保護層之間。
  4. 一種半導體結構，包括：第一基底，包括設置在其上的第一焊墊，所述第一焊墊包括內部分以及高於所述內部分且環繞所述內部分的外部分；第二基底，包括設置在其上的凸塊，其中所述凸塊結合所述內部分且被所述外部分環繞；以及介電材料，設置在所述第一基底與所述第二基底之間以包封所述第一焊墊及所述凸塊。
  5. 如申請專利範圍第4項所述的半導體結構，還包括設置在所述第一基底的表面上的保護層，其中所述介電材料設置在所述第一焊墊的所述外部分與所述凸塊之間。
  6. 一種半導體結構，包括：第一晶粒，包括第一基底；第二晶粒，結合至所述第一晶粒且包括第二基底，其中所述第一基底在所述第二基底的上表面上的投影面積小於所述第二晶粒的所述上表面的面積；保護層，設置在所述第一基底的側壁及上表面上，其中所述保護層未覆蓋所述第二基底的側壁；第一包封材料，包封所述第一晶粒及所述保護層，其中所述保護層的材料不同於所述第一包封材料的材料；重佈線路結構，設置在所述第一晶粒及所述第二晶粒上；以及多個導電端子，設置在所述重佈線路結構上且電連接到所述重佈線路結構。
  7. 如申請專利範圍第6項所述的半導體結構，其中所述第一包封材料的側壁與所述第二基底的所述側壁實質上齊平。
  8. 一種形成半導體結構的方法，包括：提供包括第一焊墊的第一基底，所述第一焊墊包括凹陷；形成保護層，以覆蓋所述第一基底的暴露表面； 提供第二基底，所述第二基底包括第二焊墊及電連接到所述第二焊墊的凸塊，其中所述保護層的材料不同於所述第二基底的材料；通過將所述凸塊插入到所述凹陷中以電連接到所述第一焊墊對所述第一基底與所述第二基底進行結合；以及在由所述保護層保護所述第一基底的同時，通過蝕刻製程來薄化所述第二基底。
  9. 一種形成半導體結構的方法，包括：提供第一晶粒，其中所述第一晶粒包括第一基底；在所述第一基底的暴露表面上形成保護層；提供晶片，其中所述晶片包括第二基底及多個晶粒區域，其中所述保護層的材料不同於所述第二基底的材料；將所述第一晶粒結合到所述晶片的所述多個晶粒區域中的一者，以形成經結合結構；在由所述保護層保護所述第一基底的同時，通過蝕刻製程來薄化所述第二基底；切割所述經結合結構以形成經結合單元，其中所述經結合單元包括所述第一晶粒及從所述晶片的所述多個晶粒區域中的一者切割出的第二晶粒；將所述經結合單元放置到載板上；形成包封材料以包封所述經結合單元；對所述包封材料及所述經結合單元執行平坦化製程；以及將所述經結合單元從所述載板剝離。
  10. 一種形成半導體結構的方法，包括： 結合第一晶粒與第二晶粒，所述第一晶粒包括第一基底，所述第二晶粒包括第二基底，在所述第一基底的側壁上形成保護層；以第一包封材料包封所述第一晶粒及所述保護層，其中所述保護層的材料不同於所述第二基底及所述第一包封材料的材料，以及在由所述保護層與所述第一包封材料保護所述第一基底的同時，薄化所述第二基底。
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