TW202117955A - 半導體封裝及其製造製程 - Google Patents

半導體封裝及其製造製程 Download PDF

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TW202117955A
TW202117955A TW109105499A TW109105499A TW202117955A TW 202117955 A TW202117955 A TW 202117955A TW 109105499 A TW109105499 A TW 109105499A TW 109105499 A TW109105499 A TW 109105499A TW 202117955 A TW202117955 A TW 202117955A
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die
interposer
crystal
wafer
degrees
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TW109105499A
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TWI720822B (zh
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朱立寰
陳旭賢
林亮臣
謝宗揚
李信賢
蔡坤宏
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台灣積體電路製造股份有限公司
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Abstract

本發明提供一種封裝製程及半導體封裝。提供具有晶體結構的中介層。將第一晶粒及第二晶粒接合在所述中介層上。將第二晶粒定位成通過間隙而與第一晶粒間隔開，所述間隙具有垂直於間隙的最短距離的間隙延伸方向，且所述間隙延伸方向不平行於中介層的晶體結構的結晶取向。在中介層之上形成覆蓋第一晶粒及第二晶粒的模製化合物。將模製化合物及中介層切割成封裝。

Description

半導體封裝及其製造製程
在先進的封裝製程中，半導體封裝可通過晶片-晶圓接合製程（chip-to-wafer bonding process）將多個晶片整合到含有穿孔的中介層上，且可將總成（assemblies）安裝到基底上。封裝的結構強度及完整性的提高使得實現更好的可靠性及高的良率。
以下公開提供用於實施所提供主題的不同特徵的許多不同的實施例或實例。以下闡述組件及佈置的具體實例以簡化本公開。當然，這些僅為實例且不旨在進行限制。舉例來說，在以下說明中，在第二特徵之上或第二特徵上形成第一特徵可包括其中第一特徵與第二特徵被形成為直接接觸的實施例，且也可包括其中第一特徵與第二特徵之間可形成附加特徵從而使得第一特徵與第二特徵可不直接接觸的實施例。另外，本公開在各種實例中可重複使用參考編號和/或字母。此種重複使用是出於簡明及清晰的目的，而不是自身指示所論述的各個實施例和/或配置之間的關係。
此外，為易於說明，本文中可能使用例如“在…之下”、“在…下方”、“下部的”、“在…上方”、“上部的”等空間相對性用語來闡述圖中所示一個元件或特徵與另一（其他）元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的取向外還囊括裝置在使用或操作中的不同取向。設備可具有其他取向（旋轉90度或處於其他取向），且本文中所使用的空間相對性描述語可同樣相應地進行解釋。
還可包括其他特徵及製程。舉例來說，可包括測試結構以幫助對三維（three-dimensional，3D）封裝或三維積體電路（three-dimensional integrated circuit，3DIC）裝置進行驗證測試。所述測試結構可包括例如在重佈線層中或基底上形成的測試焊盤（test pad），以便能夠對3D封裝或3DIC進行測試、使用探針和/或探針卡（probe card）等。可對中間結構以及最終結構執行驗證測試。另外，本文中所公開的結構及方法可與包含對已知良好晶粒（known good die）進行中間驗證的測試方法結合使用以提高良率並降低成本。
對於本文中提供的實施例來說，可在特定的上下文（即，相對於下伏結晶半導體晶圓中介層的結晶方向而在特定方向上佈置晶粒或晶片）中論述所述技術。通過晶粒的佈置及佈局設計，使應力位置不平行於下伏中介層的結晶取向且使較小或最小的應力沿著結晶取向傳遞，從而可避免或減少由於在加熱製程期間封裝結構的翹曲而引起的下伏結晶半導體晶圓中介層的可能的開裂。這通過降低中介層開裂的可能性來實現更可靠的封裝結構。晶粒與下伏結晶半導體晶圓中介層的相對取向可減輕或緩和由熱膨脹係數（coefficient of thermal expansion，CTE）失配引起的翹曲而造成的影響。
封裝製程可包括使用基底上晶圓上晶片（Chip-on-Wafer-on-Substrate，CoWoS）封裝處理來形成多晶片封裝結構。其他實施例也可包括其他處理（包括晶圓級封裝處理或疊層封裝（package-on-package）總成處理）。本文中所論述的實施例是為了提供能夠製作或使用本公開主題的實例，且所屬領域中的一般技術人員將容易地理解，在保持處於不同實施例的預期範圍內的同時可作出修改。以下各圖中相同的參考編號及字符指代相同的組件。儘管方法實施例可被論述為以特定次序執行，然而其他方法實施例可以任何邏輯次序執行。
圖1到圖6是根據本公開一些示例性實施例的封裝結構的製造方法中各個階段的示意圖。
在圖1中，提供中介層200。在一些實施例中，中介層200中包括半導體基底202及穿孔204。在圖1中，並沒有示出整個中介層200，而是僅示出包括一個或多個封裝單元PKU的中介層200的一部分，且中介層中的穿孔的數目並非僅限於圖中所示的示例性實例。在一些實施例中，在基底202上以及穿孔204之上形成重佈線結構210。在一些實施例中，基底202可包括塊狀半導體材料基底、絕緣體上矽（silicon on insulator，SOI）基底或多層式半導體材料基底。半導體基底202的半導體材料可為矽、鍺、矽鍺、碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、銻化銦、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP或其組合。在一些實施例中，基底202可為經摻雜或未經摻雜的。在一些實施例中，基底202可摻雜有P型摻雜劑（例如硼（B）、鋁（A1）或鎵（Ga））或者摻雜有N型摻雜劑（例如磷（P）、砷（As）或銻（Sb））。在一些實施例中，中介層200包括具有晶體結構的塊狀半導體晶圓。在一個實施例中，中介層200可為具有晶體結構（例如立方晶體結構）的塊狀矽晶圓。
在一些實施例中，在基底202中形成穿透過基底202的穿孔204。在一些實施例中，如圖1中所示，穿孔204是基底穿孔。在一些實施例中，當基底202包括矽基底時，穿孔204是矽穿孔。在一些其他實施例中，穿孔204可延伸到基底202中而不穿透過基底202，且在稍後的階段，可從背側將基底202減薄以暴露出穿孔204的端部。在圖1中，在此階段，中介層200已經變薄且穿孔204的端部被暴露出。儘管圖中未示出，然而應理解，可在中介層200之下提供載體或玻璃載體以用於支撐目的。在一些實施例中，可通過在基底202中形成孔或凹槽（recess）且接著使用導電材料填充凹槽來形成穿孔204。在一些實施例中，可通過例如蝕刻、銑削（milling）、雷射鑽孔等形成凹槽。在一些實施例中，可通過電化學鍍覆製程（electro-chemical plating process）、化學氣相沉積（chemical vapor deposition，CVD）、原子層沉積（atomic layer deposition，ALD）或物理氣相沉積（physical vapor deposition，PVD）形成導電材料，且導電材料可包括銅、鎢、鋁、銀、金或其組合。
從具有規則晶體結構的晶體生長晶圓。結晶平面及結晶方向由米勒指數（Miller Indices）（例如（100）、（111）、（110）等）描述。在對稱的晶格（crystal lattice）中，某些方向彼此對等，且對等方向或平面的群組被稱為族（family）。舉例來說，在立方晶體系統中，方向[100]、[010]及[001]屬於>100>族。晶圓的晶體取向以兩種方式加以規定：晶圓表面的平面的取向及晶圓主平面（wafer primary flat）的位置（位於晶圓的圓周中的最長長度的平直側）。對於常用的晶圓（p型及n型（100）及（111）晶圓），主平面與[110]方向對齊。作為另外一種選擇，對於較大大小的晶圓，在製作期間使用凹口（notch）而不是主平面來標記晶圓的取向。舉例來說，可使用指向[011]方向的凹口沿著{100}平面切割（100）矽晶圓，以對晶圓進行取向。
在一些實施例中，塊狀矽晶圓是具有晶體結構的矽晶圓，且結晶矽晶圓的表面的結晶取向可為（100）或（111）。在一個實施例中，塊狀矽晶圓是具有在（100）晶體平面上取向的晶圓的頂表面且具有與[110]方向對齊的主平面的（100）晶圓。在圖7A中對（100）矽晶圓的晶體取向進行闡述，而圖7B示出晶圓在>110>方向上的方向以及自然X軸及Y軸。對於（100）矽晶圓，X軸的方向是[110]方向，Y軸的方向是[-110]方向，且與（100）的頂表面正交的方向是[100]方向，[100]方向可被視為XYZ坐標系統的自然Z軸。
在一些實施例中，提供具有晶體結構的中介層200，接著確定中介層200的晶體結構的結晶取向。在一個實施例中，可基於晶圓的主平面對中介層200進行取向，且確定中介層200的晶體結構的結晶取向（例如X軸及Y軸）。
在一些實施例中，形成在基底202上的重佈線結構210包括交替堆疊的金屬圖案206a、206b、206c與介電層208a、208b、208c。在一些實施例中，金屬圖案206a可包括與穿孔204連接的導電部分，且金屬圖案206c可包括用作凸塊焊盤和/或凸塊下金屬（under bump metallurgy，UBM）的導電部分。在一些實施例中，介電層208a、208b、208c的材料可包括聚合材料（包括聚醯亞胺（polyimide，PI）、聚苯並噁唑（polybenzoxazole，PBO）、苯並環丁烯（benzocyclobutene，BCB）或任何其他合適的聚合物系介電材料。在一些實施例中，可通過疊層（lamination）、塗布、化學氣相沉積（CVD）等形成介電層208a、208b、208c。在一些實施例中，金屬化圖案206a、206b、206c的形成可包括利用微影技術及一個或多個蝕刻製程將介電層圖案化以及將金屬材料填充到圖案化介電層的開口中。可例如利用化學機械拋光製程來移除介電層上的任何過量的導電材料。在一些實施例中，金屬化圖案206a、206b、206c的材料包括銅、鋁、鎢、銀、鈦及其組合。
在某些實施例中，中介層200還可包括主動元件或被動元件，例如形成在基底202中的電晶體、電容器、電阻器或二極體被動元件。
參照圖2A及圖2B，在中介層200上提供並安裝第一晶粒12及第二晶粒14。圖中僅示出一個第一晶粒及一個第二晶粒作為示例性實例，但第一晶粒及第二晶粒的數目並非僅限於本文中所示的實例。在一些實施例中，第一晶粒12及第二晶粒14是從晶圓單體化而成的各別半導體晶粒。在一些實施例中，各個第一晶粒12含有相同的電路（例如裝置及金屬化圖案），或者各個第一晶粒12是相同類型的晶粒。在一些實施例中，各個第二晶粒14含有相同的電路，或者各個第二晶粒14是相同類型的晶粒。在某些實施例中，第一晶粒12與第二晶粒14具有不同的電路或者是不同類型的晶粒。在替代實施例中，第一晶粒12與第二晶粒14可具有相同的電路。
從在切割道（scribe lane，SL）之間界定的封裝單元PKU來看，第一晶粒12及第二晶粒14在封裝單元PKU的跨度內佈置在中介層200的頂表面200a上，且第一晶粒12與第二晶粒14並排地佈置且彼此間隔開。晶粒的佈局設計或晶粒佈置的位置設計旨在相對於下伏中介層的結晶取向來以特定方式對晶粒進行取向。
在一些實施例中，如圖2B中所示，第一晶粒12是矩形形狀的晶粒，具有兩個相對的側12X及連接所述兩個相對的側12X的另兩個相對的側。另外，第二晶粒14可為矩形形狀的晶粒。在一個實施例中，在每一個封裝單元PKU的一個第一晶粒12旁邊佈置有兩個第二晶粒14。在一個實施例中，每一第二晶粒14通過間距SP的間隙而與第一晶粒12間隔開。在一個實施例中，間距SP可介於40微米到100微米的範圍內。參照圖2B，當第一晶粒12被放置在中介層200上時，第一晶粒12的位置被恰當地選擇成使得第一晶粒12的一個側12X與方向X1對齊（實質上平行於（在製造偏差內）方向X1），且接著第二晶粒14被取向成使第二晶粒14的側對齊成實質上平行於（在製造偏差內）第一晶粒12的側12X且實質上平行於（在製造偏差內）方向X1。從圖2B來看，各個第二晶粒14被佈置成實質上平行的（在製造偏差內）且位於第一晶粒12的側12X旁邊。由於所述兩個第二晶粒14被佈置成通過間隙（例如，具有相同的間距SP）而與第一晶粒12間隔開且所述兩個第二晶粒14沿著方向X1佈置，因此方向X1也是間隙延伸方向。也就是說，第二晶粒14被定位成使第二晶粒14的側對齊成實質上平行於（在製造偏差內）第一晶粒12的側12X，且通過第一晶粒12與第二晶粒14的相互面對的側的佈置，間隙的延伸方向X1（間隙延伸方向X1）被界定成和第一晶粒12與第二晶粒14的相互面對的側平行的方向。在某些實施例中，第一晶粒12與第二晶粒14之間的間隙或間距SP是第一晶粒12與第二晶粒14的所述兩個相互面對的側之間的最短距離，且間隙延伸方向X1實質上垂直於間距SP的方向。當封裝結構中發生翹曲時，晶粒之間存在的間隙是最大應力位置，且應力可沿著間隙的縱向延伸方向傳遞。在一個實施例中，中介層200包括具有如圖7A到圖7B中所示的結晶取向（例如，X、Y、Z軸）的矽（100）晶圓，且第一晶粒12及第二晶粒14以間隙的延伸方向X1不平行於中介層200的自然軸X的方式佈置。通過使應力位置與下伏晶圓中介層的晶格取向失配，應力傳遞方向不平行於晶格取向，從而避免應力傳遞到中介層而導致開裂。也就是說，在間隙延伸方向X1（由第一晶粒與第二晶粒的相互面對的側界定）與中介層200的結晶取向X（即，中介層200的晶圓的自然軸X）之間存在夾角θ，並且夾角θ大於零且小於180度。在一些實施例中，夾角θ介於約60度到約120度的範圍內。在一些實施例中，夾角θ介於75度到約105度的範圍內。在一些實施例中，夾角θ介於85度到約95度的範圍內。在一個實施例中，夾角θ為約90度，方向X1在[-1-10]方向上。當夾角θ為約90度時，傳遞的應力最小並實現更好的抗應力效果。
在某些實施例中，第一晶粒12具有比第二晶粒14的表面積大的表面積。另外，在一些實施例中，第一晶粒12與第二晶粒14可具有不同的大小，從而包括不同的表面積和/或不同的厚度。在一些實施例中，第一晶粒12可為邏輯晶粒，包括中央處理器（central processing unit，CPU）晶粒、圖形處理單元（graphics processing unit，GPU）晶粒、系統晶片（system-on-a-chip，SoC）晶粒、微控制器等。在一些實施例中，第一晶粒12是電源管理晶粒，例如電源管理積體電路（power management integrated circuit，PMIC）晶粒。在一些實施例中，第二晶粒14可為記憶體晶粒，包括動態隨機存取記憶體（dynamic random access memory，DRAM）晶粒、靜態隨機存取記憶體（static random access memory，SRAM）晶粒或高帶寬記憶體（high bandwidth memory，HBM）晶粒。在一些實施例中，第一晶粒12包括形成在第一晶粒12的本體的主動表面上的連接元件122。在某些實施例中，連接元件122還可包括柱結構。在一些實施例中，第二晶粒14包括形成在第二晶粒14的主動表面上的連接元件142。在其他實施例中，連接元件142還可包括柱結構。在一些實施例中，主動晶粒是一個或多個晶粒的堆疊（例如，邏輯晶粒堆疊或記憶體晶粒堆疊）。在這些實施例中，材料、數量和/或大小可不限於實施例中所提供的說明。
在圖2A到圖2B中，例如通過連接元件122、142將第一晶粒12及第二晶粒14以倒裝晶片接合（flip-chip bonding）方式貼合到中介層200的頂表面200a。在某些實施例中，通過執行回流製程將連接元件122、142接合到金屬圖案206c的某些導電部分，從而將晶粒12、14與中介層200電連接及實體連接。在某些實施例中，連接元件122、142可為微凸塊，例如具有銅金屬柱的微凸塊。連接元件122、142通過金屬圖案206a、206b、206c將第一晶粒12及第二晶粒14與中介層200的穿孔204電連接。
在一些實施例中，回流製程被作為接合製程的一部分來執行，以將第一晶粒12及第二晶粒14接合到重佈線結構210上且接合到中介層200。在一個實施例中，連接元件122、142是微凸塊，且回流溫度介於攝氏210度到攝氏250度的範圍內，或者為約攝氏240度。
在一些實施例中，通過以特定方式佈置第一晶粒及第二晶粒而使得第一晶粒與第二晶粒之間的間隙延伸方向不平行於中介層的半導體晶圓的結晶取向，中介層的強度得到提高。由此，中介層強度得到加強，特別是在高溫熱處理（例如回流製程）期間容易發生翹曲的各個晶粒之間的間隙處得到加強，且由於翹曲可能導致的中介層的開裂可顯著減少或被最小化。
在一些實施例中，晶粒12、14與中介層200之間的接合可為焊料接合（solder bonding）。在一些實施例中，晶粒12、14與中介層200之間的接合可為直接的金屬對金屬接合（metal-to-metal bonding），例如銅對銅接合（copper-to-copper bonding）。在一些實施例中，底部填充材料150可配置在晶粒12、14與中介層200之間的間隙之間並環繞晶粒12的連接元件122、晶粒14的連接元件142。
在圖3中，在中介層200之上形成覆蓋第一晶粒12及第二晶粒14、底部填充材料150以及連接元件122、142的包封體240。在一些實施例中，包封體240可為模製化合物。在一些實施例中，包封體240包含環氧樹脂且可通過包覆模製（over-molding）、壓縮模製（compression molding）或轉移模製（transfer molding）形成。在一個實施例中，可執行固化製程以固化包封體240。在一些實施例中，第一晶粒12及第二晶粒14以及連接元件122、142被包封體240包封。在一些實施例中，可執行平坦化製程（包括研磨或拋光）以局部地移除包封體240，從而暴露出第一晶粒12的背側表面12s及第二晶粒14的背側表面14s。在某些實施例中，第一晶粒12的背側表面12s及第二晶粒14的背側表面14s與包封體240的頂表面240a齊平。
在圖4中，將圖3所示結構翻轉或上下顛倒，並放置在載體C上，以使載體C直接接觸第一晶粒12的背側表面12s及第二晶粒14的背側表面14s以及包封體240的頂表面240a。
在圖4中，在中介層200的另一表面200b上形成重佈線結構220。在一些實施例中，重佈線結構220對穿孔204進行電連接且重佈線結構210與220通過穿孔204進行電連接。在某些實施例中，重佈線結構220包括至少一個介電層214及位於介電層214中的金屬化圖案216。在一些實施例中，金屬化圖案216可包括焊盤、通孔和/或跡線以對穿孔204進行內連，並進一步將穿孔204連接到一個或多個導電元件和/或外部裝置。儘管在圖4中示出一層介電層，然而應理解，在重佈線結構內可包括多於一個介電層。在一些實施例中，介電層214的材料可包括聚合材料（包括聚醯亞胺（PI）、聚苯並噁唑（PBO）、苯並環丁烯（BCB）或任何其他合適的聚合物系介電材料）。在一些實施例中，可通過疊層、塗布、CVD等形成介電層214。在一些實施例中，金屬化圖案216的形成可包括：利用微影技術及一個或多個蝕刻製程將介電層圖案化；以及將金屬材料填充到開口中；以及利用化學機械拋光製程對介電層上過量的導電材料進行拋光。在一些實施例中，金屬化圖案216的材料包括銅、鋁、鎢、銀、鈦及其組合。
在圖5中，在重佈線結構220的金屬化圖案216上形成導電連接件250。在一些實施例中，在金屬化圖案216上形成凸塊下焊盤230，且在凸塊下焊盤230上形成導電連接件250。在一些實施例中，凸塊下焊盤230包括凸塊下金屬（UBM）。導電連接件250通過重佈線結構220的金屬化圖案216電耦合到穿孔204。在一些實施例中，導電連接件250位於重佈線結構220的頂表面220a上。在一些實施例中，導電連接件250包括無鉛焊料球、焊料球、球柵陣列（ball grid array，BGA）球、金凸塊、受控塌陷晶片連接（controlled collapse chip connection，C4）凸塊或含有銅柱的微凸塊。在一些實施例中，導電連接件250可包含導電材料，例如焊料、銅、鋁、金、鎳、銀、鈀、錫或其組合。在一些實施例中，通過例如蒸鍍、電鍍、印刷或焊料轉移在重佈線結構300上形成焊料膏且接著使所述焊料膏回流成期望的凸塊形狀來形成導電連接件250。在一些實施例中，通過植球（ball placement）等將導電連接件250放置在重佈線結構300上。在其他實施例中，通過以下方式來形成導電連接件250：通過濺鍍、印刷、無電鍍或電鍍或者CVD來形成無焊料金屬柱（例如銅柱）且接著通過對金屬柱進行鍍覆來形成無鉛頂蓋層。
導電連接件250可用於接合到外部裝置或附加電組件。在一些實施例中，導電連接件250用於接合到電路基底、半導體基底或封裝基底。
在圖5中，在形成導電連接件250之後，執行單體化製程以沿著封裝單元PKU周圍的切割道SL（圖4所示）將晶圓形式結構切割成多個各別封裝50。在一些實施例中，如圖5中所示，每一封裝50包括至少一個第一晶粒12、多於一個的第二晶粒14、環繞第一晶粒12及第二晶粒14的包封體240、連接元件122、142、中介層200的一部分（包括穿孔204）、包括金屬圖案及金屬化圖案216的重佈線結構210、220（在圖5中，被切割的重佈線結構也被稱為重佈線結構）以及設置在重佈線結構220的頂表面220a上的導電連接件250。在一些實施例中，單體化製程可包括刀片鋸切製程（blade sawing process）或晶圓劃切製程（wafer dicing process）。
在單體化製程之後，可將封裝50從載體C分離並轉移到膠帶膜TP。在後續製程中，可將封裝50翻轉並進一步安裝在電路基底或封裝基底上。
在圖6中，提供上面具有安裝部分302的電路基底300。在一些實施例中，電路基底300可包括構成基底（build-up substrate）、疊層基底（laminate substrate）、電路板（例如印刷電路板（printed circuit board，PCB））等。在一些實施例中，安裝部分302可包括形成在電路基底的焊盤上的預焊料（pre-solder）。另外，電路基底300還可包括嵌入在電路基底300中的電接觸件或其他電組件。
在圖6中，將封裝50放置在電路基底300上且通過執行回流製程將封裝50接合到電路基底300。在一些實施例中，拾取封裝50並將封裝50放置在電路基底300的頂表面之上，且封裝50的底表面上的導電連接件250與電路基底300的安裝部分302對齊且設置在電路基底300的安裝部分302上。回流製程被作為對封裝50與電路基底300進行的接合製程的一部分來執行，以將導電連接件250接合到安裝部分302。在一些實施例中，回流製程包括執行熱處理以將導電連接件250轉變成熔化狀態或半熔化狀態，從而與電路基底300的安裝部分302整合及接合。導電連接件250的回流溫度需要高於導電連接件250的熔點。在一個實施例中，導電連接件250是C4凸塊，且回流溫度介於攝氏210度到攝氏250度的範圍內。在一個實施例中，導電連接件250是焊料球或無鉛焊料球，且回流溫度介於攝氏200度到攝氏260度的範圍內。
在一些實施例中，封裝50具有接合在中介層200上的第一晶粒12及位於第一晶粒12周圍的第二晶粒14。如圖2A及圖2B中所示，通過以特定方式佈置第一晶粒12及第二晶粒14來確保第一晶粒12與第二晶粒14之間的間隙延伸方向X1不平行於中介層的半導體晶圓的結晶取向，中介層結構的強度會得到提高。在回流製程期間的熱衝擊下，甚至是由於CTE失配，封裝50（及晶粒12、14）的翹曲也可隨著中介層強度的提高而變得更少，且中介層結構可發生更少開裂或不發生開裂。
通過調整半導體中介層上的半導體晶粒的佈置或對齊，封裝結構的結構強度會得到提高。由於由間隔開的晶粒界定的間隙延伸方向被預先佈置成不平行於中介層的晶體結構的結晶取向，因此與間隙延伸方向和下面的中介層的結晶取向平行的晶粒的佈置相比，結晶中介層的強度提高了20%。因此，回流期間中介層開裂的問題可顯著減少。因此，大大增強了封裝的可靠性且極大增加了生產良率。
圖8A是示出根據本公開實施例的封裝及電路基底的示意性剖視圖。圖8B是示出根據本公開實施例的封裝中的中介層上的晶粒的佈置的示意性俯視圖。
在圖8A中，封裝50A通過導電連接件250接合在電路基底300上。在一些實施例中，封裝50A是具有尺寸較大的第一晶粒12A及佈置在第一晶粒12A周圍的若干第二晶粒14A的CoWoS封裝，且電路基底300還包括用於外部連接的導電球80。在此種實施例中，在封裝50A中的一個第一晶粒12A旁邊及周圍佈置有四個第二晶粒14A，且兩組各兩個第二晶粒14A平行地佈置且分別佈置在第一晶粒12A的兩個相對的側12X旁邊，如圖8B中所示。在一些實施例中，第一晶粒12A可為邏輯晶粒，包括中央處理器（CPU）晶粒、圖形處理單元（GPU）晶粒、系統晶片（SoC）晶粒、微控制器等。在一些實施例中，第一晶粒12A是電源管理晶粒，例如電源管理積體電路（PMIC）晶粒。在一些實施例中，第二晶粒14A可為記憶體晶粒，包括動態隨機存取記憶體（DRAM）晶粒、靜態隨機存取記憶體（SRAM）晶粒或高帶寬記憶體（HBM）晶粒。
在一個實施例中，第二晶粒14A通過間隙或間距SP而與第一晶粒12A間隔開，且存在由第一晶粒12A與第二晶粒14A的相互面對的側界定的間隙延伸方向X1。在一個實施例中，中介層200可具有晶體結構，晶體結構具有結晶取向X，如圖8B中所示，且在間隙延伸方向X1（由第一晶粒與第二晶粒的相互面對的側界定）與中介層200的結晶取向X之間存在夾角θ，且夾角θ大於零且小於180度。在一些實施例中，夾角θ介於約60度到約120度的範圍內。在一些實施例中，夾角θ介於75度到約105度的範圍內。在一些實施例中，夾角θ介於85度到約95度的範圍內。在一個實施例中，夾角θ為約90度。
在實施例中，通過晶粒的位移，晶粒之間的間隙被設計成具有不與中介層的下面的晶體結構的結晶取向平行的延伸方向。在某些實施例中，封裝的中介層的強度得到提高且封裝的結構可靠性得到增強。
根據本公開的一些實施例，提供一種製造製程。提供具有晶體結構的中介層。在將第一晶粒設置在所述中介層上之後，將第二晶粒設置在所述中介層上。將所述第二晶粒定位成通過間隙而與所述第一晶粒間隔開且界定所述間隙的間隙延伸方向。所述間隙延伸方向不平行於所述中介層的所述晶體結構的結晶取向。將所述第一晶粒及所述第二晶粒接合到所述中介層。在所述中介層之上形成覆蓋所述第一晶粒及所述第二晶粒的模製化合物。將所述模製化合物及所述中介層切割成封裝。
根據本公開的一些替代實施例，一種封裝製程包括以下步驟。提供具有晶體結構的晶圓中介層且確定所述晶體結構的結晶取向。將第一晶粒設置在所述晶圓中介層上且將每一第一晶粒的一側取向成與第一方向平行。所述第一方向被取向成在所述結晶取向與所述第一方向之間具有夾角θ，且所述夾角θ大於零且小於90度。將第二晶粒設置在所述晶圓中介層上且將每一第二晶粒的一側取向成與所述第一方向平行。所述第二晶粒設置在所述第一晶粒旁邊且通過間隙而與所述第一晶粒間隔開，且所述間隙在所述第一方向上延伸。將所述第一晶粒及所述第二晶粒接合到所述晶圓中介層。在所述晶圓中介層之上形成覆蓋所述第一晶粒及所述第二晶粒的模製化合物。將所述模製化合物及所述晶圓中介層切成封裝。
根據本公開的一些實施例，闡述一種封裝結構。所述封裝結構包括半導體中介層、第一晶粒及第二晶粒以及導電連接件。所述半導體中介層具有晶體結構且具有第一表面及與所述第一表面相對的第二表面。所述半導體中介層包括從所述第一表面延伸到所述第二表面的穿孔（204）。所述第一晶粒設置在所述半導體中介層的所述第一表面上且與所述穿孔電連接。所述第二晶粒設置在所述半導體中介層的所述第一表面上、設置在所述第一晶粒旁邊且與所述穿孔電連接。所述第一晶粒與所述第二晶粒通過所述第一晶粒與所述第二晶粒之間的間隙而隔開，且所述第一晶粒與所述第二晶粒的相互面對的側界定所述間隙的間隙延伸方向。所述間隙延伸方向不平行於所述半導體中介層的所述晶體結構的結晶取向。所述導電連接件設置在所述半導體中介層的所述第二表面上且與所述穿孔電連接。
以上概述了若干實施例的特徵，以使所屬領域中的技術人員可更好地理解本公開的各個方面。所屬領域中的技術人員應理解，他們可容易地使用本公開作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的和/或實現與本文中所介紹的實施例相同的優點。所屬領域中的技術人員還應認識到，這些等效構造並不背離本公開的精神及範圍，而且他們可在不背離本公開的精神及範圍的條件下對其作出各種改變、代替及變更。
12:第一晶粒/晶粒 12A:第一晶粒 12s、14s:背側表面 12X:側 14:第二晶粒/晶粒 14A:第二晶粒 50、50A:封裝 80:導電球 122、142:連接元件 150:底部填充材料 200:中介層 200a、220a、240a:頂表面 202:半導體基底/基底 200b:表面 204:穿孔 206a、206b、206c:金屬圖案/金屬化圖案 208a、208b、208c、214:介電層 210、220:重佈線結構 216:金屬化圖案 230:凸塊下焊盤 240:包封體 250:導電連接件 260:底部填充材 300:重佈線結構/電路基底 302:安裝部分 （100）:晶片 [001]、[010]、[011]、[100]、[110]、[-110]、[-1-10]:方向 {100}:平面 C:載體 PKU:封裝單元 SL:切割道 SP:間距 TP:膠帶膜 X:軸/自然軸/結晶取向 X1、Y1:方向 Y:軸 θ:夾角
結合附圖閱讀以下詳細說明，會最好地理解本公開的各個方面。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為使論述清晰起見，可任意增大或減小各種特徵的尺寸。 圖1、圖2A及圖3到圖6是根據本公開一些示例性實施例的封裝結構的製造方法中各個階段的示意性剖視圖。 圖2B是示出根據本公開一些實施例的中介層上的晶粒的位置的示意圖。 圖7A及圖7B示出（100）晶圓的結晶取向。 圖8A是示出根據本公開實施例的封裝及電路基底的示意性剖視圖。 圖8B是示出根據本公開實施例的中介層上的晶粒的位置的示意圖。
12:第一晶粒/晶粒
12X:側
14:第二晶粒/晶粒
200:中介層
SP:間距
X1、Y1:方向

Claims (20)

  1. 一種製造製程，包括： 提供具有晶體結構的中介層； 將第一晶粒設置在所述中介層上； 將第二晶粒設置在所述中介層上，並且將所述第二晶粒定位成通過間隙而與所述第一晶粒間隔開且界定與所述間隙的最短距離垂直的間隙延伸方向，其中所述間隙延伸方向不平行於所述中介層的所述晶體結構的結晶取向； 將所述第一晶粒及所述第二晶粒接合到所述中介層； 在所述中介層之上形成覆蓋所述第一晶粒及所述第二晶粒的模製化合物；以及 切割透所述模製化合物及所述中介層以形成封裝。
  2. 如申請專利範圍第1項所述的製程，其中將所述第一晶粒及所述第二晶粒接合到所述中介層包括執行回流製程。
  3. 如申請專利範圍第2項所述的製程，其中所述第一晶粒及所述第二晶粒通過微凸塊接合到所述中介層，且所述回流製程是在介於約攝氏210度到約攝氏250度的範圍內的回流溫度下執行的。
  4. 如申請專利範圍第1項所述的製程，還包括：在所述封裝的被切割的所述中介層上形成導電連接件，其中被切割的所述中介層中包括穿孔且所述導電連接件與所述穿孔電連接。
  5. 如申請專利範圍第4項所述的製程，還包括：提供電路基底且通過執行回流製程將所述封裝的所述導電連接件接合到所述電路基底。
  6. 如申請專利範圍第5項所述的製程，其中所述導電連接件是受控塌陷晶片連接凸塊，且所述回流製程是在介於約攝氏210度到約攝氏250度的範圍內的回流溫度下執行的。
  7. 如申請專利範圍第4項所述的製程，還包括：在形成所述導電連接件之前，在所述中介層上形成重佈線結構。
  8. 如申請專利範圍第1項所述的製程，其中所述第一晶粒包括至少一個邏輯晶粒，且所述第二晶粒包括至少一個記憶體晶粒。
  9. 如申請專利範圍第1項所述的製程，還包括：在設置所述第一晶粒及設置所述第二晶粒之前，在所述中介層上形成重佈線結構。
  10. 一種封裝製程，包括： 提供具有晶體結構的晶圓中介層； 將第一晶粒及第二晶粒接合在所述晶圓中介層上且使所述第一晶粒與所述第二晶粒通過所述第一晶粒的一側與所述第二晶粒的一側之間的間隙彼此間隔開，所述第一晶粒的所述一側與所述第二晶粒的所述一側實質上平行於第一方向，其中所述第一方向被取向成在所述晶圓中介層的所述晶體結構的結晶取向與所述第一方向之間具有夾角θ，且所述夾角θ大於零且小於180度； 在所述晶圓中介層之上形成覆蓋所述第一晶粒及所述第二晶粒的模製化合物；以及 切透所述模製化合物及所述晶圓中介層以形成封裝。
  11. 如申請專利範圍第10項所述的製程，其中所述晶圓中介層包括具有立方晶體結構的矽晶圓。
  12. 如申請專利範圍第10項所述的製程，其中所述夾角θ介於約60度到約120度的範圍內。
  13. 如申請專利範圍第10項所述的製程，其中所述夾角θ介於約85度到約95度的範圍內。
  14. 如申請專利範圍第1項所述的製程，其中將所述第一晶粒及所述第二晶粒接合到所述晶圓中介層包括執行回流製程。
  15. 如申請專利範圍第14項所述的製程，其中所述第一晶粒及所述第二晶粒通過微凸塊接合到所述晶圓中介層，且所述回流製程是在介於約攝氏210度到約攝氏250度的範圍內的回流溫度下執行的。
  16. 一種封裝結構，包括： 半導體中介層，具有晶體結構，其中所述半導體中介層具有第一表面及與所述第一表面相對的第二表面，且所述半導體中介層包括從所述第一表面延伸到所述第二表面的穿孔； 第一晶粒及第二晶粒，分別設置在所述半導體中介層的所述第一表面上且與所述穿孔電連接；其中所述第一晶粒與所述第二晶粒通過所述第一晶粒的一側與所述第二晶粒的一側之間的間隙彼此間隔開，所述第一晶粒的所述一側與所述第二晶粒的所述一側實質上平行於第一方向，且所述第一方向不平行於所述半導體中介層的所述晶體結構的結晶取向；以及 導電連接件，設置在所述半導體中介層的所述第二表面上且與所述穿孔電連接。
  17. 如申請專利範圍第16項所述的結構，其中所述第一晶粒包括至少一個邏輯晶粒，且所述第二晶粒包括至少一個記憶體晶粒。
  18. 如申請專利範圍第16項所述的結構，還包括設置在所述半導體中介層的所述第一表面上的重佈線結構，且所述第一晶粒及所述第二晶粒通過所述重佈線結構而與所述穿孔電連接。
  19. 如申請專利範圍第16項所述的結構，還包括設置在所述半導體中介層的所述第二表面上的重佈線結構，且所述導電連接件通過所述重佈線結構而與所述穿孔電連接。
  20. 如申請專利範圍第16項所述的結構，其中在所述第一方向與所述結晶取向之間存在夾角θ，且所述夾角θ介於約85度到約95度的範圍內。
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