CN112005371A - 用于多层3d集成的裸片堆叠 - Google Patents

用于多层3d集成的裸片堆叠 Download PDF

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CN112005371A
CN112005371A CN201980025193.7A CN201980025193A CN112005371A CN 112005371 A CN112005371 A CN 112005371A CN 201980025193 A CN201980025193 A CN 201980025193A CN 112005371 A CN112005371 A CN 112005371A
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semiconductor
die
semiconductor die
stack
wafer
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CN201980025193.7A
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English (en)
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拉胡尔·阿加瓦尔
米林德·S·巴格瓦特
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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Publication of CN112005371A publication Critical patent/CN112005371A/zh
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Abstract

公开各种裸片堆叠以及创建所述裸片堆叠的方法。在一个方面中，提供一种制造方法，包括将第一半导体裸片(40)安装在第一半导体晶片(185)的第二半导体裸片(35)上。将所述第二半导体裸片从所述第一半导体晶片切单以产生第一裸片堆叠。将所述第一裸片堆叠的所述第二半导体裸片安装在第二半导体晶片(205)的第三半导体裸片(30)上。将所述第三半导体裸片从所述第二半导体晶片切单以产生第二裸片堆叠。将所述第二裸片堆叠安装在第三半导体晶片(225)的第四半导体裸片(25)上。

Description

用于多层3D集成的裸片堆叠
发明背景
许多当前的集成电路在公共晶片上形成为多个裸片。完成在裸片上形成电路的基本工艺步骤之后，将各个裸片从晶片切单。通常，随后将切单的裸片安装至例如电路板的结构或封装在某种形式的壳体中。
一种常用封装由其上安装裸片的衬底组成。衬底的上表面包括电气互连件。裸片用多个接合焊盘制造。在裸片的接合焊盘与衬底互连件之间设置焊点集合以建立欧姆接触。在裸片安装至衬底之后，将盖子附接至衬底以覆盖裸片。例如微处理器的一些常规集成电路会产生大量热量，必须将所述热量散发出去以避免装置关机或损坏。盖子用作保护盖和热量传递路径两者。
堆叠裸片布置涉及将一个或多个半导体裸片放置或堆叠在基础半导体芯片上。在一些常规变型中，基础半导体裸片是例如微处理器的高散热装置。堆叠裸片有时是存储器装置。在典型的常规制造过程中，将裸片一次一个地堆叠在基础裸片上。裸片至裸片电气连接借助于凸块和芯片通孔实现。
附图说明
在阅读以下详细描述后并且在参考附图后将明白本发明的前述内容和其它优点，在附图中：
图1是具有裸片叠层的半导体裸片装置的示例性布置的截面图；
图2是以更大放大率示出的图1的部分；
图3是示例性半导体晶片的部分的截面图；
图4是描绘半导体晶片在载体晶片上的示例性安装的截面图；
图5是描绘示例性晶片薄化的截面图；
图6是描绘半导体裸片在半导体晶片的半导体裸片上的示例性安装的截面图；
图7是切单的裸片堆叠的截面图；
图8是另一示例性半导体晶片的部分的截面图；
图9是描绘半导体晶片在另一载体晶片上的示例性安装的截面图；
图10是描绘示例性晶片薄化的截面图；
图11是描绘裸片堆叠在半导体晶片的半导体裸片上的示例性安装的截面图；
图12是另一切单的裸片堆叠的截面图；
图13是描绘裸片堆叠在半导体晶片的半导体裸片上的示例性安装的截面图；
图14是切单的裸片堆叠的截面图；
图15是另一示例性半导体晶片的部分的截面图；
图16是描绘半导体晶片在另一载体晶片上的示例性安装的截面图；
图17是描绘示例性晶片薄化的截面图；
图18是描绘裸片堆叠在半导体晶片的半导体裸片上的示例性安装的截面图；
图19是描绘安装在半导体晶片的裸片上的裸片堆叠的截面图；
图20是描绘示例性虚拟组件安装的截面图；
图21是描绘示例性模制材料模制的截面图；以及
图22是描绘示例性I/O安装的截面图。
具体实施方式
常规裸片堆叠技术按顺序堆叠裸片，一个裸片处于第一裸片的顶部上，以此类推直到堆叠的顶部裸片。在裸片通孔(TDV)用于裸片至裸片电气连接的情况下，需要显露工艺以显露一个裸片的TDV，然后再安装下一裸片。这通常通过创建先前切单的裸片的重构晶片，然后对重构晶片执行显露工艺而在一个常规过程中完成。通常，需要间隙填充工艺以避免在显露堆叠中的当前最顶部裸片的TDV期间对堆叠中的下部裸片产生不利影响。然而，本文所公开的技术使得能够在总是可以在晶片级执行TDV显露的情况下创建裸片堆叠而无需采取重新构造。在堆叠创建期间的间隙填充工艺不是必需的。
根据本发明的一个方面，提供一种制造方法，包括将第一半导体裸片安装在第一半导体晶片的第二半导体裸片上。将第二半导体裸片从第一半导体晶片切单以产生第一裸片堆叠。将第一裸片堆叠的第二半导体裸片安装在第二半导体晶片的第三半导体裸片上。将第三半导体裸片从第二半导体晶片切单以产生第二裸片堆叠。将第二裸片堆叠安装在第三半导体晶片的第四半导体裸片上。
所述方法包括将第一虚拟组件安装在与第二裸片堆叠的第一侧相邻的第三半导体晶片上；以及将第二虚拟组件安装在与第二裸片堆叠的第二侧相邻的第三半导体晶片上，所述第二侧与所述第一侧相对。
所述方法包括将第四半导体裸片从第三半导体晶片切单以产生第三裸片堆叠。
所述方法包括将第一半导体晶片安装至第一载体晶片；以及显露第二半导体裸片的多个裸片通孔，之后再将第一半导体裸片安装在第二半导体裸片上。
所述方法包括将第二半导体晶片安装至第二载体晶片；以及显露第三半导体裸片的多个裸片通孔，之后再将第二半导体裸片安装在第三半导体裸片上。
所述方法包括在第一半导体裸片与第二半导体裸片之间制造多个互连件。
所述方法，其中将第一半导体裸片安装至第二半导体裸片包括：在第一半导体裸片与第二半导体裸片之间形成具有第一玻璃层和第二玻璃层的绝缘结合层，并且所述绝缘结合层结合第一半导体裸片和第二半导体裸片；以及退火以将第一玻璃层结合至第二玻璃层并冶金地结合第一半导体裸片的导体结构和第二半导体裸片的导体结构。
所述方法包括对模制材料进行模制以至少部分地包围第二裸片堆叠。
所述方法，其中第四半导体裸片具有面向第三半导体裸片的第一侧以及与所述第一侧相对的另一侧，并且所述方法包括在另一侧上制造多个I/O。
根据本发明的另一方面，提供一种制造方法，包括：将第一半导体晶片安装在第一载体晶片上；显露第一半导体晶片的第一半导体裸片的裸片通孔；在显露裸片通孔之后，将第二半导体裸片安装在第一半导体裸片上；将第一半导体裸片从第一半导体晶片切单以产生第一裸片堆叠；将第二半导体晶片安装在第二载体晶片上；显露第二半导体晶片的第三半导体裸片的多个裸片通孔；在显露第三半导体裸片的裸片通孔之后，将第一裸片堆叠的第一半导体裸片安装在第三半导体裸片上；将第三半导体裸片从第二半导体晶片切单以产生第二裸片堆叠；以及将第二裸片堆叠安装在第三半导体晶片的第四半导体裸片上。
所述方法包括将第一虚拟组件安装在与第二裸片堆叠的第一侧相邻的第三半导体晶片上；以及将第二虚拟组件安装在与第二裸片堆叠的第二侧相邻的第三半导体晶片上，所述第二侧与所述第一侧相对。
所述方法包括将第四半导体裸片从第三半导体晶片切单以产生第三裸片堆叠。
所述方法包括在第二裸片堆叠的裸片中的每一个之间制造多个互连件。
所述方法，其中将第二半导体裸片安装至第一半导体裸片包括：在第一半导体裸片与第二半导体裸片之间形成具有第一玻璃层和第二玻璃层的绝缘结合层，并且所述绝缘结合层结合第一半导体裸片和第二半导体裸片；以及退火以将第一玻璃层结合至第二玻璃层。
所述方法包括对模制材料进行模制以至少部分地包围第二裸片堆叠。
所述方法，其中第一半导体裸片具有面向第二半导体裸片的第一侧以及与所述第一侧相对的另一侧，包括在另一侧上制造多个I/O。
根据本发明的另一方面，提供一种半导体裸片装置，包括：第一半导体裸片；多个半导体裸片的堆叠，其位于第一半导体裸片上，其中多个半导体裸片的堆叠中的每两个相邻半导体裸片通过多个互连件电连接；第一虚拟组件，所述第一虚拟组件位于与半导体裸片的堆叠的第一侧相对并且与多个半导体裸片的堆叠间隔开第一间隙，以及第二虚拟组件，所述第二虚拟组件位于与多个半导体裸片的堆叠的第二侧相对并且与多个半导体裸片的堆叠间隔开第二间隙；以及模制材料，所述模制材料位于第一和第二间隙中并且至少部分地包围多个半导体裸片的堆叠。
半导体裸片装置，其中多个半导体裸片的堆叠中的每两个相邻半导体裸片通过绝缘结合层物理连接，所述绝缘结合层包括第一绝缘层以及结合至第一绝缘层的第二绝缘层。
半导体裸片装置，其中互连件包括无凸块互连件。
半导体裸片装置，其中第一半导体裸片具有面向多个半导体裸片的堆叠中的最低半导体裸片的第一侧以及与所述第一侧相对的另一侧，以及在另一侧上的多个I/O。
在下文描述的图式中，相同元件出现在不止一个图式中的情况下通常重复参考标号。现在转向图式，且具体地转向图1，图1是包括安装在另一半导体裸片20上的多个半导体裸片的堆叠15的示例性半导体裸片装置10的截面图。半导体裸片装置10可以安装在电路板(未示出)上，例如封装衬底、系统板、子板、电路卡等。在此说明性布置中，堆叠15由四个半导体裸片25、30、35和40组成，但是当然其它数目也是可能的。半导体裸片20、25、30、35和40包括线结构(BEOL)45、50、55、60和65的相应后端。BEOL 45、50、55、60和65由逻辑和其它装置层组成，这些层构成半导体裸片20、25、30、35和40以及多个金属化层间介电层的功能性。半导体裸片堆叠15的半导体裸片25、30、35和40可以具有不同的占用空间或大致相同的占用空间。在所说明的布置中，半导体裸片堆叠15的半导体裸片25、30、35和40可以具有连续更小的占用空间，也就是说，半导体裸片40小于半导体裸片35，半导体裸片35又小于半导体裸片30等等。
半导体裸片25与半导体裸片20之间借助于多个互连件70电连接。半导体裸片30借助于多个互连件75电连接至半导体裸片25。另外，互连件80和85的集合分别在半导体裸片35和30以及40和35之间建立导电性。绝缘层90、95、100和105分别位于半导体裸片25与半导体裸片20、半导体裸片30与半导体裸片25、半导体裸片35与半导体裸片30，以及半导体裸片40与半导体裸片35之间。绝缘层90、95、100和105可以是单层或多层结构，如下文更详细地描述。互连件70、75、80和85可以是混合键、导电柱、焊料凸块、焊料微凸块，或其它类型的互连件。
半导体裸片20、25、30、35和40可以是多种集成电路中的任一个。实例的非详尽列表包括处理器，例如微处理器、图形处理单元、组合这两者的各方面的加速处理单元、存储器装置、专用集成电路等。在一个布置中，半导体裸片20可以是处理器，并且半导体裸片25、30、35和40可以是存储器裸片，例如DRAM、SRAM等。
为了促进来自半导体裸片20的热传递，虚拟组件110和115可以安装在半导体裸片20上并且分别通过粘合剂层120和125固定至所述半导体裸片。虚拟组件110和115可以由硅、锗或其它类型的半导体或者甚至介电材料组成，并且用作用于将热量从半导体裸片20和半导体裸片装置10的其它组件传导出来的热传递途径。粘合剂层120和125可以是各种类型的有机粘合剂、无机结合层、玻璃基粘合剂，或甚至在其它布置中的焊接材料。非详尽列表包括环氧树脂、有机TIM，例如混合有铝颗粒和氧化锌的硅橡胶。可以使用除硅橡胶之外的顺应基础材料和除铝之外的导热颗粒。导热油脂以及金、铂和银表示几个实例。在其它布置中，粘合剂层120和125可以是由铝和镍的层组成的纳米箔。
模制材料130至少横向地包围半导体裸片堆叠15并且位于半导体裸片堆叠15与虚拟组件110和115之间。在示例性布置中，用于模制材料130的材料可以具有约165℃的模制温度。两个商业变体是Sumitomo EME-G750和G760。可以使用已知的压缩模制技术对模制材料130进行模制。
通过多个裸片通孔(TDV)提供贯穿裸片的导电性。例如，半导体裸片20包括连接至互连件70和I/O 140的多个TDV 135。TDV 135(以及任何相关的所公开导体，例如柱和焊盘)可以由各种导体材料组成，例如铜、铝、银、金、铂、钯等。通常，每个TDV 135由SiOx或其它绝缘体的内衬层(未示出)以及TiN或其它阻挡材料的阻挡层横向地包围。半导体裸片25类似地包括连接在互连件70和75之间的TDV 145。半导体裸片30包括连接在互连件75和80之间的TDV 150，并且半导体裸片35包括连接在互连件80和85之间的TDV 155。最终，半导体裸片40包括多个TDV 160，所述TDV在此说明性布置中未示出，但是当然可以使用本文公开的薄化/显露工艺来显露，以促进在需要时与堆叠在堆叠15顶部的又另一裸片的互连。I/O 140使半导体裸片装置10能够与例如电路板或其它装置的另一组件电连接，并且可以是焊料凸块、球或其它类型的互连结构。众所周知的无铅焊料，例如Sn-Ag、Sn-Ag-Cu等可以用于I/O140以及本文公开的其它焊料结构。
现在将结合图2描述互连件75和绝缘层95的示例性布置的附加细节。应注意，图2是由以更大放大率示出的小虚线矩形165界定的图1的部分。以下描述将说明其它互连件70、80和85以及其它绝缘层90、100和105。如图2中所示，互连件75中的每一个由无凸块氧化物混合键组成。就此而言，半导体裸片25与半导体裸片30的BEOL 55之间的互连件75由BEOL55的接合焊盘170与半导体裸片25的接合焊盘172之间的冶金结合构成。接合焊盘170连接至TDV 150并且接合焊盘172连接至TDV 145。另外，绝缘结构95将半导体裸片25接合至半导体裸片30，并且由半导体裸片30的玻璃层175(例如，SiOx)以及半导体裸片25的另一玻璃层180(例如，氮氧化硅)组成。玻璃层175和180优选地通过等离子体增强化学气相沉积(PECVD)分别沉积在半导体裸片25和30上。接合焊盘170位于玻璃层175中并且接合焊盘172位于玻璃层180中。接合焊盘170和接合焊盘172通过退火工艺冶金结合。就此而言，将半导体裸片30放下或以其它方式定位在半导体裸片25上，使得玻璃层175在玻璃层180上或非常靠近玻璃层180，而接合焊盘170在接合焊盘172上或非常靠近接合焊盘172。此后，执行退火工艺，所述退火工艺产生接合焊盘170和172的短暂热膨胀，从而使这些结构物理接触并使它们形成冶金结合，即使在半导体裸片25和30进行冷却并且接合焊盘170和172热膨胀之后仍存在所述冶金结合。铜在此金属结合工艺中表现良好，但可以使用其它导体。在玻璃层175与玻璃层180之间还形成氧化物/氮化物键。在约300℃下执行示例性退火约30至60分钟，以形成必要的氮氧化物-氧化物键和金属-金属键。在另一替代方案中，可以对两个相邻堆叠裸片中的每一个上的导电柱进行热压结合。在另一替代布置中，可以使用方向氧化物键和TSV最后连接。在此技术中，每两个相邻的堆叠裸片的面对侧各自接收氧化物膜。随后使用化学机械抛光将氧化物膜平坦化，然后进行等离子体处理以使其亲水。接下来将氧化物表面放置在一起并进行退火以形成结合。
现在将结合图3、图4、图5、图6、图7、图8、图9、图10、图11、图12、图13、图14、图15、图16、图17、图18、图19、图20、图21和图22描述用于制造图1中所描绘的半导体裸片装置10的示例性过程流。首先将注意力转向图3，图3是半导体晶片185的部分的截面图。除了半导体裸片35之外，半导体晶片185还可以包括数十个或数百个个别半导体裸片。此处，半导体裸片35通过切割道190和195定界，其中将出现从半导体晶片185的最终切单。当然，存在不与半导体裸片35相关联的额外切割道，这在图3中不可见。已将晶片185处理成与TDV 155一起完成半导体裸片35的BEOL 60的程度。然而，晶片185还没有经历薄化工艺以显露TDV155。
接下来并且如图4中所示，将晶片185从图3中所描绘的定向翻转并且安装在载体晶片200上，其中BEOL 60面向载体晶片200。载体晶片200可以由硅、各种玻璃，或其它类型的半导体材料组成。晶片185可以通过施加至载体晶片200的粘合剂202固定至载体晶片200。粘合剂202优选地是众所周知的可逆粘合剂，例如，光活化或热活化粘合剂，可以将所述可逆粘合剂逆转，使得稍后可以去除载体晶片200。任选地，可以使用需要化学和/或机械去除技术的结合剂。
接下来并且如图5中所示，晶片185经历薄化工艺以显露TDV 155。可以使用各种薄化/显露工艺。在一个布置中，显露工艺优选地为软显露，其中晶片185和半导体裸片35经受研磨工艺以正好处于裸片通孔155的顶部上方，然后回蚀以显露裸片通孔155的顶部。接下来，使用沉积工艺来建立薄玻璃层(不可见，但类似于图2中描绘以及上文描述的玻璃层180)。优选地使用PECVD沉积薄玻璃层，然后使其经受CMP。载体晶片200促进这些各种研磨、蚀刻、沉积和CMP工艺。在一种所谓的“硬显露”技术中，使用研磨工艺来暴露TDV 155，然后回蚀少量晶片185(硅或其它)，接着通过CVD进行薄氧化物生长或沉积或薄氮化硅沉积，然后再次进行化学机械平面化，以便完成裸片通孔显露。第一技术避免将衬底半导体晶片185暴露于可以在硬显露期间露出来的松散的铜或其它金属颗粒。
接下来并且如图6中所示，将半导体裸片40安装在晶片185的半导体裸片35上。半导体裸片40是形式上为另一半导体晶片(未示出)的一部分的切单的装置，所述半导体晶片经过处理以建立半导体裸片40的BEOL 65及其未暴露的TDV 160。此时使用本文结合图2在其它地方公开以及用于互连件75和绝缘层95的技术来制造互连件85和绝缘层105。当然，如果使用结合图2描述的前述无凸块混合键工艺，则在安装过程之前将玻璃层(不可见，但类似于图2中描绘且本文其它地方描述的玻璃层175)施加在半导体裸片40(或所述半导体裸片在形式上为其一部分的晶片)上。任选地，如果互连件85是焊料凸块、焊料微凸块或其它类型的互连件，则将在此阶段执行合适的安装和回流工艺以建立互连件85。
接下来并且如图7中所示，在最初去除图6中所示的载体晶片200之后，将半导体裸片35从晶片185切单以产生半导体裸片35和40的组合。载体晶片200的去除工艺将取决于粘合剂202的类型。实例包括热释放、化学释放、机械剥离或激光诱导去除。半导体裸片35和40的这种组合现在为将放置于半导体裸片30上的可堆叠元件，如下文更全面地描述。
现将结合图8、图9和图10描述半导体裸片30的制造。另一半导体晶片205包括多个半导体裸片，包括已使用众所周知的技术进行处理以建立BEOL 55以及其TDV 150的半导体裸片30。类似于半导体晶片185，晶片205此时还没有经历薄化工艺以显露TDV 150。半导体裸片30由切割道210和215以及图8中不可见的至少两个其它切割道定界。接下来并且如图9中所示，将半导体晶片205从图8中所示的定向翻转并且安装在另一载体晶片220上，使得BEOL 55面向载体晶片220。载体晶片220可以由硅、各种玻璃或其它类型的半导体材料组成。半导体晶片205可以通过施加至载体晶片220的粘合剂220固定至载体晶片220。粘合剂可以类似于上述粘合剂202并且为了简洁说明起见未示出。接下来并且如图10中所示，半导体晶片205经历薄化工艺以显露半导体裸片30的TDV 150。可以通过上文结合图5公开的薄化/显露工艺实现显露。现在，晶片205准备好使半导体裸片35和40的组合安装在其半导体裸片30上。接下来并且如图11中所示，将半导体裸片35和40的组合安装在晶片205的半导体裸片30上。安装过程可以类似于上文结合将半导体裸片40安装在半导体裸片35上描述的安装过程。就此而言，此时使用上文结合图1和图2中描绘的互连件75和绝缘结构95描述的技术来建立互连件80和绝缘层100。使用适合于结合至半导体晶片205的粘合剂(不可见)(例如本文其它地方所公开的类型)的工艺来去除载体晶片220。然后将半导体裸片30从晶片205切单，以产生如图12中所示的半导体裸片30、35和40的切单的组合。可以通过机械锯切、激光切割或其它技术来实现切单。
接下来并且如图13中所示，将半导体裸片30、35和40的组合安装在半导体裸片25上，所述半导体裸片在此阶段仍为半导体晶片225的一部分，所述半导体晶片已类似于上文描述的半导体晶片185和205在载体晶片230上经过处理，使得晶片225已经受薄化工艺以显露半导体裸片25的TDV 145并且BEOL 50面向载体晶片230。将半导体裸片30、35和40安装至半导体裸片25的过程类似于将半导体裸片35和40的组合安装至刚才描述的半导体裸片30的过程。在安装过程之后，去除载体晶片230并且将半导体裸片25从半导体晶片225切单，以产生图14中所示的完整半导体裸片堆叠15。由半导体裸片25、30、35和40组成的半导体裸片堆叠15现在准备就绪，可安装在图1中所示的半导体裸片20上。
现在参考图15，半导体裸片20最初是半导体晶片235的一部分，并且由切割道240和245以及两个其它此类道(不可见)定界。晶片235已经过处理，使得已制造半导体裸片20的BEOL 45和TDV 135。然而，晶片235还没有经历薄化工艺以显露TDV 135。接下来并且如图16中所示，将半导体晶片235从图15中所示的定向翻转并且安装在载体晶片250上，其中BEOL 45面向载体晶片250。半导体晶片235可以使用施加至载体晶片250的粘合剂固定至载体晶片250。粘合剂可以类似于上述粘合剂202，并且为了简洁说明起见未示出。接下来并且如图17中所示，在载体晶片250就位的情况下，晶片235经历薄化工艺以显露半导体裸片20的TDV 135。可以通过上文结合图5公开的薄化/显露工艺实现显露。接下来并且如图18中所示，将半导体裸片堆叠15安装在晶片235的半导体裸片20上。此安装过程建立互利件70和绝缘结构90，并且可以通过前述混合结合工艺或在互连件70不是混合键的情况下通过另一工艺实现。在图19中描绘将堆叠15安装在半导体裸片20上。接下来并且如图20中所示，在载体晶片250仍就位的情况下，将虚拟组件110和115安装在处于半导体裸片堆叠15任一侧上的半导体晶片235上。可以对虚拟组件110和115进行预成型以安装至半导体裸片堆叠15并且专用于半导体裸片堆叠15。当然，在虚拟组件110和115足够大以细分为针对半导体裸片堆叠15预留的虚拟组件以及将由半导体晶片235上的相邻半导体裸片堆叠(不可见)使用的其它虚拟组件(不可见)的情况下可以实现效率。实际上，应注意，在后续的切单工艺期间，切割道240和245将定界虚拟组件110和115的切单后的横向边缘。
接下来并且如图21中所示，在载体晶片250就位的情况下，半导体晶片235经历模制工艺以建立模制材料130。此模制工艺可以为模制材料130建立与虚拟组件110和115成一平面的上表面。任选地，模制材料130可以覆盖虚拟组件110和115以及甚至半导体裸片堆叠15的最顶部半导体裸片40，然后可以使用后续研磨工艺来平面化模制材料130和虚拟组件110和115。接下来并且如图22中所示，制造I/O结构140或另外将I/O结构140附接至半导体裸片20。这可能需要拾取与放置和回流或焊料模板或其它工艺以建立I/O结构140。在附接或另外制造I/O结构140之前，使用本文其它地方公开的载体晶片去除技术来去除图21中描绘的载体晶片250。接下来使用本文其它地方公开的技术在切割道240和245处将半导体裸片20从半导体晶片235切单，以产生图1中所示的完整半导体裸片装置10。
尽管本发明可以容许各种修改和替代形式，但是特定实施方案借助于图式中的实例示出并且已在本文中详细地描述。然而，应理解，本发明并不意图限于所公开的特定形式。相反，本发明将涵盖落入如所附权利要求书限定的本发明的精神和范围内的所有修改、等效物和替代方案。

Claims (20)

1.一种制造方法，包括：
将第一半导体裸片(40)安装在第一半导体晶片(185)的第二半导体裸片(35)上；
将所述第二半导体裸片从所述第一半导体晶片切单以产生第一裸片堆叠；
将所述第一裸片堆叠的所述第二半导体裸片安装在第二半导体晶片(205)的第三半导体裸片(30)上；
将所述第三半导体裸片从所述第二半导体晶片切单以产生第二裸片堆叠；以及
将所述第二裸片堆叠安装在第三半导体晶片(225)的第四半导体裸片(25)上。
2.如权利要求1所述的方法，包括将第一虚拟组件(110)安装在与所述第二裸片堆叠的第一侧相邻的所述第三半导体晶片上；以及将第二虚拟组件(115)安装在与所述第二裸片堆叠的第二侧相邻的所述第三半导体晶片上，所述第二侧与所述第一侧相对。
3.如权利要求1所述的方法，包括将所述第四半导体裸片从所述第三半导体晶片切单以产生第三裸片堆叠。
4.如权利要求1所述的方法，包括将所述第一半导体晶片安装至第一载体晶片(200)；以及显露所述第二半导体裸片的多个裸片通孔(155)，之后再将所述第一半导体裸片安装在所述第二半导体裸片上。
5.如权利要求4所述的方法，包括将所述第二半导体晶片安装至第二载体(220)晶片；以及显露所述第三半导体裸片的多个裸片通孔(150)，之后再将所述第二半导体裸片安装在所述第三半导体裸片上。
6.如权利要求1所述的方法，包括在所述第一半导体裸片与所述第二半导体裸片之间制造多个互连件(85)。
7.如权利要求1所述的方法，其中所述将所述第一半导体裸片安装至所述第二半导体裸片包括在所述第一半导体裸片与所述第二半导体裸片之间形成具有第一玻璃层(175)和第二玻璃层(180)的绝缘结合层，并且所述绝缘结合层结合所述第一半导体裸片和所述第二半导体裸片；以及退火以将所述第一玻璃层结合至所述第二玻璃层并冶金地结合所述第一半导体裸片的导体结构和所述第二半导体裸片的导体结构。
8.如权利要求1所述的方法，包括对模制材料(130)进行模制以至少部分地包围所述第二裸片堆叠。
9.如权利要求1所述的方法，其中所述第四半导体裸片具有面向所述第三半导体裸片的第一侧以及与所述第一侧相对的另一侧，所述方法包括在所述另一侧上制造多个I/O(140)。
10.一种制造方法，包括：
将第一半导体晶片(185)安装在第一载体晶片(200)上；
显露所述第一半导体晶片的第一半导体裸片(35)的多个裸片通孔(155)；
在所述显露所述裸片通孔之后，将第二半导体裸片(40)安装在所述第一半导体裸片上；
将所述第一半导体裸片从所述第一半导体晶片切单以产生第一裸片堆叠；
将第二半导体晶片(205)安装在第二载体晶片(220)上；
显露所述第二半导体晶片的第三半导体裸片(205)的多个裸片通孔(150)；
在所述显露所述第三半导体裸片的所述裸片通孔之后，将所述第一裸片堆叠的所述第一半导体裸片安装在所述第三半导体裸片上；
将所述第三半导体裸片从所述第二半导体晶片切单以产生第二裸片堆叠；以及
将所述第二裸片堆叠安装在第三半导体晶片(225)的第四半导体裸片(25)上。
11.如权利要求10所述的方法，包括将第一虚拟组件(110)安装在与所述第二裸片堆叠的第一侧相邻的所述第三半导体晶片上，以及将第二虚拟组件(115)安装在与所述第二裸片堆叠的第二侧相邻的所述第三半导体晶片上，所述第二侧与所述第一侧相对。
12.如权利要求10所述的方法，包括将所述第四半导体裸片从所述第三半导体晶片切单以产生第三裸片堆叠。
13.如权利要求10所述的方法，包括在所述第二裸片堆叠的所述裸片中的每一个之间制造多个互连件(75)。
14.如权利要求10所述的方法，其中所述将所述第二半导体裸片安装至所述第一半导体裸片包括在所述第一半导体裸片与所述第二半导体裸片之间形成具有第一玻璃层(175)和第二玻璃层(180)的绝缘结合层，并且所述绝缘结合层结合所述第一半导体裸片和所述第二半导体裸片；以及退火以将所述第一玻璃层结合至所述第二玻璃层。
15.如权利要求10所述的方法，包括对模制材料(130)进行模制以至少部分地包围所述第二裸片堆叠。
16.如权利要求10所述的方法，其中所述第一半导体裸片具有面向所述第二半导体裸片的第一侧以及与所述第一侧相对的另一侧，所述方法包括在所述另一侧上制造多个I/O(140)。
17.一种半导体裸片装置，包括：
第一半导体裸片(20)；
多个半导体裸片()的堆叠(15)，其位于所述第一半导体裸片上，所述多个半导体裸片的堆叠中的每两个相邻半导体裸片通过多个互连件互连；
第一虚拟组件(110)，其位于与半导体裸片的所述堆叠的第一侧相对并且与所述多个半导体裸片的堆叠间隔开第一间隙，以及第二虚拟组件(115)，其位于与所述多个半导体裸片的堆叠的第二侧相对并且与所述多个半导体裸片的堆叠间隔开第二间隙；以及
模制材料(130)，其位于所述第一和第二间隙中并且至少部分地包围所述多个半导体裸片的堆叠。
18.如权利要求17所述的半导体裸片装置，其中所述多个半导体裸片的堆叠中的每两个相邻半导体裸片通过绝缘结合层物理地连接，所述绝缘结合层包括第一绝缘层以及结合至所述第一绝缘层的第二绝缘层。
19.如权利要求18所述的半导体裸片装置，其中所述互连件包括无凸块互连件。
20.如权利要求17所述的半导体裸片装置，其中所述第一半导体裸片具有面向所述多个半导体裸片的堆叠中的最低半导体裸片的第一侧以及与所述第一侧相对的另一侧，以及所述另一侧上的多个I/O(140)。
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Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11069734B2 (en) 2014-12-11 2021-07-20 Invensas Corporation Image sensor device
US9741620B2 (en) 2015-06-24 2017-08-22 Invensas Corporation Structures and methods for reliable packages
US10204893B2 (en) 2016-05-19 2019-02-12 Invensas Bonding Technologies, Inc. Stacked dies and methods for forming bonded structures
US10879212B2 (en) 2017-05-11 2020-12-29 Invensas Bonding Technologies, Inc. Processed stacked dies
US10217720B2 (en) 2017-06-15 2019-02-26 Invensas Corporation Multi-chip modules formed using wafer-level processing of a reconstitute wafer
US11276676B2 (en) 2018-05-15 2022-03-15 Invensas Bonding Technologies, Inc. Stacked devices and methods of fabrication
US10727204B2 (en) * 2018-05-29 2020-07-28 Advances Micro Devices, Inc. Die stacking for multi-tier 3D integration
WO2020010265A1 (en) 2018-07-06 2020-01-09 Invensas Bonding Technologies, Inc. Microelectronic assemblies
WO2020010136A1 (en) 2018-07-06 2020-01-09 Invensas Bonding Technologies, Inc. Molded direct bonded and interconnected stack
US11296044B2 (en) 2018-08-29 2022-04-05 Invensas Bonding Technologies, Inc. Bond enhancement structure in microelectronics for trapping contaminants during direct-bonding processes
US11309334B2 (en) 2018-09-11 2022-04-19 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells
US11211334B2 (en) 2018-11-18 2021-12-28 iCometrue Company Ltd. Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip
CN113330557A (zh) 2019-01-14 2021-08-31 伊文萨思粘合技术公司 键合结构
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
US11227838B2 (en) 2019-07-02 2022-01-18 iCometrue Company Ltd. Logic drive based on multichip package comprising standard commodity FPGA IC chip with cooperating or supporting circuits
DE102021101251A1 (de) 2020-03-31 2021-09-30 Taiwan Semiconductor Manufacturing Co., Ltd. Schutz vor antenneneffekten und schutz vor elektrostatischen entladungen für dreidimensionale integrierte schaltkreise
US11437708B2 (en) 2020-03-31 2022-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Antenna effect protection and electrostatic discharge protection for three-dimensional integrated circuit
US11631647B2 (en) 2020-06-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Integrated device packages with integrated device die and dummy element
US11764177B2 (en) 2020-09-04 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11728273B2 (en) 2020-09-04 2023-08-15 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11594460B2 (en) * 2021-03-11 2023-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method of fabricating the same
KR20220151442A (ko) * 2021-05-06 2022-11-15 삼성전자주식회사 반도체 패키지
US20230207525A1 (en) * 2021-12-24 2023-06-29 Intel Corporation Ic die stacking with mixed hybrid and solder bonding

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070048969A1 (en) * 2005-08-31 2007-03-01 Samsung Electronics Co., Ltd. Stacked chip package using photosensitive polymer and manufacturing method thereof
CN101038883A (zh) * 2006-03-17 2007-09-19 海力士半导体有限公司 晶片级堆叠封装的制造方法
KR20110044963A (ko) * 2011-04-20 2011-05-03 앰코 테크놀로지 코리아 주식회사 Ｔｓｖ를 이용한 적층 칩 패키지
KR20140112674A (ko) * 2013-03-14 2014-09-24 에스케이하이닉스 주식회사 적층 반도체 패키지의 제조방법
CN104241229A (zh) * 2013-06-21 2014-12-24 三星电子株式会社 具有贯穿电极的半导体封装及其制造方法
US20150333026A1 (en) * 2014-05-19 2015-11-19 Micron Technology, Inc. Interconnect structure with improved conductive properties and associated systems and methods
US20170250172A1 (en) * 2016-02-29 2017-08-31 Semtech Corporation Semiconductor Device and Method of Stacking Semiconductor Die for System-Level ESD Protection
CN107301957A (zh) * 2016-04-15 2017-10-27 台湾积体电路制造股份有限公司 以裸片接合到形成的重布线的三维集成电路形成方法
CN107369630A (zh) * 2016-05-13 2017-11-21 台湾积体电路制造股份有限公司 用于浸润接合的系统及方法

Family Cites Families (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3065753B2 (ja) 1991-12-04 2000-07-17 イビデン株式会社 半導体集積回路ベアチップの樹脂封止方法、半導体装置
US5901041A (en) 1997-12-02 1999-05-04 Northern Telecom Limited Flexible integrated circuit package
JP2000311905A (ja) 1999-04-28 2000-11-07 Nippon Inter Electronics Corp 複合半導体装置の製造方法
JP2000357768A (ja) 1999-06-17 2000-12-26 Hitachi Ltd 半導体装置及びその製造方法
US6589802B1 (en) 1999-12-24 2003-07-08 Hitachi, Ltd. Packaging structure and method of packaging electronic parts
US6949822B2 (en) 2000-03-17 2005-09-27 International Rectifier Corporation Semiconductor multichip module package with improved thermal performance; reduced size and improved moisture resistance
US6537482B1 (en) 2000-08-08 2003-03-25 Micron Technology, Inc. Underfill and encapsulation of carrier substrate-mounted flip-chip components using stereolithography
JP2002124654A (ja) 2000-10-13 2002-04-26 Mitsubishi Electric Corp 固体撮像装置
US6906415B2 (en) 2002-06-27 2005-06-14 Micron Technology, Inc. Semiconductor device assemblies and packages including multiple semiconductor devices and methods
TW569416B (en) 2002-12-19 2004-01-01 Via Tech Inc High density multi-chip module structure and manufacturing method thereof
US7122906B2 (en) 2004-01-29 2006-10-17 Micron Technology, Inc. Die-wafer package and method of fabricating same
US7208342B2 (en) 2004-05-27 2007-04-24 Intel Corporation Package warpage control
JP2006261566A (ja) 2005-03-18 2006-09-28 Alps Electric Co Ltd 電子部品用ホルダ及び電子部品用保持シート、これらを用いた電子モジュール、電子モジュールの積層体、電子モジュールの製造方法並びに検査方法
JP2007183164A (ja) 2006-01-06 2007-07-19 Fujitsu Ltd 半導体集積回路装置及びその試験方法
JP4391508B2 (ja) 2006-09-29 2009-12-24 Ｏｋｉセミコンダクタ株式会社 半導体装置、及び半導体装置の製造方法
JP2009158623A (ja) 2007-12-26 2009-07-16 Panasonic Corp 半導体装置の製造方法
US7973310B2 (en) * 2008-07-11 2011-07-05 Chipmos Technologies Inc. Semiconductor package structure and method for manufacturing the same
US8691626B2 (en) 2010-09-09 2014-04-08 Advanced Micro Devices, Inc. Semiconductor chip device with underfill
US8552567B2 (en) * 2011-07-27 2013-10-08 Micron Technology, Inc. Semiconductor die assemblies, semiconductor devices including same, and methods of fabrication
US8842945B2 (en) 2011-08-09 2014-09-23 Soitec Methods of forming three dimensionally integrated semiconductor systems including photoactive devices and semiconductor-on-insulator substrates
US8372741B1 (en) 2012-02-24 2013-02-12 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US9768105B2 (en) 2012-04-20 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Rigid interconnect structures in package-on-package assemblies
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US9312198B2 (en) 2013-03-15 2016-04-12 Intel Deutschland Gmbh Chip package-in-package and method thereof
US9406588B2 (en) 2013-11-11 2016-08-02 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package and manufacturing method thereof
US9214454B2 (en) 2014-03-31 2015-12-15 Invensas Corporation Batch process fabrication of package-on-package microelectronic assemblies
KR20150123420A (ko) 2014-04-24 2015-11-04 에스케이하이닉스 주식회사 반도체 패키지 및 그 제조 방법
US9331021B2 (en) * 2014-04-30 2016-05-03 Taiwan Semiconductor Manufacturing Company, Ltd. Chip-on-wafer package and method of forming same
US9620464B2 (en) 2014-08-13 2017-04-11 International Business Machines Corporation Wireless communications package with integrated antennas and air cavity
WO2016118209A2 (en) 2014-11-05 2016-07-28 Massachusetts Institute Of Technology Multi-layer semiconductor devices fabricated using a combination of substrate and via structures and fabrication techniques
KR102411064B1 (ko) 2015-03-10 2022-06-21 삼성전자주식회사 관통전극을 갖는 반도체 소자 및 그의 제조방법
US9780079B2 (en) 2015-04-30 2017-10-03 Micron Technology, Inc. Semiconductor die assembly and methods of forming thermal paths
JP2016225466A (ja) 2015-05-29 2016-12-28 株式会社東芝 半導体装置および半導体装置の製造方法
US9520333B1 (en) 2015-06-22 2016-12-13 Inotera Memories, Inc. Wafer level package and fabrication method thereof
US9698790B2 (en) * 2015-06-26 2017-07-04 Advanced Micro Devices, Inc. Computer architecture using rapidly reconfigurable circuits and high-bandwidth memory interfaces
US9601461B2 (en) 2015-08-12 2017-03-21 Semtech Corporation Semiconductor device and method of forming inverted pyramid cavity semiconductor package
US9899355B2 (en) * 2015-09-30 2018-02-20 Taiwan Semiconductor Manufacturing Co., Ltd. Three-dimensional integrated circuit structure
US9972603B2 (en) * 2015-12-29 2018-05-15 Taiwan Semiconductor Manufacturing Co., Ltd. Seal-ring structure for stacking integrated circuits
US9806014B2 (en) 2016-01-27 2017-10-31 Advanced Micro Devices, Inc. Interposer with beyond reticle field conductor pads
US9865566B1 (en) 2016-06-15 2018-01-09 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
EP3288076B1 (en) 2016-08-25 2021-06-23 IMEC vzw A semiconductor die package and method of producing the package
US9972611B2 (en) 2016-09-30 2018-05-15 Intel Corporation Stacked semiconductor package having fault detection and a method for identifying a fault in a stacked package
US10008395B2 (en) * 2016-10-19 2018-06-26 Micron Technology, Inc. Stacked semiconductor die assemblies with high efficiency thermal paths and molded underfill
US10727204B2 (en) * 2018-05-29 2020-07-28 Advances Micro Devices, Inc. Die stacking for multi-tier 3D integration

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070048969A1 (en) * 2005-08-31 2007-03-01 Samsung Electronics Co., Ltd. Stacked chip package using photosensitive polymer and manufacturing method thereof
CN101038883A (zh) * 2006-03-17 2007-09-19 海力士半导体有限公司 晶片级堆叠封装的制造方法
KR20110044963A (ko) * 2011-04-20 2011-05-03 앰코 테크놀로지 코리아 주식회사 Ｔｓｖ를 이용한 적층 칩 패키지
KR20140112674A (ko) * 2013-03-14 2014-09-24 에스케이하이닉스 주식회사 적층 반도체 패키지의 제조방법
CN104241229A (zh) * 2013-06-21 2014-12-24 三星电子株式会社 具有贯穿电极的半导体封装及其制造方法
US20150333026A1 (en) * 2014-05-19 2015-11-19 Micron Technology, Inc. Interconnect structure with improved conductive properties and associated systems and methods
US20170250172A1 (en) * 2016-02-29 2017-08-31 Semtech Corporation Semiconductor Device and Method of Stacking Semiconductor Die for System-Level ESD Protection
CN107301957A (zh) * 2016-04-15 2017-10-27 台湾积体电路制造股份有限公司 以裸片接合到形成的重布线的三维集成电路形成方法
CN107369630A (zh) * 2016-05-13 2017-11-21 台湾积体电路制造股份有限公司 用于浸润接合的系统及方法

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