JP4391508B2 - 半導体装置、及び半導体装置の製造方法 - Google Patents
半導体装置、及び半導体装置の製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 118
- 238000004519 manufacturing process Methods 0.000 title claims description 20
- 239000000758 substrate Substances 0.000 claims description 53
- 238000007789 sealing Methods 0.000 claims description 52
- 229920005989 resin Polymers 0.000 claims description 45
- 239000011347 resin Substances 0.000 claims description 45
- 238000000034 method Methods 0.000 claims description 19
- 230000002093 peripheral effect Effects 0.000 claims description 9
- 239000007788 liquid Substances 0.000 description 52
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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Description
請求項1に係る発明は、
チップ実装領域の周囲に外部端子が形成された実装基板を準備する第1工程と、
複数の側面を有する半導体チップを準備する第2工程と、
前記半導体チップを前記実装基板に実装する第3工程と、
前記半導体チップの前記側面のうち、当該側面から当該側面に対向する前記外部端子までの距離が最も短い第1側面において、前記第1側面の前記実装基板側端辺と前記実装基板における前記第1側面の前記実装基板側端辺の直下部分とで形成される領域である第1間隙の少なくとも1部に第1封止樹脂を充填する第4工程と、
前記第1封止樹脂を硬化させて前記第1間隙を封止する第5工程と、
前記第1封止樹脂を充填した前記第1間隙又は前記第1封止樹脂により封止した前記第1間隙を除く、前記半導体チップと前記実装基板との第2間隙に第2封止樹脂を充填する第6工程と、
前記第2封止樹脂を硬化させて前記第2間隙を封止する第7工程と、
を有することを特徴とする半導体装置の製造方法である。
前記第1封止樹脂の粘度が第2封止樹脂の粘度よりも高い、請求項1に記載の半導体装置の製造方法である。
前記第4工程において、少なくとも1つ以上の未充填領域を設けるように、第1封止樹脂を前記第1間隙に充填する、請求項1又は請求項2に記載の半導体装置の製造方法である。
前記第4工程において、前記実装基板を加熱しはじめた後に、前記第1封止樹脂を前記第1間隙に充填し、前記第5工程による前記第1封止樹脂の硬化を同時に行う、請求項1乃至請求項3のいずれか1つに記載の半導体装置の製造方法である。
前記第5工程による前記第1封止樹脂の硬化と、前記第7工程による前記第2封止樹脂の硬化を同時行う、請求項1乃至請求項3のいずれか1つに記載の半導体装置の製造方法である。
前記第3工程において、前記半導体チップは単数であり、前記半導体チップの中心と前記実装基板の中心とをずらすようにして、前記半導体チップを前記実装基板に実装する、請求項1乃至請求項5のいずれか1つに記載の半導体装置の製造方法である。
チップ実装領域と、該チップ実装領域を囲む外周領域と、該外周領域に形成される外部端子と、該チップ実装領域及び該外周領域に亘って形成され外部端子に接続される配線と、を有する実装基板と、
複数の端辺を有し、前記配線に接続されると共に前記実装基板に実装される半導体チップと、
前記半導体チップの前記端辺のうち、当該端辺から当該端辺に対向する前記外部端子までの距離が最も短い端辺と前記実装基板との第1間隙の少なくとも一部を封止する第1封止樹脂と、
前記第1封止樹脂により封止された前記第1間隙を除く、前記半導体チップと前記実装基板との第2間隙を封止する第2封止樹脂と、
を備えた半導体装置である。
前記半導体チップは単数であり、前記半導体チップは前記半導体チップの中心と前記実装基板の中心とをずらすようにして前記実装基板に実装される請求項7に記載の半導体装置である。
12 パッド(外部端子)
20 半導体チップ
21 バンプ
30 第1アンダーフィル
31 液状の第1アンダーフィル
40 第2アンダーフィル
41 液状の第2アンダーフィル
50 未封止部
51 未充填部
100 半導体装置
Claims (8)
- チップ実装領域の周囲に外部端子が形成された実装基板を準備する第1工程と、
複数の側面を有する半導体チップを準備する第2工程と、
前記半導体チップを前記実装基板に実装する第3工程と、
前記半導体チップの前記側面のうち、当該側面から当該側面に対向する前記外部端子までの距離が最も短い第1側面において、前記第1側面の前記実装基板側端辺と前記実装基板における前記第1側面の前記実装基板側端辺の直下部分とで形成される領域である第1間隙の少なくとも1部に第1封止樹脂を充填する第4工程と、
前記第1封止樹脂を硬化させて前記第1間隙を封止する第5工程と、
前記第1封止樹脂を充填した前記第1間隙又は前記第1封止樹脂により封止した前記第1間隙を除く、前記半導体チップと前記実装基板との第2間隙に第2封止樹脂を充填する第6工程と、
前記第2封止樹脂を硬化させて前記第2間隙を封止する第7工程と、
を有することを特徴とする半導体装置の製造方法。 - 前記第1封止樹脂の粘度が第2封止樹脂の粘度よりも高い、請求項1に記載の半導体装置の製造方法。
- 前記第4工程において、少なくとも1つ以上の未充填領域を設けるように、第1封止樹脂を前記第1間隙に充填する、請求項1又は請求項2に記載の半導体装置の製造方法。
- 前記第4工程において、前記実装基板を加熱しはじめた後に、前記第1封止樹脂を前記第1間隙に充填し、前記第5工程による前記第1封止樹脂の硬化を同時に行う、請求項1乃至請求項3のいずれか1つに記載の半導体装置の製造方法。
- 前記第5工程による前記第1封止樹脂の硬化と、前記第7工程による前記第2封止樹脂の硬化を同時行う、請求項1乃至請求項3のいずれか1つに記載の半導体装置の製造方法。
- 前記第3工程において、前記半導体チップは単数であり、前記半導体チップの中心と前記実装基板の中心とをずらすようにして、前記半導体チップを前記実装基板に実装する、請求項1乃至請求項5のいずれか1つに記載の半導体装置の製造方法。
- チップ実装領域と、該チップ実装領域を囲む外周領域と、該外周領域に形成される外部端子と、該チップ実装領域及び該外周領域に亘って形成され外部端子に接続される配線と、を有する実装基板と、
複数の側面を有し、前記配線に接続されると共に前記実装基板に実装される半導体チップと、
前記半導体チップの前記側面のうち、当該側面から当該側面に対向する前記外部端子までの距離が最も短い第1側面において、前記第1側面の前記実装基板側端辺と前記実装基板における前記第1側面の前記実装基板側端辺の直下部分とで形成される領域である第1間隙の少なくとも一部を前記第1側面と接触するように封止する第1封止樹脂と、
前記第1封止樹脂により封止された前記第1間隙を除く、前記半導体チップと前記実装基板との第2間隙を封止する第2封止樹脂と、
を備えた半導体装置。 - 前記半導体チップは単数であり、前記半導体チップは前記半導体チップの中心と前記実装基板の中心とをずらすようにして前記実装基板に実装される請求項7に記載の半導体装置。
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JP2006269209A JP4391508B2 (ja) | 2006-09-29 | 2006-09-29 | 半導体装置、及び半導体装置の製造方法 |
KR1020070051898A KR20080029747A (ko) | 2006-09-29 | 2007-05-29 | 반도체장치 및 반도체장치의 제조 방법 |
CN2007101073601A CN101154601B (zh) | 2006-09-29 | 2007-05-29 | 半导体器件以及半导体器件的制造方法 |
US11/857,216 US7569419B2 (en) | 2006-09-29 | 2007-09-18 | Method for manufacturing semiconductor device that includes mounting chip on board and sealing with two resins |
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EP1914798A3 (en) * | 2006-10-18 | 2009-07-29 | Panasonic Corporation | Semiconductor Mounting Substrate and Method for Manufacturing the Same |
JP5168160B2 (ja) | 2009-01-15 | 2013-03-21 | ソニー株式会社 | 半導体装置及び半導体装置の製造方法 |
JP2013503919A (ja) * | 2009-09-08 | 2013-02-04 | ヤンセン バイオテツク,インコーポレーテツド | 癌患者においてヘプシジンを減少させるための抗il−6抗体の使用 |
US8691626B2 (en) * | 2010-09-09 | 2014-04-08 | Advanced Micro Devices, Inc. | Semiconductor chip device with underfill |
JP2012238796A (ja) * | 2011-05-13 | 2012-12-06 | Panasonic Corp | 半導体装置及び半導体装置の製造方法 |
US9373559B2 (en) * | 2014-03-05 | 2016-06-21 | International Business Machines Corporation | Low-stress dual underfill packaging |
US20150371916A1 (en) * | 2014-06-23 | 2015-12-24 | Rohm And Haas Electronic Materials Llc | Pre-applied underfill |
JP6591234B2 (ja) | 2015-08-21 | 2019-10-16 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
KR102374107B1 (ko) | 2015-10-07 | 2022-03-14 | 삼성전자주식회사 | 반도체 패키지 제조 방법 |
US10529693B2 (en) | 2017-11-29 | 2020-01-07 | Advanced Micro Devices, Inc. | 3D stacked dies with disparate interconnect footprints |
US10727204B2 (en) | 2018-05-29 | 2020-07-28 | Advances Micro Devices, Inc. | Die stacking for multi-tier 3D integration |
US10937755B2 (en) | 2018-06-29 | 2021-03-02 | Advanced Micro Devices, Inc. | Bond pads for low temperature hybrid bonding |
US11211263B2 (en) * | 2019-11-19 | 2021-12-28 | Qualcomm Incorporated | Structure for arrayed partial molding of packages |
US20230402417A1 (en) * | 2022-06-10 | 2023-12-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package and method of manufacturing |
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US6373142B1 (en) * | 1999-11-15 | 2002-04-16 | Lsi Logic Corporation | Method of adding filler into a non-filled underfill system by using a highly filled fillet |
US6501171B2 (en) * | 2001-01-30 | 2002-12-31 | International Business Machines Corporation | Flip chip package with improved cap design and process for making thereof |
US6528408B2 (en) * | 2001-05-21 | 2003-03-04 | Micron Technology, Inc. | Method for bumped die and wire bonded board-on-chip package |
US6888259B2 (en) * | 2001-06-07 | 2005-05-03 | Denso Corporation | Potted hybrid integrated circuit |
JP2003234362A (ja) | 2002-02-12 | 2003-08-22 | Yokogawa Electric Corp | 半導体装置 |
JP2004179576A (ja) | 2002-11-29 | 2004-06-24 | Ngk Spark Plug Co Ltd | 配線基板及びその製造方法 |
JP4415717B2 (ja) | 2004-03-23 | 2010-02-17 | ソニー株式会社 | 半導体装置及びその製造方法 |
JP2006140327A (ja) | 2004-11-12 | 2006-06-01 | Matsushita Electric Ind Co Ltd | 配線基板およびこれを用いた電子部品の実装方法 |
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