JP2008091529A - 半導体装置、及び半導体装置の製造方法 - Google Patents
半導体装置、及び半導体装置の製造方法 Download PDFInfo
- Publication number
- JP2008091529A JP2008091529A JP2006269209A JP2006269209A JP2008091529A JP 2008091529 A JP2008091529 A JP 2008091529A JP 2006269209 A JP2006269209 A JP 2006269209A JP 2006269209 A JP2006269209 A JP 2006269209A JP 2008091529 A JP2008091529 A JP 2008091529A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- sealing resin
- underfill
- gap
- mounting substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
- H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83007—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting the layer connector during or after the bonding process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83009—Pre-treatment of the layer connector or the bonding area
- H01L2224/83051—Forming additional members, e.g. dam structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83104—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus by applying pressure, e.g. by injection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8312—Aligning
- H01L2224/83136—Aligning involving guiding structures, e.g. spacers or supporting members
- H01L2224/83138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
- H01L2224/83141—Guiding structures both on and outside the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
Abstract
熱抵抗を低減した半導体装置を提供すること。
【解決手段】実装する半導体チップ(20A、20B)の4つの端辺のうち、少なくとも端辺から当該端辺に対向するインターポーザのパッド12までの距離が最も短い端辺とインターポーザ10との間隙に対し、液状の第2アンダーフィル41よりも粘度が高い液状の第1アンダーフィル31を充填して、これを硬化し第1アンダーフィル30により封止する。そして、その後、第1アンダーフィル30により封止された間隙を除く、半導体チップとインターポーザ10との間隙に対し、液状の第2アンダーフィル41を充填して、これを硬化して第2アンダーフィル40により封止する。
【選択図】図2
Description
請求項1に係る発明は、
チップ実装領域の周囲に外部端子が形成された実装基板を準備する第1工程と、
複数の端辺を有する半導体チップを準備する第2工程と、
前記半導体チップを前記実装基板に実装する第3工程と、
前記半導体チップの前記端辺のうち、当該端辺から当該端辺に対向する前記外部端子までの距離が最も短い端辺と前記実装基板との第1間隙の少なくとも1部に第1封止樹脂を充填する第4工程と、
前記第1封止樹脂を硬化させて前記第1間隙を封止する第5工程と、
前記第1封止樹脂を充填した前記第1間隙又は前記第1封止樹脂により封止した前記第1間隙を除く、前記半導体チップと前記実装基板との第2間隙に第2封止樹脂を充填する第6工程と、
前記第2封止樹脂を硬化させて前記第2間隙を封止する第7工程と、
を有することを特徴とする半導体装置の製造方法である。
前記第1封止樹脂の粘度が第2封止樹脂の粘度よりも高い、請求項1に記載の半導体装置の製造方法である。
前記第4工程において、少なくとも1つ以上の未充填領域を設けるように、第1封止樹脂を前記第1間隙に充填する、請求項1又は請求項2に記載の半導体装置の製造方法である。
前記第4工程において、前記実装基板を加熱しはじめた後に、前記第1封止樹脂を前記第1間隙に充填し、前記第5工程による前記第1封止樹脂の硬化を同時に行う、請求項1乃至請求項3のいずれか1つに記載の半導体装置の製造方法である。
前記第5工程による前記第1封止樹脂の硬化と、前記第7工程による前記第2封止樹脂の硬化を同時行う、請求項1乃至請求項3のいずれか1つに記載の半導体装置の製造方法である。
前記第3工程において、前記半導体チップは単数であり、前記半導体チップの中心と前記実装基板の中心とをずらすようにして、前記半導体チップを前記実装基板に実装する、請求項1乃至請求項5のいずれか1つに記載の半導体装置の製造方法である。
チップ実装領域と、該チップ実装領域を囲む外周領域と、該外周領域に形成される外部端子と、該チップ実装領域及び該外周領域に亘って形成され外部端子に接続される配線と、を有する実装基板と、
複数の端辺を有し、前記配線に接続されると共に前記実装基板に実装される半導体チップと、
前記半導体チップの前記端辺のうち、当該端辺から当該端辺に対向する前記外部端子までの距離が最も短い端辺と前記実装基板との第1間隙の少なくとも一部を封止する第1封止樹脂と、
前記第1封止樹脂により封止された前記第1間隙を除く、前記半導体チップと前記実装基板との第2間隙を封止する第2封止樹脂と、
を備えた半導体装置である。
前記半導体チップは単数であり、前記半導体チップは前記半導体チップの中心と前記実装基板の中心とをずらすようにして前記実装基板に実装される請求項7に記載の半導体装置である。
12 パッド(外部端子)
20 半導体チップ
21 バンプ
30 第1アンダーフィル
31 液状の第1アンダーフィル
40 第2アンダーフィル
41 液状の第2アンダーフィル
50 未封止部
51 未充填部
100 半導体装置
Claims (8)
- チップ実装領域の周囲に外部端子が形成された実装基板を準備する第1工程と、
複数の端辺を有する半導体チップを準備する第2工程と、
前記半導体チップを前記実装基板に実装する第3工程と、
前記半導体チップの前記端辺のうち、当該端辺から当該端辺に対向する前記外部端子までの距離が最も短い端辺と前記実装基板との第1間隙の少なくとも1部に第1封止樹脂を充填する第4工程と、
前記第1封止樹脂を硬化させて前記第1間隙を封止する第5工程と、
前記第1封止樹脂を充填した前記第1間隙又は前記第1封止樹脂により封止した前記第1間隙を除く、前記半導体チップと前記実装基板との第2間隙に第2封止樹脂を充填する第6工程と、
前記第2封止樹脂を硬化させて前記第2間隙を封止する第7工程と、
を有することを特徴とする半導体装置の製造方法。 - 前記第1封止樹脂の粘度が第2封止樹脂の粘度よりも高い、請求項1に記載の半導体装置の製造方法。
- 前記第4工程において、少なくとも1つ以上の未充填領域を設けるように、第1封止樹脂を前記第1間隙に充填する、請求項1又は請求項2に記載の半導体装置の製造方法。
- 前記第4工程において、前記実装基板を加熱しはじめた後に、前記第1封止樹脂を前記第1間隙に充填し、前記第5工程による前記第1封止樹脂の硬化を同時に行う、請求項1乃至請求項3のいずれか1つに記載の半導体装置の製造方法。
- 前記第5工程による前記第1封止樹脂の硬化と、前記第7工程による前記第2封止樹脂の硬化を同時行う、請求項1乃至請求項3のいずれか1つに記載の半導体装置の製造方法。
- 前記第3工程において、前記半導体チップは単数であり、前記半導体チップの中心と前記実装基板の中心とをずらすようにして、前記半導体チップを前記実装基板に実装する、請求項1乃至請求項5のいずれか1つに記載の半導体装置の製造方法。
- チップ実装領域と、該チップ実装領域を囲む外周領域と、該外周領域に形成される外部端子と、該チップ実装領域及び該外周領域に亘って形成され外部端子に接続される配線と、を有する実装基板と、
複数の端辺を有し、前記配線に接続されると共に前記実装基板に実装される半導体チップと、
前記半導体チップの前記端辺のうち、当該端辺から当該端辺に対向する前記外部端子までの距離が最も短い端辺と前記実装基板との第1間隙の少なくとも一部を封止する第1封止樹脂と、
前記第1封止樹脂により封止された前記第1間隙を除く、前記半導体チップと前記実装基板との第2間隙を封止する第2封止樹脂と、
を備えた半導体装置。 - 前記半導体チップは単数であり、前記半導体チップは前記半導体チップの中心と前記実装基板の中心とをずらすようにして前記実装基板に実装される請求項7に記載の半導体装置。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006269209A JP4391508B2 (ja) | 2006-09-29 | 2006-09-29 | 半導体装置、及び半導体装置の製造方法 |
CN2007101073601A CN101154601B (zh) | 2006-09-29 | 2007-05-29 | 半导体器件以及半导体器件的制造方法 |
KR1020070051898A KR20080029747A (ko) | 2006-09-29 | 2007-05-29 | 반도체장치 및 반도체장치의 제조 방법 |
US11/857,216 US7569419B2 (en) | 2006-09-29 | 2007-09-18 | Method for manufacturing semiconductor device that includes mounting chip on board and sealing with two resins |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006269209A JP4391508B2 (ja) | 2006-09-29 | 2006-09-29 | 半導体装置、及び半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008091529A true JP2008091529A (ja) | 2008-04-17 |
JP4391508B2 JP4391508B2 (ja) | 2009-12-24 |
Family
ID=39256158
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006269209A Expired - Fee Related JP4391508B2 (ja) | 2006-09-29 | 2006-09-29 | 半導体装置、及び半導体装置の製造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7569419B2 (ja) |
JP (1) | JP4391508B2 (ja) |
KR (1) | KR20080029747A (ja) |
CN (1) | CN101154601B (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010165814A (ja) * | 2009-01-15 | 2010-07-29 | Sony Corp | 半導体装置及び半導体装置の製造方法 |
JP2017041603A (ja) * | 2015-08-21 | 2017-02-23 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1914798A3 (en) * | 2006-10-18 | 2009-07-29 | Panasonic Corporation | Semiconductor Mounting Substrate and Method for Manufacturing the Same |
JP2013503919A (ja) * | 2009-09-08 | 2013-02-04 | ヤンセン バイオテツク,インコーポレーテツド | 癌患者においてヘプシジンを減少させるための抗il−6抗体の使用 |
US8691626B2 (en) * | 2010-09-09 | 2014-04-08 | Advanced Micro Devices, Inc. | Semiconductor chip device with underfill |
JP2012238796A (ja) * | 2011-05-13 | 2012-12-06 | Panasonic Corp | 半導体装置及び半導体装置の製造方法 |
US9373559B2 (en) * | 2014-03-05 | 2016-06-21 | International Business Machines Corporation | Low-stress dual underfill packaging |
US20150371916A1 (en) * | 2014-06-23 | 2015-12-24 | Rohm And Haas Electronic Materials Llc | Pre-applied underfill |
KR102374107B1 (ko) | 2015-10-07 | 2022-03-14 | 삼성전자주식회사 | 반도체 패키지 제조 방법 |
US10529693B2 (en) | 2017-11-29 | 2020-01-07 | Advanced Micro Devices, Inc. | 3D stacked dies with disparate interconnect footprints |
US10727204B2 (en) | 2018-05-29 | 2020-07-28 | Advances Micro Devices, Inc. | Die stacking for multi-tier 3D integration |
US10937755B2 (en) | 2018-06-29 | 2021-03-02 | Advanced Micro Devices, Inc. | Bond pads for low temperature hybrid bonding |
US11211263B2 (en) * | 2019-11-19 | 2021-12-28 | Qualcomm Incorporated | Structure for arrayed partial molding of packages |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05144875A (ja) * | 1991-11-18 | 1993-06-11 | Sharp Corp | 配線基板の実装方法 |
US6373142B1 (en) * | 1999-11-15 | 2002-04-16 | Lsi Logic Corporation | Method of adding filler into a non-filled underfill system by using a highly filled fillet |
US6501171B2 (en) * | 2001-01-30 | 2002-12-31 | International Business Machines Corporation | Flip chip package with improved cap design and process for making thereof |
US6528408B2 (en) * | 2001-05-21 | 2003-03-04 | Micron Technology, Inc. | Method for bumped die and wire bonded board-on-chip package |
US6888259B2 (en) * | 2001-06-07 | 2005-05-03 | Denso Corporation | Potted hybrid integrated circuit |
JP2003234362A (ja) | 2002-02-12 | 2003-08-22 | Yokogawa Electric Corp | 半導体装置 |
JP2004179576A (ja) | 2002-11-29 | 2004-06-24 | Ngk Spark Plug Co Ltd | 配線基板及びその製造方法 |
JP4415717B2 (ja) | 2004-03-23 | 2010-02-17 | ソニー株式会社 | 半導体装置及びその製造方法 |
JP2006140327A (ja) | 2004-11-12 | 2006-06-01 | Matsushita Electric Ind Co Ltd | 配線基板およびこれを用いた電子部品の実装方法 |
CN100394569C (zh) * | 2005-07-06 | 2008-06-11 | 乾坤科技股份有限公司 | 防止封装元件溢胶的方法 |
-
2006
- 2006-09-29 JP JP2006269209A patent/JP4391508B2/ja not_active Expired - Fee Related
-
2007
- 2007-05-29 KR KR1020070051898A patent/KR20080029747A/ko not_active Application Discontinuation
- 2007-05-29 CN CN2007101073601A patent/CN101154601B/zh not_active Expired - Fee Related
- 2007-09-18 US US11/857,216 patent/US7569419B2/en not_active Expired - Fee Related
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010165814A (ja) * | 2009-01-15 | 2010-07-29 | Sony Corp | 半導体装置及び半導体装置の製造方法 |
US9041199B2 (en) | 2009-01-15 | 2015-05-26 | Sony Corporation | Semiconductor device and method of fabricating the same |
JP2017041603A (ja) * | 2015-08-21 | 2017-02-23 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
CN106469708A (zh) * | 2015-08-21 | 2017-03-01 | 瑞萨电子株式会社 | 半导体装置 |
US10553558B2 (en) | 2015-08-21 | 2020-02-04 | Renesas Electronics Corporation | Semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
KR20080029747A (ko) | 2008-04-03 |
CN101154601A (zh) | 2008-04-02 |
JP4391508B2 (ja) | 2009-12-24 |
US7569419B2 (en) | 2009-08-04 |
CN101154601B (zh) | 2010-12-01 |
US20080081401A1 (en) | 2008-04-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4391508B2 (ja) | 半導体装置、及び半導体装置の製造方法 | |
US10510687B2 (en) | Packaging devices and methods for semiconductor devices | |
US8901732B2 (en) | Semiconductor device package and method | |
TWI620303B (zh) | 低成本封裝體翹曲解決方案 | |
KR20180036676A (ko) | 패키지와 기판 또는 다른 패키지 사이의 영역의 일부분에 언더필 재료를 포함하는 패키지를 구비한 전자 장치 | |
US20200185296A1 (en) | Semiconductor package including organic interposer | |
JP2010251408A (ja) | 半導体装置及びその製造方法並びに電子装置 | |
CN103165531B (zh) | 管芯结构及其制造方法 | |
JP2011077108A (ja) | 半導体装置 | |
KR102228461B1 (ko) | 반도체 패키지 장치 | |
US20170236804A1 (en) | Apparatuses and methods for internal heat spreading for packaged semiconductor die | |
KR102152041B1 (ko) | 높은 신뢰성을 갖는 전자 패키지 구조체, 회로 보드 및 디바이스 | |
US11367714B2 (en) | Semiconductor package device | |
JP2009135428A (ja) | 実装構造体とその製造方法 | |
KR20130122218A (ko) | 언더필 플립칩 패키지 제조방법 | |
KR101778395B1 (ko) | 3d 프린팅 기술을 이용한 반도체 패키지 | |
US9397020B2 (en) | Semiconductor package | |
US10553457B2 (en) | Semiconductor device to suppress warpage of the semiconductor device | |
TWI658544B (zh) | 半導體裝置及半導體裝置之製造方法 | |
JP2007188930A (ja) | 半導体装置及び半導体装置の製造方法 | |
KR20200032360A (ko) | 반도체 패키지 및 그 제조방법 | |
JP2013175492A (ja) | 半導体装置およびその製造方法 | |
JP2008270257A (ja) | 半導体装置およびその製造方法 | |
JP2014033167A (ja) | 半導体装置 | |
KR20120126369A (ko) | 반도체 패키지 제조방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20080922 |
|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A712 Effective date: 20081210 |
|
RD03 | Notification of appointment of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7423 Effective date: 20090203 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20090212 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20090224 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20090427 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20090929 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20091007 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121016 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
LAPS | Cancellation because of no payment of annual fees |