CN101154601A - 半导体器件以及半导体器件的制造方法 - Google Patents
半导体器件以及半导体器件的制造方法 Download PDFInfo
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Abstract
本发明提供一种能以简易且低成本的方式抑制密封树脂的溢出、获得良好的密封质量的半导体器件的制造方法,以及以简易且低成本的方式抑制密封树脂的溢出、并具有良好的密封质量的半导体器件,和降低了热电阻的半导体器件。对于所安装的半导体芯片(20A、20B)的4个端边中至少从端边到与该端边相对的转接板的焊盘(12)的距离最短的端边,向该端边与转接板(10)的间隙填充粘度比液状第2底填料(41)高的液状第1底填料(31),并使其固化,而由第1底填料(30)密封。然后,向除了被第1底填料(30)密封的间隙以外的、半导体芯片与转接板(10)的间隙,填充液状第2底填料(41),并使其固化,而由第2底填料(40)密封。
Description
技术领域
本发明涉及把半导体芯片安装在安装基板上并实施了封装的半导体器件以及半导体器件的制造方法。
背景技术
近年来,随着以移动电话等为代表的小型电子设备的高性能化和小型化,对把多个半导体芯片和无源元件等芯片器件高密度安装在被称为转接板(interposer)的安装基板上,并实施了封装的半导体器件,即所谓SiP(System in Package:系统级封装)的要求越来越高。
但是,为了实现高密度安装,需要使安装基板尽可能地小型化,要求减小所安装的半导体芯片的外形与安装基板的外形之差。
通常,利用被称为底填料(underfill)的密封树脂来密封安装基板与半导体芯片之间的间隙,但如果减小半导体芯片的外形与安装基板的外形之差,则由于该密封树脂的溢出,密封树脂会覆盖设在安装基板的芯片安装区域周围的外部端子,由此造成连接不良的问题。
为了减少溢出,虽然可以通过使用高粘度密封树脂来加以改善,但存在着需要长的填充时间,以及容易产生气泡和未填充的问题。
因此,在专利文献1中提出了如下的方案,即,使用低粘度且填充性好的密封树脂,并在安装基板上在半导体芯片与外部端子之间设置阻挡密封树脂的堤坝,使得溢出的密封树脂不会覆盖设在安装基板的芯片安装区域周围的外部端子。
[专利文献1]日本特开2005-276879
但是,上述的方案,由于在形成堤坝时采用在安装基板的整个面上涂敷了树脂后,通过光刻工序加工成规定的形状等方法,因而目前在成本和制造时间等方面,不能令人满意。
发明内容
因此,本发明的目的是提供一种能以简易且成本低的方式抑制密封树脂的溢出、获得良好的密封质量的半导体器件的制造方法。另外,本发明的目的是提供一种以简易且低成本的方式抑制密封树脂的溢出、并具有良好密封质量的半导体器件。
上述的问题采用以下的方案来解决。即,
本发明之1是一种半导体器件的制造方法,其特征在于,包括:第1工序,准备在芯片安装区域的周围形成了外部端子的安装基板;第2工序,准备具有多个端边的半导体芯片;第3工序,把上述半导体芯片安装在上述安装基板上;第4工序,向上述半导体芯片的上述端边中从该端边到和该端边相对的上述外部端子的距离最短的端边、与上述安装基板的第1间隙的至少一部分填充第1密封树脂;第5工序,通过使上述第1密封树脂固化而密封上述第1间隙;第6工序,向除了填充了上述第1密封树脂的上述第1间隙或由上述第1密封树脂密封了的上述第1间隙以外的、上述半导体芯片与上述安装基板的第2间隙填充第2密封树脂;以及第7工序,使上述第2密封树脂固化而密封上述第2间隙。
本发明之2是基于本发明之1的半导体器件的制造方法,其中,上述第1密封树脂的粘度比第2密封树脂的粘度高。
本发明之3是基于本发明之1或2的半导体器件的制造方法,其中,在上述第4工序中,以设置至少1个以上的未填充区域的方式,向上述第1间隙填充第1密封树脂。
本发明之4是基于本发明之1至3中的任意一项发明的半导体器件的制造方法,其中,在上述第4工序中,在开始了对上述安装基板的加热后,向上述第1间隙填充上述第1密封树脂,并同时进行上述第5工序的上述第1密封树脂的固化。
本发明之5是基于本发明之1至3中的任意一项发明的半导体器件的制造方法,其中,同时进行上述第5工序的上述第1密封树脂的固化、和上述第7工序的上述第2密封树脂的固化。
本发明之6是基于本发明之1至5中的任意一项发明的半导体器件的制造方法,其中,在上述第3工序中,上述半导体芯片为一个,以使上述半导体芯片的中心与上述安装基板的中心错开的方式,把上述半导体芯片安装在上述安装基板上。
本发明之7是一种半导体器件,其特征在于,具有:安装基板,其具有芯片安装区域、包围该芯片安装区域的外周区域、形成在该外周区域上的外部端子、以及形成于该芯片安装区域和该外周区域并与外部端子连接的布线;半导体芯片,其具有多个端边,与上述布线连接并安装在上述安装基板上;第1密封树脂,其对上述半导体芯片的上述端边中从该端边到和该端边相对的上述外部端子的距离为最短的端边、与上述安装基板的第1间隙的至少一部分进行密封;和第2密封树脂,其对除了由上述第1密封树脂密封了的上述第1间隙以外的、上述半导体芯片与上述安装基板的第2间隙进行密封。
本发明之8是基于本发明之7的半导体器件,其中,上述半导体芯片为一个,上述半导体芯片以使上述半导体芯片的中心与上述安装基板的中心错开的方式安装在上述安装基板上。
附图说明
图1是表示实施方式的半导体器件的概略俯视图。
图2是表示实施方式的半导体器件的概略剖面图。
图3是表示实施方式的半导体器件的制造工序的工序图。
图4是表示实施方式的半导体器件的制造工序的工序图。
图5是表示其他实施方式的半导体器件的概略俯视图。
图6是表示其他实施方式的半导体器件的概略剖面图。
图中:10-转接板(安装基板);12-焊盘(外部端子);20-半导体芯片;21-凸点;30-第1底填料;31-液状第1底填料;40-第2底填料;41-液状第2底填料;50-未密封部;51-未填充部;100-半导体器件。
具体实施方式
下面,参照附图,对本发明的实施方式进行说明。另外,对于具有实质相同功能的部分在所有图中标记相同的符号进行说明,根据情况,有时省略其说明。
图1是表示实施方式的半导体器件的概略俯视图。图2是表示实施方式的半导体器件的概略剖面图。图2是图1的A-A剖面图。
如图1和图2所示,实施方式的半导体器件100具有转接板10(安装基板),该转接板10在主面上具有芯片安装区域11、包围该芯片安装区域11的外周区域13、和以规定间隔形成在该外周区域13上的作为外部端子的焊盘(pad)12。在转接板10上,还设有形成于芯片安装区域11和外周区域13并与作为外部端子的焊盘12连接的布线等。
另外,在转接板10上,通过倒装片式连接而安装有例如在一面上作为外部端子而设置了凸点21A的第1半导体芯片20A(半导体芯片)、和同样地在一面上作为外部端子而设置了凸点(bump)21B的第2半导体芯片20B。另外,在本实施方式中,第2半导体芯片20B比第1半导体芯片20A小,第1半导体芯片20A和第2半导体芯片20B使用了大小不同的芯片,但不限于此。另外除了半导体芯片以外,例如也可以安装电容器、电阻等无源元件(电子部件)。
而且,第1半导体芯片20A的4个端边22A、23A、24A、25A中从端边到和该端边相对的转接板10的焊盘12的距离为最短的3个端边22A、23A、24A,与上述转接板10的间隙由第1底填料30密封。在本实施方式中,对于第1半导体芯片20A的安装位置而言,其4个端边中的除了与第2半导体芯片20B相对的端边25A以外的3个端边22A、23A、24A到各自相对的转接板10的焊盘12的距离大致相同,所以该3个端边22A、23A、24A与转接板10的间隙利用第1底填料30密封。
另外,对于第2半导体芯片20B的4个端边22B、23B、24B、25B中从端边到与该端边相对的转接板10的焊盘12的距离最短的一个端边25B,利用第1底填料30密封该端边25B与转接板10的间隙。
该第1底填料30设有至少1个未密封部50。在本实施方式中,在设置于一个端边与转接板10之间的第1底填料上设置有2个,并且在设置于相邻的端边与转接板10之间的第1底填料之间也设置有未密封部50。
另外,第1底填料30只要至少密封所安装的半导体芯片的4个端边中从端边到和该端边相对的转接板的焊盘的距离最短的端边、与转接板的间隙即可,也可以密封除了从端边到和该端边相对的转接板的焊盘的距离最远的端边以外的所有端边、与转接板的间隙。当然,后述的液状底填料也是同样地被填充到各个间隙中。
这里,所谓半导体芯片的端边与转接板(安装基板)的焊盘(外部端子)的距离,是指沿着与端边正交的方向的、端边与外部端子的最短距离。
另一方面,除了被第1底填料30密封的间隙以外,第1半导体芯片与转接板10的间隙、和第2半导体芯片20B与转接板10的间隙利用第2底填料40密封。
这样,本实施方式的半导体器件100便完成封装,可安装在主板等其他安装基板上。
作为转接板10也可以是例如硅基板、以铝基板等为代表的金属基板、玻璃基板和以玻璃环氧树脂基板为代表的有机树脂基板(也包括挠性印刷基板)等。在本实施方式中,作为转接板10,使用硅基板。
在转接板10上,通过对基板利用镀敷法、溅射法、光刻法、蚀刻等进行加工,形成了作为外部端子的焊盘12和布线电路(未图示)。
第1半导体芯片20A和第2半导体芯片20B分别在其一面上设置有凸点21A、21B,构成为能够与外部电连接并能安装。但是,不限于此,例如,也可以如WCSP和MDP所代表的那样,实施封装。
这里,WCSP(Wafer Level Chip Size Package或Wafer Level ChipScale Package:晶片级芯片尺寸封装)是通过以晶片单位进行封装处理,并单片化处理而得到的具有与芯片尺寸大致相同的外形尺寸的封装体。这样的WCSP已由例如日本特开平9-64049号所公开。MCP(Multi ChipPackage:多芯片封装)是2维或3维(叠层构造)地重叠搭载了多个半导体芯片的封装体。
作为第1底填料30和第2底填料,例如可列举出环氧树脂和硅树脂、和酚醛树脂等。第1底填料30和第2底填料40可以是同一种类,也可以是不同种类。不过,如后述那样,液状第1底填料使用粘度比液状第2底填料高的材料。
下面,对本实施方式的半导体器件100的制造方法进行说明。图3和图4是表示实施方式的半导体器件的制造工序的工序图,图3是基于半导体器件的概略俯视图所表示的工序图,图4是基于半导体器件的概略剖面图所表示的工序图。
首先,准备转接板10、第1半导体芯片20A、和第2半导体芯片20B。
然后,如图3(A)和图4(A)所示,把第1半导体芯片20A通过倒装片式连接,安装在该转接板10的芯片安装区域11上,使其作为外部端子的凸点21A面对转接板10。
同样,第2半导体芯片20B,也通过倒装片式连接,安装在该转接板10的芯片安装区域11上,使得其作为外部端子的凸点21B面对转接板10。
然后,如图3(B)和图4(B)所示那样,对于第1半导体芯片20A的4个端边22A、23A、24A、25A中从端边到与该端边相对的转接板10的焊盘12的距离最短的3个端边22A、23A、24A,向该3个端边22A、23A、24A与转接板10的间隙填充液状第1底填料31。该填充例如可采用由针连续供给的方法、和以一定的时间滴下一定量的方法等来实施。
这里,所使用的液状第1底填料31,其粘度比后述的液状第2底填料41的粘度高。具体是,例如作为液状第1底填料31使用的底填料,其粘度例如为(25℃)40~100Pa·s(理想的是50~70Pa·s),在填充后,在基板面上不蔓延,而维持其形状。
另外,将液状第1底填料31填充为:具有至少1个成为固化后的第1底填料30的未密封部50的未填充部51。在本实施方式中,将液状第1底填料31填充为:对填充在一个端边与转接板10之间的液状第1底填料31设置2个未填充部51,在相邻的端边与转接板10之间填充的液状第1底填料31之间也设置未填充部51。
另外,液状第1底填料31的填充是在开始了把转接板10加热到使该液状第1底填料31固化的温度(例如100~120℃)后进行。由此,同时进行液状第1底填料31的填充、和该液状第1底填料31的固化(即,利用第1底填料30的密封)。
液状第1底填料31的固化(即,利用第1底填料30的密封)虽然也可以在填充了液状第1底填料31后通过加热基板等来进行,但由于通过同时进行液状第1底填料31的填充、和该液状第1底填料31的固化(即、利用第1底填料30的密封),能够在维持了液状第1底填料31的填充形状的状态下立即固化,所以对于设于第1底填料30的未密封部50(未填充部51),能够形成在任意部位且形成得较小。
然后,如图3(C)和图4(C)所示那样,在通常的作业温度(例如25℃)下,在保持于转接板10上的状态下,对除了被第1底填料30所密封的间隙以外的、第1半导体芯片与转接板10的间隙和第2半导体芯片20B与转接板10的间隙填充液状第2底填料41。然后,通过加热基板等使液状第2底填料41固化,利用第2底填料40密封。
这里,所使用的液状第2底填料41,其粘度比液状第1底填料31的粘度低。具体是,例如作为液状第2底填料41使用的底填料,其粘度例如为(25℃)0.1~30Pa·s(理想的是1~20Pa·s),其流动性好,不产生气泡和未填充。
这样,可制造出本实施方式的半导体器件100。
对于以上说明的本实施方式的半导体器件100,向所安装的半导体芯片的4个端边中至少从端边到和该端边相对的转接板10的焊盘12的距离最短的端边、与转接板10之间的间隙填充液状第1底填料31,并使其固化,而利用第1底填料30把其密封。然后,通过向除了被第1底填料30密封了的间隙以外的、半导体芯片与转接板之间的间隙,填充液状第2底填料,并使其固化,而利用第2底填料40进行密封。
该密封了的第1底填料31在填充液状第2底填料41时,起到围堰部件(堤坝)的作用,抑制了第2底填料40的溢出,使其不能流到转接板10的焊盘12上。而且,第1底填料与第2底填料40一样,可只通过进行填充、固化等操作来形成。另外,由于不需要围堰部件,所以还能够缩短半导体芯片的端边与外部端子的距离。
另外,如果使用粘度比液状第2底填料41高的液状第1底填料31,则在填充时不会在转接板10上蔓延,液状第1底填料31难以流到转接板10的焊盘12上。并且,由于是高粘度,所以容易维持液状第1底填料31的填充形状,从而对于设在第1底填料30上的未密封部50(未填充部51),可容易地形成在任意部位并且形成得较小。
因此,能够以简易且低成本的方式抑制底填料(密封树脂)的溢出,实现良好的密封质量。
而且,由于在填充液状第1底填料31时,设置了未填充部51,并且在通过把其固化而得到的第1底填料30上设有未密封部50,所以,该未密封部50作为排出空气的孔而发挥作用,液状第2底填料41被填充成与第1底填料30之间不会存在间隙(未填充部),从而可实现更良好的密封质量。
另外,在上述的实施方式中,说明了安装了2个半导体芯片20A、20B的方式,但不限于此,也可以是安装了1个或3个以上的多个半导体芯片的方式。
这里,在只安装一个半导体芯片的情况下,如图5和图6所示,最好以使半导体芯片20的中心与转接板10的中心错开的方式,即、以使半导体芯片20偏置于转接板10上的芯片安装区域上的方式安装半导体芯片20。由此,能够使半导体芯片20的4个端边中的至少一个端边与相对的转接板10的作为外部端子的焊盘12的距离比其他端边近。具体是,通过使至少1个端边与相对的转接板10的作为外部端子的焊盘12的距离比其他端边远,来确保液状第2底填料41的填充位置。
然后,与上述本实施方式一样,对所安装的半导体芯片20的4个端边中至少从端边到和该端边相对的转接板的焊盘的距离最短的端边、与转接板之间的间隙,填充粘度比液状第2底填料高的液状第1底填料31,并使其固化,而利用第1底填料30进行密封。然后,对除了利用第1底填料30密封的间隙以外的、半导体芯片与转接板的间隙,填充液状第2底填料,并使其固化,而利用第2底填料40进行密封。由此,即使是安装一个半导体芯片的方式,也能够以简易且低成本的方式抑制底填料(密封树脂)的溢出,实现良好的密封质量。
另外,图5是表示其他实施方式的半导体器件的概略俯视图。图6是表示其他实施方式的半导体器件的概略剖面图。图6是图5的B-B剖面图。
另外,在本实施方式中,说明了在2个半导体芯片20A、20B上,都设置了底填料30(或者是液状第1底填料31)的方式,但例如在安装多个半导体芯片的方式中,对于该多个半导体芯片中的其所有端边与转接板10的焊盘12的距离为充分远的半导体芯片,不需要设置第1底填料30。
另外,在本实施方式中,说明了同时进行液状第1底填料31的填充及其固化的方式,但也可以是在填充了液状第1底填料31后进行固化的方式。另外,也可以是在填充了液状第1底填料31后,填充液状第2底填料41,然后,使液状第1底填料31和液状第2底填料41同时固化的方式。此方式与上述实施方式相比,可减少工时。另外,在此方式的情况下,被填充的液状第1底填料31由于是高粘度所以可充分维持填充形状,因此可起到作为填充液状第2底填料41时的围堰部件的作用。
另外,在本实施方式中,说明了作为液状第1底填料31而使用了粘度比液状第2底填料41高的高粘度底填料的方式,但不限于此,如果调整液状第1底填料31的固化温度,则也可以使用粘度与第2底填料41的粘度相同或在其以下的低粘度底填料。
另外,关于上述实施方式,不应被解释为对本发明的限定,不言而喻,在满足本发明的特征的范围内,都可实现本发明。
Claims (8)
1.一种半导体器件的制造方法,其特征在于,包括:
第1工序,准备在芯片安装区域的周围形成了外部端子的安装基板;
第2工序,准备具有多个端边的半导体芯片;
第3工序,把上述半导体芯片安装在上述安装基板上;
第4工序,向上述半导体芯片的上述端边中从该端边到和该端边相对的上述外部端子的距离最短的端边、与上述安装基板的第1间隙的至少一部分,填充第1密封树脂;
第5工序,使上述第1密封树脂固化而密封上述第1间隙;
第6工序,向除了填充了上述第1密封树脂的上述第1间隙或由上述第1密封树脂密封了的上述第1间隙以外的、上述半导体芯片与上述安装基板的第2间隙,填充第2密封树脂;以及
第7工序,使上述第2密封树脂固化而密封上述第2间隙。
2.根据权利要求1所述的半导体器件的制造方法,其特征在于,上述第1密封树脂的粘度比第2密封树脂的粘度高。
3.根据权利要求1或2所述的半导体器件的制造方法,其特征在于,
在上述第4工序中,以设置至少1个以上的未填充区域的方式向上述第1间隙填充第1密封树脂。
4.根据权利要求1至3中任意一项所述的半导体器件的制造方法,其特征在于,在上述第4工序中,在开始了对上述安装基板的加热后,向上述第1间隙填充上述第1密封树脂,并同时进行上述第5工序的上述第1密封树脂的固化。
5.根据权利要求1至3中任意一项所述的半导体器件的制造方法,其特征在于,同时进行上述第5工序的上述第1密封树脂的固化、和上述第7工序的上述第2密封树脂的固化。
6.根据权利要求1至5中任意一项所述的半导体器件的制造方法,其特征在于,在上述第3工序中,上述半导体芯片为一个,以使上述半导体芯片的中心与上述安装基板的中心错开的方式,把上述半导体芯片安装在上述安装基板上。
7.一种半导体器件,其特征在于,具有:
安装基板,具有芯片安装区域、包围该芯片安装区域的外周区域、形成在该外周区域上的外部端子、以及形成于该芯片安装区域和该外周区域并与外部端子连接的布线;
半导体芯片,具有多个端边,与上述布线连接,并且安装在上述安装基板上;
第1密封树脂,对上述半导体芯片的上述端边中从该端边到和该端边相对的上述外部端子的距离最短的端边、与上述安装基板的第1间隙的至少一部分进行密封;以及
第2密封树脂,对除了由上述第1密封树脂密封的上述第1间隙以外的、上述半导体芯片与上述安装基板的第2间隙进行密封。
8.根据权利要求7所述的半导体器件,其特征在于,上述半导体芯片为一个,上述半导体芯片以使上述半导体芯片的中心与上述安装基板的中心错开的方式安装在上述安装基板上。
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CN102779795A (zh) * | 2011-05-13 | 2012-11-14 | 松下电器产业株式会社 | 半导体装置及半导体装置的制造方法 |
TWI571387B (zh) * | 2014-06-23 | 2017-02-21 | 羅門哈斯電子材料有限公司 | 預施加底部填充劑 |
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JP5168160B2 (ja) | 2009-01-15 | 2013-03-21 | ソニー株式会社 | 半導体装置及び半導体装置の製造方法 |
WO2011031657A1 (en) * | 2009-09-08 | 2011-03-17 | Centocor Ortho Biotech Inc. | Use of an anti-il6 antibody to decrease hepcidin in cancer patients |
US8691626B2 (en) * | 2010-09-09 | 2014-04-08 | Advanced Micro Devices, Inc. | Semiconductor chip device with underfill |
US9373559B2 (en) * | 2014-03-05 | 2016-06-21 | International Business Machines Corporation | Low-stress dual underfill packaging |
JP6591234B2 (ja) | 2015-08-21 | 2019-10-16 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
KR102374107B1 (ko) | 2015-10-07 | 2022-03-14 | 삼성전자주식회사 | 반도체 패키지 제조 방법 |
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US10937755B2 (en) | 2018-06-29 | 2021-03-02 | Advanced Micro Devices, Inc. | Bond pads for low temperature hybrid bonding |
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JPH05144875A (ja) * | 1991-11-18 | 1993-06-11 | Sharp Corp | 配線基板の実装方法 |
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JP2003234362A (ja) | 2002-02-12 | 2003-08-22 | Yokogawa Electric Corp | 半導体装置 |
JP2004179576A (ja) | 2002-11-29 | 2004-06-24 | Ngk Spark Plug Co Ltd | 配線基板及びその製造方法 |
JP4415717B2 (ja) | 2004-03-23 | 2010-02-17 | ソニー株式会社 | 半導体装置及びその製造方法 |
JP2006140327A (ja) | 2004-11-12 | 2006-06-01 | Matsushita Electric Ind Co Ltd | 配線基板およびこれを用いた電子部品の実装方法 |
CN100394569C (zh) * | 2005-07-06 | 2008-06-11 | 乾坤科技股份有限公司 | 防止封装元件溢胶的方法 |
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CN102779795A (zh) * | 2011-05-13 | 2012-11-14 | 松下电器产业株式会社 | 半导体装置及半导体装置的制造方法 |
TWI571387B (zh) * | 2014-06-23 | 2017-02-21 | 羅門哈斯電子材料有限公司 | 預施加底部填充劑 |
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