JPH11260851A - 半導体装置及び該半導体装置の製造方法 - Google Patents

半導体装置及び該半導体装置の製造方法

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Publication number
JPH11260851A
JPH11260851A JP10060040A JP6004098A JPH11260851A JP H11260851 A JPH11260851 A JP H11260851A JP 10060040 A JP10060040 A JP 10060040A JP 6004098 A JP6004098 A JP 6004098A JP H11260851 A JPH11260851 A JP H11260851A
Authority
JP
Japan
Prior art keywords
semiconductor chip
electrode
semiconductor
pad electrode
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10060040A
Other languages
English (en)
Other versions
JP3891678B2 (ja
Inventor
Toshiaki Sugimura
利明 杉村
Kazuto Nishida
一人 西田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP06004098A priority Critical patent/JP3891678B2/ja
Publication of JPH11260851A publication Critical patent/JPH11260851A/ja
Application granted granted Critical
Publication of JP3891678B2 publication Critical patent/JP3891678B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

(57)【要約】 【課題】 高集積化された半導体装置であって従来より
も面積を縮小化した半導体装置、及び該半導体装置の製
造方法を提供する。 【解決手段】 多層基板１１０と、第１半導体チップ１
１１と、第２半導体チップ１１２とを備える。上記多層
基板は、対向する一方の側面に上記第１半導体チップが
フリップチップ装着される第１パッド電極１２４及び上
記第２半導体チップの第２電極１３６と電気的に接続さ
れる第２パッド電極１２５を有し、他方の側面に上記第
１パッド電極及び上記第２パッド電極と電気的に接続さ
れる第３パッド電極１２６を有する。よって従来の内部
リードは不要となり、半導体装置全体の面積を縮小する
ことができる。又、上記第１半導体チップ上に第２半導
体チップを重ねることでより集積化を図ることができ
る。

Description

【発明の詳細な説明】
【０００１】
【発明の属する技術分野】本発明は、基板上にフリップ
チップ実装した第１のＩＣ上に第２のＩＣを固定し該第
２ＩＣと上記基板とを電気的に接続した半導体装置、及
び該半導体装置の製造方法に関する。
【０００２】
【従来の技術及び発明が解決しようとする課題】ＬＳＩ
（大規模集積回路）は、長年Ｓｉ基板上に平面的に設計
され形成されてきており、その配線ルールからもわかる
ようにますます微細化が進んでいる。しかしながら上記
微細化の追求は、製造コストの上昇や製造方法の困難さ
を招くことが懸念されている。そのため三次元的にデバ
イスを構成することが提案されている。例えば特開平３
−１６９０６２号公報には、図１３に示すようなＱＦＰ
（Quad Flat Gull Wing Leaded Package）形態の半導体
デバイス２０が開示されている。該半導体デバイス２０
では、アイランド５上に第１半導体チップ１が固定さ
れ、該第１半導体チップ１上に形成されたパッド電極８
にバンプ３を介して第２半導体チップ２がフリップチッ
プ実装されている。さらに、第１半導体チップ１におい
て、当該第１半導体チップ１に載置された第２半導体チ
ップ２の周囲部分に存在するパッド電極７と内部リード
６の一端部との間に金属の細線４がボンディングされ
る。そして内部リード６の他端部を外部に露出させるよ
うにして第１半導体チップ１、第２半導体チップ２、金
属細線４等が樹脂材９にて封止される。
【０００３】しかしながら上述のように構成される半導
体デバイス２０では、第１半導体チップ１及び第２半導
体チップ２と内部リード６とを電気的に接続するため、
第１半導体チップ１上にて当該第１半導体チップ１の周
囲に沿って形成されているパッド電極７を利用する。し
たがって、第１半導体チップ１にフリップチップ実装さ
れる第２半導体チップ２の平面的な大きさは、上記パッ
ド電極７に干渉しないようにパッド電極７よりも内側の
面積に相当する大きさに限定される。即ち、第２半導体
チップ２は第１半導体チップ１よりも平面的に小さくな
ければならないという制限がある。又、内部リード６へ
金属細線４をボンディングすることから、上記ＱＦＰ構
造のパッケージサイズが大きくなるという問題もある。
本発明はこのような問題点を解決するためになされたも
ので、高集積化された半導体装置であって従来よりも面
積を縮小化した半導体装置、及び該半導体装置の製造方
法を提供することを目的とする。
【０００４】
【課題を解決するための手段】本発明の第１態様の半導
体装置は、第１電極形成面に第１電極を有し該第１電極
がフリップチップ装着される第１半導体チップと、上記
第１半導体チップとほぼ同等の面積を占め、かつ上記第
１半導体チップの上記第１電極形成面に対向する第１電
極非形成面のほぼ全面に対向して配置される第２電極非
形成面を有する第２半導体チップと、対向する２つの側
面の一方には上記第１半導体チップの上記第１電極がフ
リップチップ装着される第１パッド電極、及び上記第２
電極非形成面に対向する上記第２半導体チップの第２電
極形成面に形成されている第２電極と金属線を介して接
続される第２パッド電極を有し、他方には第３パッド電
極を有し上記第１及び第２パッド電極と上記第３パッド
電極とを電気的に接続した基板と、を備えたことを特徴
とする。
【０００５】本発明の第２態様の半導体装置の製造方法
は、対向する２つの側面の一方には第１パッド電極及び
第２パッド電極を有し、他方には第３パッド電極を有し
上記第１及び第２パッド電極と上記第３パッド電極とを
電気的に接続した基板における上記第１パッド電極と、
第１半導体チップの第１電極形成面に形成された第１電
極とをフリップチップ装着し、上記第１半導体チップに
おいて上記第１電極形成面に対向する第１電極非形成面
と、上記第１半導体チップとほぼ同等の面積を有し上記
第１電極非形成面のほぼ全面に対向して配置される第２
半導体チップの第２電極非形成面とを対向させて固定
し、上記第１半導体チップ及び上記第２半導体チップが
上記基板に取り付けられた後、上記第２半導体チップに
おいて上記第２電極非形成面に対向する第２電極形成面
に形成される第２電極と上記基板の上記第２パッド電極
とを金属線にて電気的に接続する、ことを特徴とする。
【０００６】
【発明の実施の形態】本発明の実施形態における半導体
装置、及び該半導体装置の製造方法について図を参照し
ながら以下に説明する。尚、各図において同じ構成部分
については同じ符号を付している。図１に示すように本
実施形態の半導体装置１０１は、大別して、多層基板１
１０と、第１半導体チップ１１１と、第２半導体チップ
１１２とを有する。キャリアと呼ばれるインターポーザ
としての多層基板１１０は、図２又は図９に示すよう
に、一辺が例えば１１ｍｍの方形状の平面形状にてな
り、例えばセラミクスや樹脂材料にてなる板材１２１を
複数の層に積層して形成され、その厚み方向において対
向する２つの側面１２２，１２３の内、一方の側面１２
２には上記第１半導体チップ１１１をフリップチップ装
着する第１パッド電極１２４、及び上記第２半導体チッ
プ１１２の第２電極１３６と金属線１３７にて電気的に
接続される第２パッド電極１２５が形成される。尚、本
実施形態では、多層基板１１０の周囲に沿って第２パッ
ド電極１２５を形成し、その内側に第１パッド電極１２
４が形成されている。他方の側面１２３には、当該半導
体装置１１０を例えばプリント基板に電気的に接続する
ための第３パッド電極１２６が形成されている。尚、第
３パッド電極１２６としては、ＬＧＡ（ランドグリッド
アレイ）タイプや、ＢＧＡ（ボールグリッドアレイ）タ
イプが使用可能である。第１パッド電極１２４及び第２
パッド電極１２５と、第３パッド電極１２６とを電気的
に接続するために、上記板材１２１には、ビア１２７が
板材１２１の板厚方向や延在方向等に沿って形成されて
いる。尚、上記「多層」とは、上記延在方向に沿って形
成される上記ビア１２７が上記板厚方向に複数層に形成
されていることを意味する。よって多層基板１１０は必
ずしも上記板材１２１が積層されているものに限定され
ず、ビア１２７が複数層に形成されている限り板材１２
１は一枚から構成される場合もある。このように多層基
板１１０を使用することで、上記第２パッド電極１２５
は第３パッド電極１２６のいずれかに接続されるので、
図１３に示すような内部リード６を設ける必要はなく半
導体装置の面積を縮小化することができる。
【０００７】第１半導体チップ１１１及び第２半導体チ
ップ１１２は、本実施形態では、シリコンウエハ上に集
積回路を形成したチップそのもの、いわゆるベアチップ
であるが、これに限定することなく本明細書にて使用す
る「半導体チップ」は集積回路を形成したシリコンチッ
プを封止してなる、図１２に示すようないわゆるＣＳＰ
（チップサイズパッケージ）のような構造までも含む概
念である。第１半導体チップ１１１は、図９に示すよう
に、一辺が例えば３〜２０ｍｍの方形状の平面形状にて
なり上記第２パッド電極１２５の内側に配置されるよう
に多層基板１１０よりも小さい面積にてなる。第１半導
体チップ１１１の厚み方向における一側面である第１電
極形成面１２８には、一若しくは複数の第１電極１２９
が形成されている。該第１電極１２９には、図９の
（ａ）から（ｃ）に示すように、バンプ１３０が形成さ
れた後、銀を含む導電性ペースト１３１が転写される。
このような第１半導体チップ１１１は、当該第１半導体
チップ１１１に形成されている第１電極１２９に対応し
て多層基板１１０の側面１２２に形成されている上記第
１パッド電極１２４と、上記導電性ペースト１３１を介
して上記バンプ１３０との電気的接続を図り、多層基板
１１０の側面１２２にフリップチップ装着される。又、
該取り付け後、第１半導体チップ１１１と多層基板１１
０の側面１２２との隙間には、図９の（ｃ）に示すよう
に封止材注入ノズル１３２から第１封止材１３３が注入
され上記隙間の封止が行われる。
【０００８】図９の（ｅ）に示すように、第２半導体チ
ップ１１２も上述の第１半導体チップ１１１と同様に方
形状の平面形状にてなり、本実施形態では第１半導体チ
ップ１１１とほぼ同等の面積を占める。第２半導体チッ
プ１１２の厚み方向における一側面である第２電極形成
面１３５には、一若しくは複数の第２電極１３６が形成
されている。尚、該第２半導体チップ１１２として、例
えばペルチエ素子を用いることができ第１半導体チップ
１１１の冷却を行うことができる。このような第１半導
体チップ１１１及び第２半導体チップ１１２について、
図９の（ｄ）に示すように、第１半導体チップ１１１の
第１電極形成面１２８に対向する第１電極非形成面１３
４と、第２半導体チップ１１２の第２電極形成面１３５
に対向する第２電極非形成面１３８とを接着剤１３９に
て接着し、多層基板１１０にフリップチップ装着された
第１半導体チップ１１１に第２半導体チップ１１２が固
定される。このとき、本実施形態では、第１半導体チッ
プ１１１の第１電極非形成面１３４のほぼ全面が第２半
導体チップ１１２の第２電極非形成面１３８の載置面と
なる。よって、図１３に示すように第２半導体チップ２
が第１半導体チップ１よりも小さくなるという現象は、
本実施形態では生じない。尚、上記第２電極１３６は上
述のように又図９の（ｆ）に示すように金属線１３７に
て上記第２パッド電極１２５に電気的に接続される。
【０００９】第１半導体チップ１１１と第２半導体チッ
プ１１２との固定を本実施形態では上述のように接着剤
１３９にて行ったが、これに限定されるものではなく、
凹、凸部材による係合等による例えば機械的な接合にて
行うこともできる。金属線１３７にて上記第２電極１３
６と上記第２パッド電極１２５との電気的接続が図られ
た後、該金属線１３７、第１半導体チップ１１１、及び
第２半導体チップ１１２を封止するために、多層基板１
１０の側面１２２上に第２封止材１４０が塗布される。
図９を参照して上述した当該半導体装置１０１の製造方
法において、従来のフリップチップ装着技術や、ワイヤ
ボンディング技術を使用することができるので、従来の
製造工程の途中に、例えば第１半導体チップ１１１上に
第２半導体チップ１１２を固定する工程等を組み込むこ
とができる。よって、新たに製造工程を開発する必要が
なく、コストアップを抑えることができる。
【００１０】第２半導体チップ１１２を第１半導体チッ
プ１１１と平面的にほぼ同等の大きさとすることで、従
来の内部リード６が不要である多層基板１１０との相乗
効果により、従来に比べて回路の高集積化、及び面積の
縮小化を図ることができる。詳しく説明すると、第１半
導体チップ１１１において、フリップチップ装着により
第１半導体チップ１１１の第１電極１２９と多層基板１
１０の第１パッド電極１２４とは電気的に接続される。
一方、このような状態において第２半導体チップ１１２
における電気的接続を図るためには、金属線１３７を介
して第２電極１３６に電気的接続される多層基板１１０
の第２パッド電極１２５は、第１半導体チップ１１１の
占有領域の周縁部に配置することになる。このような状
態において面積の縮小化を図るために、第２パッド電極
１２５が形成されている多層基板１１０の側面１２２に
対向する側面１２３に第３パッド電極１２６を形成し、
多層基板１１０内に形成したビア１２７により上記第２
パッド電極１２５と上記第３パッド電極１２６の一部と
を電気的に接続した。このように構成することで、図１
３に示すように内部リード６を設ける必要がなくなり、
半導体装置全体の面積の縮小化を図ることができる。上
述のように、第１半導体チップ１１１の第１電極非形成
面１３４と第２半導体チップ１１２の第２電極非形成面
１３８とを対向させ、第２電極１３６と上記第２パッド
電極１２５とを金属線１３７にて電気的接続を図ったこ
とから、第１半導体チップ１１１と同等の大きさにてな
る第２半導体チップ１１２を使用することができ、回路
の高集積化を図ることができる。
【００１１】図９を参照した上述の説明では、多層基板
１１０に第１半導体チップ１１１をフリップチップ装着
した後に、該第１半導体チップ１１１上に第２半導体チ
ップ１１２を固定したが、この工程順に限定されるもの
ではない。即ち、まず、第１半導体チップ１１１の第１
電極非形成面１３４と、第２半導体チップ１１２の第２
電極非形成面１３８とを接着剤１３９にて接着した後、
第１半導体チップ１１１を多層基板１１０にフリップチ
ップ装着してもよい。
【００１２】上述の半導体装置１０１は、第１半導体チ
ップ１１１及び第２半導体チップ１１２がともに一つの
チップから構成される場合であるが、これに限定される
ものではない。即ち、図３に示す半導体装置１０２のよ
うに上記第１半導体チップを複数のチップ１５１，１５
２にて構成することもできる。この場合、チップ１５１
の厚み寸法ｔ１と、チップ１５２の厚み寸法ｔ２とを同
寸法とすることで、これらのチップ１５１，１５２上に
上記第２半導体チップ１１２を載置することができ、か
つ該第２半導体チップ１１２は、個々のチップ１５１，
１５２における大きさよりも大きいものを使用すること
ができる。
【００１３】又、上記半導体装置１０２の場合、多層基
板１１０にフリップチップ装着された例えば２つのチッ
プ１５１及びチップ１５２について、上述のように第１
封止材１３３にて上記隙間の封止が行われるが、図１０
に示すように２つのチップ１５１，１５２に挟まれた部
分１５３に注入される第１封止材１３３によって、積み
重ねられる上記第２半導体チップ１１２の固定をも行う
こともできる。即ち、チップ１５１，１５２と第２半導
体チップ１１２とを接着剤１３９を用いて接着するので
はなく、第１封止材１３３に上記接着剤１３９の作用を
も兼ねされる。このようにすることで、第１封止材１３
３の硬化、並びに接着剤１３９の塗布及び硬化の工程を
一度に済ますことができ、製造時間の短縮を図ることが
できる。
【００１４】又、図４に示す半導体装置１０３のよう
に、一つの第１半導体チップ１１１に対して上記第２半
導体チップを複数の、例えば２つのチップ１５５，１５
６にて構成してもよい。さらに、上述の半導体装置１０
２と半導体装置１０３とをミックスし、図５に示す半導
体装置１０４のように、上記第１半導体チップ及び上記
第２半導体チップの両方をそれぞれ複数のチップにて構
成してもよい。
【００１５】又、図６に示すような半導体装置１０５を
構成することもできる。半導体装置１０５は、上述の例
えば半導体装置１０１において、多層基板１１０の側面
１２２に形成されている第２パッド電極１２５と、それ
に隣接する第１パッド電極１２４との間に、図１１に詳
しく示すような流出防止部１６０を設けている。流出防
止部１６０は、例えばセラミック材にて形成したり、ガ
ラス材をプリントして形成したり、シート材から形成し
たりする。上述のように第１半導体チップ１１１が多層
基板１１０にフリップチップ装着された後、第１半導体
チップ１１１の第１電極形成面１２８と多層基板１１０
の側面１２２との間には第１封止材１３３が注入される
が、該第１封止材１３３が第２パッド電極１２５へ流れ
出ないように、上記流出防止部１６０は、堰として作用
し上記第１封止材１３３の流出を防止する。多層基板１
１０の厚み方向に沿った流出防止部１６０の高さは、封
止される第１半導体チップ１１１の大きさ、又は上記第
１封止材１３３の使用量によって変動し、当然ながら第
１封止材１３３が第２パッド電極１２５側へ溢れ出ない
ような高さ、例えば５０〜５００μｍの高さに設定され
る。このような流出防止部１６０を設けることで、第１
封止材１３３が流れる領域を規定することができること
から、第２パッド電極１２５の設置位置に余裕を持たせ
る必要がなくなり、多層基板１１０の平面面積を縮小す
ることができ、よって半導体装置全体の面積の縮小化を
図ることができる。又、第１封止材１３３が第２パッド
電極１２５に付着し金属線１３７の接続を阻害するとい
う現象の発生を抑えることもできる。尚、図１１では、
多層基板１１０の長手方向に沿って第２パッド電極１２
５が配列されていることから、流出防止部１６０も上記
長手方向に沿って第２パッド電極１２５と第１パッド電
極１２４との間に形成しているが、これに限定されるも
のではない。即ち、もし上記長手方向に直交方向に沿っ
て、多層基板１１０に第２パッド電極１２５が形成され
ているときには、それに対応して、流出防止部１６０を
形成する。よって、多層基板１１０上に方形状に流出防
止部１６０が形成される場合もある。
【００１６】又、流出防止部１６０は、上述のように多
層基板１１０の側面１２２に突設されるタイプに限定さ
れるものではない。即ち、図７に示すように、多層基板
１６１の側面１２２に形成した第２パッド電極１２５と
第１パッド電極１２４との間に、流出する第１封止材１
３３を受け止める凹部にてなる流出防止部１６２を形成
してもよい。尚、流出防止部１６２の深さは、封止され
る第１半導体チップ１１１の大きさ、又は上記第１封止
材１３３の使用量によって変動し、当然ながら第１封止
材１３３が第２パッド電極１２５側へ溢れ出ないような
深さ、例えば５０〜２００μｍの深さに設定される。
【００１７】さらに又、図８に示すような流出防止部１
６３を設けることもできる。流出防止部１６３は、多層
基板１１０の側面１２２に形成される上記第２パッド電
極１２５における、上記多層基板１１０の厚み方向に沿
った厚みを大きくしたものであり、上記第２パッド電極
としての機能をも兼ねる。該流出防止部１６３の厚み
は、封止される第１半導体チップ１１１の大きさ、又は
上記第１封止材１３３の使用量によって変動し、当然な
がら第１封止材１３３が第２パッド電極１２５側へ溢れ
出ないような高さ、例えば５０〜５００μｍの高さに設
定される。
【００１８】尚、図７及び図８では、流出防止部１６３
に主に関係する部分を図示しているので、第２封止材１
４０等の図示は省略している。又、上述した流出防止部
１６０，１６２，１６３のいずれかを、図３から図５に
示す半導体装置１０２〜１０４に適用することももちろ
ん可能である。
【００１９】又、上述の実施形態では、第１半導体チッ
プ１１１の第１電極１２９と、多層基板１１０の第１パ
ッド電極１２４とはバンプ１３０及びペースト１３１を
介して電気的接続を図っているが、これに限定されるも
のではない。例えば、金属粒を含む導電性ペーストを例
えば上記第１電極１２９に塗布した後、第１電極１２９
と第１パッド電極１２４とを圧接し上記金属粒を潰すこ
とで第１電極１２９と第１パッド電極との導通を図って
も良い。
【００２０】
【発明の効果】以上詳述したように本発明の第１態様の
半導体装置、及び第２態様の半導体装置の製造方法によ
れば、多層基板と、第１半導体チップと、第２半導体チ
ップとを備える。上記多層基板は、対向する一方の側面
に上記第１半導体チップがフリップチップ装着される第
１パッド電極及び上記第２半導体チップの第２電極と電
気的に接続される第２パッド電極を有し、他方の側面に
上記第１パッド電極及び上記第２パッド電極と電気的に
接続される第３パッド電極を有する。よって、例えば上
記多層基板の厚み方向に直交する平面方向に延在する、
従来の内部リードは不要となり、半導体装置全体の面積
を縮小することができる。さらに又、上記第１半導体チ
ップと上記第２半導体チップとは同等の平面面積を有
し、上記第１半導体チップ上に上記第２半導体チップを
載置する。このように構成することで、当該半導体装置
における回路の集積化を向上させることができる。
【図面の簡単な説明】
【図１】 本発明の実施形態における半導体装置の断面
図である。
【図２】 図１に示す多層基板、及び該多層基板と第１
半導体チップとの装着部分の拡大図である。
【図３】 図１に示す半導体装置の他の実施形態におけ
る断面図である。
【図４】 図１に示す半導体装置の別の実施形態におけ
る断面図である。
【図５】 図１に示す半導体装置のさらに他の実施形態
における断面図である。
【図６】 図１に示す半導体装置のさらに別の実施形態
における断面図である。
【図７】 図５に示す流出防止部の他の実施形態を示す
図である。
【図８】 図５に示す流出防止部の別の実施形態を示す
図である。
【図９】 図１に示す半導体装置の製造方法を説明する
ための斜視図である。
【図１０】 図３に示す半導体装置における第１半導体
チップ部分の封止を行うときの状態を示す斜視図であ
る。
【図１１】 図６に示す流出防止部を示す斜視図であ
る。
【図１２】 図１に示す半導体装置の変形例における断
面図である。
【図１３】 従来の半導体装置を示す断面図である。
【符号の説明】
１０１，１０２，１０３，１０４，１０５…半導体装
置、１１０…多層基板、１１１…第１半導体チップ、１
１２…第２半導体チップ、１２１…板材、１２２，１２
３…側面、１２４…第１パッド電極、１２５…第２パッ
ド電極、１２６…第３パッド電極、１２８…第１電極形
成面、１２９…第１電極、１３３…第１封止材、１３４
…第１電極非形成面、１３５…第２電極形成面、１３６
…第２電極、１３７…金属線、１３８…第２電極非形成
面、１３９…接着剤、１４０…第２封止材、１５１，１
５２，１５５，１５６…チップ、１６０，１６２，１６
３…流出防止部。

Claims (10)

    【特許請求の範囲】
  1. 【請求項１】 第１電極形成面（１２８）に第１電極
    （１２９）を有し該第１電極がフリップチップ装着され
    る第１半導体チップ（１１１）と、 上記第１半導体チップとほぼ同等の面積を占め、かつ上
    記第１半導体チップの上記第１電極形成面に対向する第
    １電極非形成面（１３４）のほぼ全面に対向して配置さ
    れる第２電極非形成面（１３８）を有する第２半導体チ
    ップ（１１２）と、 対向する２つの側面（１２２，１２３）の一方には上記
    第１半導体チップの上記第１電極がフリップチップ装着
    される第１パッド電極（１２４）、及び上記第２電極非
    形成面に対向する上記第２半導体チップの第２電極形成
    面（１３５）に形成されている第２電極（１３６）と金
    属線（１３７）を介して接続される第２パッド電極（１
    ２５）を有し、他方には第３パッド電極（１２６）を有
    し上記第１及び第２パッド電極と上記第３パッド電極と
    を電気的に接続した基板（１１０）と、を備えたことを
    特徴とする半導体装置。
  2. 【請求項２】 上記第１半導体チップの上記第１電極非
    形成面と上記第２半導体チップの上記第２電極非形成面
    とは接着剤（１３９）にて固定される、請求項１記載の
    半導体装置。
  3. 【請求項３】 上記第１半導体チップは複数の半導体チ
    ップ（１５１，１５２）から構成される、請求項１又は
    ２に記載の半導体装置。
  4. 【請求項４】 上記第２半導体チップは複数の半導体チ
    ップ（１５５，１５６）から構成される、請求項１ない
    し３のいずれかに記載の半導体装置。
  5. 【請求項５】 上記基板において、上記第２パッド電極
    は該基板の上記一方の側面の周縁部分に配置され上記第
    １パッド電極はその内側に配置されるとき、上記第１パ
    ッド電極と上記第２パッド電極との間に設けられ上記基
    板に装着された上記第１半導体チップの封止を行う第１
    封止材（１３３）が上記第２パッド電極へ流出するのを
    防止する流出防止部（１６０，１６２，１６３）を有す
    る、請求項１ないし４のいずれかに記載の半導体装置。
  6. 【請求項６】 上記基板の上記一方の側面は第２封止材
    （１４０）にて封止される、請求項１ないし５のいずれ
    かに記載の半導体装置。
  7. 【請求項７】 上記第２半導体チップはペルチエ素子を
    構成する、請求項１ないし６のいずれかに記載の半導体
    装置。
  8. 【請求項８】 対向する２つの側面（１２２，１２３）
    の一方には第１パッド電極（１２４）及び第２パッド電
    極（１２５）を有し、他方には第３パッド電極（１２
    ６）を有し上記第１及び第２パッド電極と上記第３パッ
    ド電極とを電気的に接続した基板（１１０）における上
    記第１パッド電極と、第１半導体チップ（１１１）の第
    １電極形成面（１２８）に形成された第１電極（１２
    ９）とをフリップチップ装着し、 上記第１半導体チップにおいて上記第１電極形成面に対
    向する第１電極非形成面（１３４）と、上記第１半導体
    チップとほぼ同等の面積を有し上記第１電極非形成面の
    ほぼ全面に対向して配置される第２半導体チップ（１１
    ２）の第２電極非形成面（１３８）とを対向させて固定
    し、 上記第１半導体チップ及び上記第２半導体チップが上記
    基板に取り付けられた後、上記第２半導体チップにおい
    て上記第２電極非形成面に対向する第２電極形成面（１
    ３５）に形成される第２電極（１３６）と上記基板の上
    記第２パッド電極とを金属線（１３７）にて電気的に接
    続する、ことを特徴とする半導体装置の製造方法。
  9. 【請求項９】 上記基板に上記第１半導体チップをフリ
    ップチップ装着した後、上記第１半導体チップと上記基
    板との接続部分へ第１封止材（１３３）を塗布するとき
    該第１封止材が上記第２パッド電極まで流れるのを防止
    しながら塗布を行う、請求項８記載の半導体装置の製造
    方法。
  10. 【請求項１０】 上記基板に上記第１半導体チップをフ
    リップチップ装着した後に上記第１半導体チップに上記
    第２半導体チップを固定するとき、上記フリップチップ
    装着後、上記第１半導体チップと上記基板との接続部分
    への上記第１封止材の塗布により上記第１半導体チップ
    と上記第２半導体チップとの固定をも併せて行う、請求
    項８又は９記載の半導体装置の製造方法。
JP06004098A 1998-03-11 1998-03-11 半導体装置 Expired - Fee Related JP3891678B2 (ja)

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