JP3891678B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP3891678B2
JP3891678B2 JP06004098A JP6004098A JP3891678B2 JP 3891678 B2 JP3891678 B2 JP 3891678B2 JP 06004098 A JP06004098 A JP 06004098A JP 6004098 A JP6004098 A JP 6004098A JP 3891678 B2 JP3891678 B2 JP 3891678B2
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Japan
Prior art keywords
electrode
semiconductor chip
pad electrode
semiconductor
pad
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Expired - Fee Related
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JP06004098A
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English (en)
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JPH11260851A (ja
Inventor
利明 杉村
一人 西田
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Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
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Priority to JP06004098A priority Critical patent/JP3891678B2/ja
Publication of JPH11260851A publication Critical patent/JPH11260851A/ja
Application granted granted Critical
Publication of JP3891678B2 publication Critical patent/JP3891678B2/ja
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Description

【０００１】
【発明の属する技術分野】
本発明は、基板上にフリップチップ実装した第１のＩＣ上に第２のＩＣを固定し該第２ＩＣと上記基板とを電気的に接続した半導体装置、及び該半導体装置の製造方法に関する。
【０００２】
【従来の技術及び発明が解決しようとする課題】
ＬＳＩ（大規模集積回路）は、長年Ｓｉ基板上に平面的に設計され形成されてきており、その配線ルールからもわかるようにますます微細化が進んでいる。しかしながら上記微細化の追求は、製造コストの上昇や製造方法の困難さを招くことが懸念されている。そのため三次元的にデバイスを構成することが提案されている。例えば特開平３−１６９０６２号公報には、図１３に示すようなＱＦＰ（Quad Flat Gull Wing Leaded Package）形態の半導体デバイス２０が開示されている。該半導体デバイス２０では、アイランド５上に第１半導体チップ１が固定され、該第１半導体チップ１上に形成されたパッド電極８にバンプ３を介して第２半導体チップ２がフリップチップ実装されている。さらに、第１半導体チップ１において、当該第１半導体チップ１に載置された第２半導体チップ２の周囲部分に存在するパッド電極７と内部リード６の一端部との間に金属の細線４がボンディングされる。そして内部リード６の他端部を外部に露出させるようにして第１半導体チップ１、第２半導体チップ２、金属細線４等が樹脂材９にて封止される。
【０００３】
しかしながら上述のように構成される半導体デバイス２０では、第１半導体チップ１及び第２半導体チップ２と内部リード６とを電気的に接続するため、第１半導体チップ１上にて当該第１半導体チップ１の周囲に沿って形成されているパッド電極７を利用する。したがって、第１半導体チップ１にフリップチップ実装される第２半導体チップ２の平面的な大きさは、上記パッド電極７に干渉しないようにパッド電極７よりも内側の面積に相当する大きさに限定される。即ち、第２半導体チップ２は第１半導体チップ１よりも平面的に小さくなければならないという制限がある。又、内部リード６へ金属細線４をボンディングすることから、上記ＱＦＰ構造のパッケージサイズが大きくなるという問題もある。
本発明はこのような問題点を解決するためになされたもので、高集積化された半導体装置であって従来よりも面積を縮小化した半導体装置、及び該半導体装置の製造方法を提供することを目的とする。
【０００４】
【課題を解決するための手段】
本発明の第１態様の半導体装置は、互いに隙間を介して並設される複数の第１半導体チップであって、それぞれの第１電極形成面に第１電極を有し該第１電極がフリップチップ装着される第１半導体チップと、
複数の上記第１半導体チップに対応して設けられる一つの第２半導体チップであって、複数の上記第１半導体チップとほぼ同等の面積を占め、かつ複数の上記第１半導体チップの上記第１電極形成面に対向する第１電極非形成面のほぼ全面に対向して配置される第２電極非形成面を有する第２半導体チップと、
対向する２つの側面の一方には上記第１半導体チップの上記第１電極がフリップチップ装着される第１パッド電極、及び上記第２電極非形成面に対向する上記第２半導体チップの第２電極形成面に形成されている第２電極と金属線を介して接続される第２パッド電極を有し、他方には第３パッド電極を有し上記第１及び第２パッド電極と上記第３パッド電極とを電気的に接続した基板と、
上記第１パッド電極と上記第２パッド電極との間、及び互いに隣接する上記第１半導体チップ間における上記隙間に注入され、上記基板に装着された上記第１半導体チップの封止を行うとともに、上記第１半導体チップの上記第１電極非形成面と上記第２半導体チップの上記第２電極非形成面とを固定する第１封止材と、
を備えたことを特徴とする。
【０００５】
本発明の第２態様の半導体装置の製造方法は、対向する２つの側面の一方には第１パッド電極及び第２パッド電極を有し、他方には第３パッド電極を有し上記第１及び第２パッド電極と上記第３パッド電極とを電気的に接続した基板に対して複数の第１半導体チップを互いに隙間を介して配置して、それぞれの第１半導体チップの第１電極形成面に形成された第１電極と上記第１パッド電極とをフリップチップ装着し、
複数の上記第１半導体チップにおいて上記第１電極形成面に対向する第１電極非形成面と、複数の上記第１半導体チップとほぼ同等の面積を有し上記第１電極非形成面のほぼ全面に対向して配置される一つの第２半導体チップの第２電極非形成面とを対向させた状態にて、上記第１パッド電極と上記第２パッド電極との間、及び複数の上記第１半導体チップ間の上記隙間に第１封止材を注入することで、上記基板に装着された上記第１半導体チップの封止を行うとともに、上記第１半導体チップと上記第２半導体チップとの固定を行い、
上記第１半導体チップ及び上記第２半導体チップが上記基板に取り付けられた後、上記第２半導体チップにおいて上記第２電極非形成面に対向する第２電極形成面に形成される第２電極と上記基板の上記第２パッド電極とを金属線にて電気的に接続する、
ことを特徴とする。
【０００６】
【発明の実施の形態】
本発明の実施形態における半導体装置、及び該半導体装置の製造方法について図を参照しながら以下に説明する。尚、各図において同じ構成部分については同じ符号を付している。
図１に示すように本実施形態の半導体装置１０１は、大別して、多層基板１１０と、第１半導体チップ１１１と、第２半導体チップ１１２とを有する。キャリアと呼ばれるインターポーザとしての多層基板１１０は、図２又は図９に示すように、一辺が例えば１１ｍｍの方形状の平面形状にてなり、例えばセラミクスや樹脂材料にてなる板材１２１を複数の層に積層して形成され、その厚み方向において対向する２つの側面１２２，１２３の内、一方の側面１２２には上記第１半導体チップ１１１をフリップチップ装着する第１パッド電極１２４、及び上記第２半導体チップ１１２の第２電極１３６と金属線１３７にて電気的に接続される第２パッド電極１２５が形成される。尚、本実施形態では、多層基板１１０の周囲に沿って第２パッド電極１２５を形成し、その内側に第１パッド電極１２４が形成されている。他方の側面１２３には、当該半導体装置１１０を例えばプリント基板に電気的に接続するための第３パッド電極１２６が形成されている。尚、第３パッド電極１２６としては、ＬＧＡ（ランドグリッドアレイ）タイプや、ＢＧＡ（ボールグリッドアレイ）タイプが使用可能である。第１パッド電極１２４及び第２パッド電極１２５と、第３パッド電極１２６とを電気的に接続するために、上記板材１２１には、ビア１２７が板材１２１の板厚方向や延在方向等に沿って形成されている。
尚、上記「多層」とは、上記延在方向に沿って形成される上記ビア１２７が上記板厚方向に複数層に形成されていることを意味する。よって多層基板１１０は必ずしも上記板材１２１が積層されているものに限定されず、ビア１２７が複数層に形成されている限り板材１２１は一枚から構成される場合もある。
このように多層基板１１０を使用することで、上記第２パッド電極１２５は第３パッド電極１２６のいずれかに接続されるので、図１３に示すような内部リード６を設ける必要はなく半導体装置の面積を縮小化することができる。
【０００７】
第１半導体チップ１１１及び第２半導体チップ１１２は、本実施形態では、シリコンウエハ上に集積回路を形成したチップそのもの、いわゆるベアチップであるが、これに限定することなく本明細書にて使用する「半導体チップ」は集積回路を形成したシリコンチップを封止してなる、図１２に示すようないわゆるＣＳＰ（チップサイズパッケージ）のような構造までも含む概念である。
第１半導体チップ１１１は、図９に示すように、一辺が例えば３〜２０ｍｍの方形状の平面形状にてなり上記第２パッド電極１２５の内側に配置されるように多層基板１１０よりも小さい面積にてなる。第１半導体チップ１１１の厚み方向における一側面である第１電極形成面１２８には、一若しくは複数の第１電極１２９が形成されている。該第１電極１２９には、図９の（ａ）から（ｃ）に示すように、バンプ１３０が形成された後、銀を含む導電性ペースト１３１が転写される。このような第１半導体チップ１１１は、当該第１半導体チップ１１１に形成されている第１電極１２９に対応して多層基板１１０の側面１２２に形成されている上記第１パッド電極１２４と、上記導電性ペースト１３１を介して上記バンプ１３０との電気的接続を図り、多層基板１１０の側面１２２にフリップチップ装着される。又、該取り付け後、第１半導体チップ１１１と多層基板１１０の側面１２２との隙間には、図９の（ｃ）に示すように封止材注入ノズル１３２から第１封止材１３３が注入され上記隙間の封止が行われる。
【０００８】
図９の（ｅ）に示すように、第２半導体チップ１１２も上述の第１半導体チップ１１１と同様に方形状の平面形状にてなり、本実施形態では第１半導体チップ１１１とほぼ同等の面積を占める。第２半導体チップ１１２の厚み方向における一側面である第２電極形成面１３５には、一若しくは複数の第２電極１３６が形成されている。尚、該第２半導体チップ１１２として、例えばペルチエ素子を用いることができ第１半導体チップ１１１の冷却を行うことができる。
このような第１半導体チップ１１１及び第２半導体チップ１１２について、図９の（ｄ）に示すように、第１半導体チップ１１１の第１電極形成面１２８に対向する第１電極非形成面１３４と、第２半導体チップ１１２の第２電極形成面１３５に対向する第２電極非形成面１３８とを接着剤１３９にて接着し、多層基板１１０にフリップチップ装着された第１半導体チップ１１１に第２半導体チップ１１２が固定される。このとき、本実施形態では、第１半導体チップ１１１の第１電極非形成面１３４のほぼ全面が第２半導体チップ１１２の第２電極非形成面１３８の載置面となる。よって、図１３に示すように第２半導体チップ２が第１半導体チップ１よりも小さくなるという現象は、本実施形態では生じない。
尚、上記第２電極１３６は上述のように又図９の（ｆ）に示すように金属線１３７にて上記第２パッド電極１２５に電気的に接続される。
【０００９】
第１半導体チップ１１１と第２半導体チップ１１２との固定を本実施形態では上述のように接着剤１３９にて行ったが、これに限定されるものではなく、凹、凸部材による係合等による例えば機械的な接合にて行うこともできる。
金属線１３７にて上記第２電極１３６と上記第２パッド電極１２５との電気的接続が図られた後、該金属線１３７、第１半導体チップ１１１、及び第２半導体チップ１１２を封止するために、多層基板１１０の側面１２２上に第２封止材１４０が塗布される。
図９を参照して上述した当該半導体装置１０１の製造方法において、従来のフリップチップ装着技術や、ワイヤボンディング技術を使用することができるので、従来の製造工程の途中に、例えば第１半導体チップ１１１上に第２半導体チップ１１２を固定する工程等を組み込むことができる。よって、新たに製造工程を開発する必要がなく、コストアップを抑えることができる。
【００１０】
第２半導体チップ１１２を第１半導体チップ１１１と平面的にほぼ同等の大きさとすることで、従来の内部リード６が不要である多層基板１１０との相乗効果により、従来に比べて回路の高集積化、及び面積の縮小化を図ることができる。詳しく説明すると、第１半導体チップ１１１において、フリップチップ装着により第１半導体チップ１１１の第１電極１２９と多層基板１１０の第１パッド電極１２４とは電気的に接続される。一方、このような状態において第２半導体チップ１１２における電気的接続を図るためには、金属線１３７を介して第２電極１３６に電気的接続される多層基板１１０の第２パッド電極１２５は、第１半導体チップ１１１の占有領域の周縁部に配置することになる。このような状態において面積の縮小化を図るために、第２パッド電極１２５が形成されている多層基板１１０の側面１２２に対向する側面１２３に第３パッド電極１２６を形成し、多層基板１１０内に形成したビア１２７により上記第２パッド電極１２５と上記第３パッド電極１２６の一部とを電気的に接続した。このように構成することで、図１３に示すように内部リード６を設ける必要がなくなり、半導体装置全体の面積の縮小化を図ることができる。上述のように、第１半導体チップ１１１の第１電極非形成面１３４と第２半導体チップ１１２の第２電極非形成面１３８とを対向させ、第２電極１３６と上記第２パッド電極１２５とを金属線１３７にて電気的接続を図ったことから、第１半導体チップ１１１と同等の大きさにてなる第２半導体チップ１１２を使用することができ、回路の高集積化を図ることができる。
【００１１】
図９を参照した上述の説明では、多層基板１１０に第１半導体チップ１１１をフリップチップ装着した後に、該第１半導体チップ１１１上に第２半導体チップ１１２を固定したが、この工程順に限定されるものではない。即ち、まず、第１半導体チップ１１１の第１電極非形成面１３４と、第２半導体チップ１１２の第２電極非形成面１３８とを接着剤１３９にて接着した後、第１半導体チップ１１１を多層基板１１０にフリップチップ装着してもよい。
【００１２】
上述の半導体装置１０１は、第１半導体チップ１１１及び第２半導体チップ１１２がともに一つのチップから構成される場合であるが、これに限定されるものではない。即ち、図３に示す半導体装置１０２のように上記第１半導体チップを複数のチップ１５１，１５２にて構成することもできる。この場合、チップ１５１の厚み寸法ｔ１と、チップ１５２の厚み寸法ｔ２とを同寸法とすることで、これらのチップ１５１，１５２上に上記第２半導体チップ１１２を載置することができ、かつ該第２半導体チップ１１２は、個々のチップ１５１，１５２における大きさよりも大きいものを使用することができる。
【００１３】
又、上記半導体装置１０２の場合、多層基板１１０にフリップチップ装着された例えば２つのチップ１５１及びチップ１５２について、上述のように第１封止材１３３にて上記隙間の封止が行われるが、図１０に示すように２つのチップ１５１，１５２に挟まれた部分１５３に注入される第１封止材１３３によって、積み重ねられる上記第２半導体チップ１１２の固定をも行うこともできる。即ち、チップ１５１，１５２と第２半導体チップ１１２とを接着剤１３９を用いて接着するのではなく、第１封止材１３３に上記接着剤１３９の作用をも兼ねされる。このようにすることで、第１封止材１３３の硬化、並びに接着剤１３９の塗布及び硬化の工程を一度に済ますことができ、製造時間の短縮を図ることができる。
【００１４】
又、図４に示す半導体装置１０３のように、一つの第１半導体チップ１１１に対して上記第２半導体チップを複数の、例えば２つのチップ１５５，１５６にて構成してもよい。
さらに、上述の半導体装置１０２と半導体装置１０３とをミックスし、図５に示す半導体装置１０４のように、上記第１半導体チップ及び上記第２半導体チップの両方をそれぞれ複数のチップにて構成してもよい。
【００１５】
又、図６に示すような半導体装置１０５を構成することもできる。
半導体装置１０５は、上述の例えば半導体装置１０１において、多層基板１１０の側面１２２に形成されている第２パッド電極１２５と、それに隣接する第１パッド電極１２４との間に、図１１に詳しく示すような流出防止部１６０を設けている。流出防止部１６０は、例えばセラミック材にて形成したり、ガラス材をプリントして形成したり、シート材から形成したりする。上述のように第１半導体チップ１１１が多層基板１１０にフリップチップ装着された後、第１半導体チップ１１１の第１電極形成面１２８と多層基板１１０の側面１２２との間には第１封止材１３３が注入されるが、該第１封止材１３３が第２パッド電極１２５へ流れ出ないように、上記流出防止部１６０は、堰として作用し上記第１封止材１３３の流出を防止する。多層基板１１０の厚み方向に沿った流出防止部１６０の高さは、封止される第１半導体チップ１１１の大きさ、又は上記第１封止材１３３の使用量によって変動し、当然ながら第１封止材１３３が第２パッド電極１２５側へ溢れ出ないような高さ、例えば５０〜５００μｍの高さに設定される。
このような流出防止部１６０を設けることで、第１封止材１３３が流れる領域を規定することができることから、第２パッド電極１２５の設置位置に余裕を持たせる必要がなくなり、多層基板１１０の平面面積を縮小することができ、よって半導体装置全体の面積の縮小化を図ることができる。又、第１封止材１３３が第２パッド電極１２５に付着し金属線１３７の接続を阻害するという現象の発生を抑えることもできる。
尚、図１１では、多層基板１１０の長手方向に沿って第２パッド電極１２５が配列されていることから、流出防止部１６０も上記長手方向に沿って第２パッド電極１２５と第１パッド電極１２４との間に形成しているが、これに限定されるものではない。即ち、もし上記長手方向に直交方向に沿って、多層基板１１０に第２パッド電極１２５が形成されているときには、それに対応して、流出防止部１６０を形成する。よって、多層基板１１０上に方形状に流出防止部１６０が形成される場合もある。
【００１６】
又、流出防止部１６０は、上述のように多層基板１１０の側面１２２に突設されるタイプに限定されるものではない。即ち、図７に示すように、多層基板１６１の側面１２２に形成した第２パッド電極１２５と第１パッド電極１２４との間に、流出する第１封止材１３３を受け止める凹部にてなる流出防止部１６２を形成してもよい。尚、流出防止部１６２の深さは、封止される第１半導体チップ１１１の大きさ、又は上記第１封止材１３３の使用量によって変動し、当然ながら第１封止材１３３が第２パッド電極１２５側へ溢れ出ないような深さ、例えば５０〜２００μｍの深さに設定される。
【００１７】
さらに又、図８に示すような流出防止部１６３を設けることもできる。流出防止部１６３は、多層基板１１０の側面１２２に形成される上記第２パッド電極１２５における、上記多層基板１１０の厚み方向に沿った厚みを大きくしたものであり、上記第２パッド電極としての機能をも兼ねる。該流出防止部１６３の厚みは、封止される第１半導体チップ１１１の大きさ、又は上記第１封止材１３３の使用量によって変動し、当然ながら第１封止材１３３が第２パッド電極１２５側へ溢れ出ないような高さ、例えば５０〜５００μｍの高さに設定される。
【００１８】
尚、図７及び図８では、流出防止部１６３に主に関係する部分を図示しているので、第２封止材１４０等の図示は省略している。
又、上述した流出防止部１６０，１６２，１６３のいずれかを、図３から図５に示す半導体装置１０２〜１０４に適用することももちろん可能である。
【００１９】
又、上述の実施形態では、第１半導体チップ１１１の第１電極１２９と、多層基板１１０の第１パッド電極１２４とはバンプ１３０及びペースト１３１を介して電気的接続を図っているが、これに限定されるものではない。例えば、金属粒を含む導電性ペーストを例えば上記第１電極１２９に塗布した後、第１電極１２９と第１パッド電極１２４とを圧接し上記金属粒を潰すことで第１電極１２９と第１パッド電極との導通を図っても良い。
【００２０】
【発明の効果】
以上詳述したように本発明の第１態様の半導体装置、及び第２態様の半導体装置の製造方法によれば、多層基板と、第１半導体チップと、第２半導体チップとを備える。上記多層基板は、対向する一方の側面に上記第１半導体チップがフリップチップ装着される第１パッド電極及び上記第２半導体チップの第２電極と電気的に接続される第２パッド電極を有し、他方の側面に上記第１パッド電極及び上記第２パッド電極と電気的に接続される第３パッド電極を有する。よって、例えば上記多層基板の厚み方向に直交する平面方向に延在する、従来の内部リードは不要となり、半導体装置全体の面積を縮小することができる。さらに又、上記第１半導体チップと上記第２半導体チップとは同等の平面面積を有し、上記第１半導体チップ上に上記第２半導体チップを載置する。このように構成することで、当該半導体装置における回路の集積化を向上させることができる。
【図面の簡単な説明】
【図１】 本発明の実施形態における半導体装置の断面図である。
【図２】 図１に示す多層基板、及び該多層基板と第１半導体チップとの装着部分の拡大図である。
【図３】 図１に示す半導体装置の他の実施形態における断面図である。
【図４】 図１に示す半導体装置の別の実施形態における断面図である。
【図５】 図１に示す半導体装置のさらに他の実施形態における断面図である。
【図６】 図１に示す半導体装置のさらに別の実施形態における断面図である。
【図７】 図５に示す流出防止部の他の実施形態を示す図である。
【図８】 図５に示す流出防止部の別の実施形態を示す図である。
【図９】 図１に示す半導体装置の製造方法を説明するための斜視図である。
【図１０】 図３に示す半導体装置における第１半導体チップ部分の封止を行うときの状態を示す斜視図である。
【図１１】 図６に示す流出防止部を示す斜視図である。
【図１２】 図１に示す半導体装置の変形例における断面図である。
【図１３】 従来の半導体装置を示す断面図である。
【符号の説明】
１０１，１０２，１０３，１０４，１０５…半導体装置、
１１０…多層基板、１１１…第１半導体チップ、
１１２…第２半導体チップ、１２１…板材、１２２，１２３…側面、
１２４…第１パッド電極、１２５…第２パッド電極、
１２６…第３パッド電極、１２８…第１電極形成面、１２９…第１電極、
１３３…第１封止材、１３４…第１電極非形成面、
１３５…第２電極形成面、１３６…第２電極、１３７…金属線、
１３８…第２電極非形成面、１３９…接着剤、１４０…第２封止材、
１５１，１５２，１５５，１５６…チップ、
１６０，１６２，１６３…流出防止部。

Claims (4)

  1. 互いに隙間を介して並設される複数の第１半導体チップであって、それぞれの第１電極形成面に第１電極を有し該第１電極がフリップチップ装着される第１半導体チップと、
    複数の上記第１半導体チップに対応して設けられる一つの第２半導体チップであって、複数の上記第１半導体チップとほぼ同等の面積を占め、かつ複数の上記第１半導体チップの上記第１電極形成面に対向する第１電極非形成面のほぼ全面に対向して配置される第２電極非形成面を有する第２半導体チップと、
    対向する２つの側面の一方には上記第１半導体チップの上記第１電極がフリップチップ装着される第１パッド電極、及び上記第２電極非形成面に対向する上記第２半導体チップの第２電極形成面に形成されている第２電極と金属線を介して接続される第２パッド電極を有し、他方には第３パッド電極を有し上記第１及び第２パッド電極と上記第３パッド電極とを電気的に接続した基板と、
    上記第１パッド電極と上記第２パッド電極との間、及び互いに隣接する上記第１半導体チップ間における上記隙間に注入され、上記基板に装着された上記第１半導体チップの封止を行うとともに、上記第１半導体チップの上記第１電極非形成面と上記第２半導体チップの上記第２電極非形成面とを固定する第１封止材と、
    を備えたことを特徴とする半導体装置。
  2. 上記基板において、上記第２パッド電極は該基板の上記一方の側面の周縁部分に配置され上記第１パッド電極はその内側に配置されるとき、上記第１パッド電極と上記第２パッド電極との間に設けられ上記基板に装着された上記第１半導体チップの封止を行う第１封止材が上記第２パッド電極へ流出するのを防止する凹状の流出防止部を有する、請求項１記載の半導体装置。
  3. 上記基板の上記一方の側面は第２封止材にて封止される、請求項１又は２記載の半導体装置。
  4. 上記第２半導体チップはペルチエ素子を構成する、請求項１から３のいずれかに記載の半導体装置。
JP06004098A 1998-03-11 1998-03-11 半導体装置 Expired - Fee Related JP3891678B2 (ja)

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