JP2004207760A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2004207760A JP2004207760A JP2004115273A JP2004115273A JP2004207760A JP 2004207760 A JP2004207760 A JP 2004207760A JP 2004115273 A JP2004115273 A JP 2004115273A JP 2004115273 A JP2004115273 A JP 2004115273A JP 2004207760 A JP2004207760 A JP 2004207760A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- lsi
- lsi chip
- electrode
- flip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Abstract
【解決手段】 配線基板5にフリップチップ接続されたLSIチップ1に形成された突起電極3と、LSIチップ8に形成された電極4とを鉛直方向において異なる位置に配置することにより、電極4におけるワイヤボンド時の機械的ダメージがフリップチップ接続部に伝播することを抑制し、フリップチップ接続部の接続信頼性を確保する。
【選択図】 図1
Description
2 LSIチップ
3,3a,3b 突起電極
4 電極
5 配線基板
6 金属細線
7 直線
8 LSIチップ
9 LSIチップ
10 LSIチップ
11 LSIチップ
12 LSIチップ
13 LSIチップ
Claims (5)
- 複数の第1のLSIチップと配線基板とが突起電極を介してフリップチップ接続され、前記複数の第1のLSIチップの回路形成されていない面と第2のLSIチップの回路形成されていない面とが接着され、前記第2のLSIチップに形成された電極と前記配線基板に形成された配線とが金属細線で電気的に接続されたことを特徴とする半導体装置。
- 複数の第1のLSIチップに対向する配線基板の表面を水平面として、前記突起電極と前記第2のLSIチップに形成された電極とが鉛直方向において異なる位置にあることを特徴とする請求項1に記載の半導体装置。
- 導電性接着剤を用いたフリップチップ接続であることを特徴とする請求項1に記載の半導体装置。
- 低融点金属を用いたフリップチップ接続であることを特徴とする請求項1に記載の半導体装置。
- 突起電極と配線基板に形成された配線とが直接接続するフリップチップ接続であることを特徴とする請求項1に記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004115273A JP2004207760A (ja) | 2004-04-09 | 2004-04-09 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004115273A JP2004207760A (ja) | 2004-04-09 | 2004-04-09 | 半導体装置 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2002163925A Division JP3558070B2 (ja) | 2002-06-05 | 2002-06-05 | 半導体装置およびその製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2004207760A true JP2004207760A (ja) | 2004-07-22 |
Family
ID=32822384
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004115273A Pending JP2004207760A (ja) | 2004-04-09 | 2004-04-09 | 半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2004207760A (ja) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11261044A (ja) * | 1998-03-11 | 1999-09-24 | Matsushita Electric Ind Co Ltd | 固体撮像素子付半導体装置及び該半導体装置の製造方法 |
JPH11260851A (ja) * | 1998-03-11 | 1999-09-24 | Matsushita Electric Ind Co Ltd | 半導体装置及び該半導体装置の製造方法 |
JP2001044358A (ja) * | 1999-07-28 | 2001-02-16 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
-
2004
- 2004-04-09 JP JP2004115273A patent/JP2004207760A/ja active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11261044A (ja) * | 1998-03-11 | 1999-09-24 | Matsushita Electric Ind Co Ltd | 固体撮像素子付半導体装置及び該半導体装置の製造方法 |
JPH11260851A (ja) * | 1998-03-11 | 1999-09-24 | Matsushita Electric Ind Co Ltd | 半導体装置及び該半導体装置の製造方法 |
JP2001044358A (ja) * | 1999-07-28 | 2001-02-16 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
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