CN112928035A - 具有电磁屏蔽功能的板级倒装芯片封装结构及其制备方法 - Google Patents
具有电磁屏蔽功能的板级倒装芯片封装结构及其制备方法 Download PDFInfo
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- CN112928035A CN112928035A CN202110126376.7A CN202110126376A CN112928035A CN 112928035 A CN112928035 A CN 112928035A CN 202110126376 A CN202110126376 A CN 202110126376A CN 112928035 A CN112928035 A CN 112928035A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0233—Structure of the redistribution layers
- H01L2224/02331—Multilayer structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0233—Structure of the redistribution layers
- H01L2224/02333—Structure of the redistribution layers being a bump
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02379—Fan-out arrangement
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
Claims (10)
Priority Applications (1)
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CN202110126376.7A CN112928035B (zh) | 2021-01-29 | 2021-01-29 | 具有电磁屏蔽功能的板级倒装芯片封装结构及其制备方法 |
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CN202110126376.7A CN112928035B (zh) | 2021-01-29 | 2021-01-29 | 具有电磁屏蔽功能的板级倒装芯片封装结构及其制备方法 |
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CN112928035A true CN112928035A (zh) | 2021-06-08 |
CN112928035B CN112928035B (zh) | 2023-11-17 |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113299569A (zh) * | 2021-06-11 | 2021-08-24 | 广东佛智芯微电子技术研究有限公司 | 大板级扇出基板倒装芯片封装结构的制备方法 |
WO2023093854A1 (zh) * | 2021-11-25 | 2023-06-01 | 青岛歌尔微电子研究院有限公司 | 电子封装结构、电子封装结构的制作方法以及电子设备 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002151371A (ja) * | 2000-11-16 | 2002-05-24 | Sony Corp | チップ状電子部品の製造に用いる疑似ウエーハおよびその製造方法ならびにチップ状電子部品の製造方法 |
US20090243069A1 (en) * | 2008-03-26 | 2009-10-01 | Zigmund Ramirez Camacho | Integrated circuit package system with redistribution |
CN103327741A (zh) * | 2013-07-04 | 2013-09-25 | 江俊逢 | 一种基于3d打印的封装基板及其制造方法 |
US20150279789A1 (en) * | 2014-03-28 | 2015-10-01 | Ravindranath V. Mahajan | Electromagnetic interference shield for semiconductor chip packages |
CN107777889A (zh) * | 2017-11-01 | 2018-03-09 | 信利(惠州)智能显示有限公司 | 玻璃料、显示装置和显示屏 |
US20190013302A1 (en) * | 2017-07-07 | 2019-01-10 | China Wafer Level Csp Co., Ltd. | Packaging method and package structure for fingerprint recognition chip and drive chip |
US20190333880A1 (en) * | 2017-10-25 | 2019-10-31 | Sj Semiconductor(Jiangyin) Corporation | Fan-out antenna packaging structure and preparation method thereof |
-
2021
- 2021-01-29 CN CN202110126376.7A patent/CN112928035B/zh active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002151371A (ja) * | 2000-11-16 | 2002-05-24 | Sony Corp | チップ状電子部品の製造に用いる疑似ウエーハおよびその製造方法ならびにチップ状電子部品の製造方法 |
US20090243069A1 (en) * | 2008-03-26 | 2009-10-01 | Zigmund Ramirez Camacho | Integrated circuit package system with redistribution |
CN103327741A (zh) * | 2013-07-04 | 2013-09-25 | 江俊逢 | 一种基于3d打印的封装基板及其制造方法 |
US20150279789A1 (en) * | 2014-03-28 | 2015-10-01 | Ravindranath V. Mahajan | Electromagnetic interference shield for semiconductor chip packages |
US20190013302A1 (en) * | 2017-07-07 | 2019-01-10 | China Wafer Level Csp Co., Ltd. | Packaging method and package structure for fingerprint recognition chip and drive chip |
US20190333880A1 (en) * | 2017-10-25 | 2019-10-31 | Sj Semiconductor(Jiangyin) Corporation | Fan-out antenna packaging structure and preparation method thereof |
CN107777889A (zh) * | 2017-11-01 | 2018-03-09 | 信利(惠州)智能显示有限公司 | 玻璃料、显示装置和显示屏 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113299569A (zh) * | 2021-06-11 | 2021-08-24 | 广东佛智芯微电子技术研究有限公司 | 大板级扇出基板倒装芯片封装结构的制备方法 |
WO2023093854A1 (zh) * | 2021-11-25 | 2023-06-01 | 青岛歌尔微电子研究院有限公司 | 电子封装结构、电子封装结构的制作方法以及电子设备 |
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Effective date of registration: 20230413 Address after: Room A107, scientific research building, block a, neifo high tech think tank center, Nanhai Software Science Park, Shishan town, Nanhai District, Foshan City, Guangdong Province, 528225 Applicant after: Guangdong fozhixin microelectronics technology research Co.,Ltd. Address before: Room A107, scientific research building, block a, neifo high tech think tank center, Nanhai Software Science Park, Shishan town, Nanhai District, Foshan City, Guangdong Province, 528225 Applicant before: Guangdong fozhixin microelectronics technology research Co.,Ltd. Applicant before: Guangdong Xinhua Microelectronics Technology Co.,Ltd. |
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