WO2023093854A1 - 电子封装结构、电子封装结构的制作方法以及电子设备 - Google Patents

电子封装结构、电子封装结构的制作方法以及电子设备 Download PDF

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WO2023093854A1
WO2023093854A1 PCT/CN2022/134373 CN2022134373W WO2023093854A1 WO 2023093854 A1 WO2023093854 A1 WO 2023093854A1 CN 2022134373 W CN2022134373 W CN 2022134373W WO 2023093854 A1 WO2023093854 A1 WO 2023093854A1
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Prior art keywords
electrical connection
substrate
layer
connection part
electronic
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PCT/CN2022/134373
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English (en)
French (fr)
Inventor
张锡光
刘家政
刘文科
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Qingdao Goertek Microelectronics Research Institute Co Ltd
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Qingdao Goertek Microelectronics Research Institute Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W95/00—Packaging processes not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires

Definitions

  • the embodiments of the present application relate to the technical field of chip packaging, and more specifically, the present application relates to an electronic packaging structure, a method for manufacturing the electronic packaging structure, and electronic equipment.
  • RDL redistribution layer
  • SIP packaging System In a Package
  • functional chips such as processors, memory and other functional chips
  • the SIP package structure has been widely used in various types of electronic products.
  • the main solution is a combination of ball in mold and laser ablation.
  • the existing solution needs to first electrically connect the functional chips on the PCB, and then add the ball planting process (that is, the SBM process), and then grind and thin the packaging layer on the PCB to expose the solder balls.
  • the multi-channel process is also time-consuming.
  • the present application aims to solve at least one of the technical problems existing in the prior art, and proposes an electronic packaging structure, a manufacturing method of the electronic packaging structure, and electronic equipment.
  • the first embodiment of the present application provides an electronic packaging structure, including:
  • a functional chip the functional chip is arranged on the substrate and is electrically connected to the substrate;
  • the encapsulation layer is formed on the substrate and covers the functional chip, and wiring grooves are opened on the encapsulation layer;
  • the rewiring layer includes a cover layer and a first electrical connection part, and the substrate and/or the functional chip and the first electrical connection part are electrically connected by wire bonding in the wiring trench connection, the covering layer is filled in the wiring trench, and the first electrical connection part is exposed on the surface of the covering layer.
  • the rewiring layer further includes a second electrical connection portion, the second electrical connection portion is disposed in the wiring trench and embedded in the covering layer;
  • the second electrical connection part is electrically connected between the substrate and the first electrical connection part by wire bonding, or is electrically connected between the functional chip and the first electrical connection part.
  • a stepped structure is formed inside the wiring trench, and the stepped structure includes a first stepped layer and a second stepped layer located below the first stepped layer;
  • the second electrical connection part is disposed on the second stepped layer
  • the first electrical connection portion is disposed on the first stepped layer.
  • the second electrical connection part is a transfer pad.
  • the first electrical connection part is an input/output pad.
  • the surface of the cover layer is flush with the surface of the encapsulation layer.
  • the encapsulation layer is made of the same material as the covering layer.
  • the functional chips are high-frequency chips.
  • the wiring groove is formed by laser.
  • a scheme for electrical connection with external circuits is provided for the electronic packaging structure, and the electrical connection part is drawn out to the surface of the electronic packaging structure by wire bonding, and then the position of the lead is fixed through the packaging process A rewiring layer is formed, which can better realize the rewiring of each functional chip and the like in the electronic packaging process.
  • the solution provided by the embodiment of the present application can realize multi-layer lead distribution, and can also simplify the manufacturing process of the chip package, and reduce the manufacturing time and cost.
  • the second embodiment of the present application provides a method for manufacturing an electronic packaging structure.
  • the manufacturing method of the electronic packaging structure includes:
  • the step of performing secondary wire bonding in the wiring trench further includes:
  • a second electrical connection part into the wiring groove, electrically connect the second electrical connection part to at least one of the substrate and the functional chip by wire bonding, and then connect the second electrical connection part to at least one of the substrate and the functional chip.
  • the second electrical connection part is electrically connected to the first electrical connection part by wire bonding.
  • the third embodiment of the present application provides an electronic device.
  • the electronic device includes: the above-mentioned electronic packaging structure.
  • FIG. 1-FIG. 5 are flow charts of a manufacturing method of a SIP encapsulation structure according to an embodiment of the present application.
  • Embodiments of the present application provide an electronic packaging structure, a manufacturing method of the electronic packaging structure, and electronic equipment.
  • an electronic packaging structure is provided.
  • the electronic package structure is, for example, a SIP package.
  • the SIP package structure may be a system-in-package well known in the field of electronic equipment.
  • packages of communication chips such as WiFi and Bluetooth.
  • WiFi and Bluetooth are also be other types of functional chips, which will not be listed in detail in this application.
  • the electronic packaging structure provided by the embodiments of the present application can be applied to various types of electronic devices.
  • the electronic device may be, for example, earphones, microphones, speakers, stereos, televisions, smart phones, etc., which will not be listed in detail in this application.
  • 1 to 5 show schematic diagrams of the manufacturing process of the electronic packaging structure provided by the embodiment of the present application.
  • 5 shows a specific structural form of the manufactured electronic package structure, and the electronic package structure provided in the embodiment of the present application is not limited to this structural form.
  • the electronic packaging structure provided by the embodiment of the present application, as shown in Figures 1 to 5, includes: a substrate 1, a functional chip 2, a packaging layer 3 and a rewiring layer;
  • the functional chip 2 is arranged on the substrate 1 and is electrically connected to the substrate 1;
  • the encapsulation layer 3 is formed on the substrate 1 and covers the functional chip 2, and a wiring groove 4 is opened on the encapsulation layer 3;
  • the rewiring layer includes a cover layer 5 and a first electrical connection portion 6, and the substrate 1 and/or the functional chip 2 are connected to the first electrical connection portion by wire bonding in the wiring trench 4 6, the covering layer 5 is filled in the wiring trench 4, and the first electrical connection portion 6 is exposed on the surface of the covering layer 5.
  • the first electrical connection part 6 is drawn out by wire bonding, and the first electrical connection part 6 can be used to establish electrical connections with external circuits or electrical signals. connection relationship. That is to say, the first electrical connection portion 6 led out by wire bonding may be equivalent to an electrical connection element for electrically connecting the entire electronic package structure with an external circuit. In this way, the electronic packaging structure can be conveniently electrically connected to an external circuit through the first electrical connection portion 6.
  • the embodiment of the present application provides a scheme for electrical connection with the external circuit for the electronic packaging structure, wherein the electrical connection part for external connection is drawn out by wire bonding, so as to replace the traditional ball planting (Ball in mold+Laser ablation ) scheme.
  • the process in the embodiment of the present application is relatively simple.
  • the first electrical connection portion 6 is drawn to the surface of the electronic packaging structure by using a wire bonding process, and then the position of the wire is fixed by using a packaging process (ie, molding), This forms a rewiring layer, which can better realize the rewiring of each functional chip in the packaging process.
  • a packaging process ie, molding
  • the substrate 1 is, for example, a printed circuit board PCB.
  • the substrate 1 is a support for the functional chip 2 and also a carrier for the electrical connection of the functional chip 2 .
  • the functional chip 2 is, for example, a high-frequency chip.
  • the functional chip 2 is, for example, an RF radio frequency chip, a GPS positioning chip, a DRAM memory chip, a Bluetooth chip, and the like. Moreover, the functional chip 2 is electrically connected to the substrate 1 by, for example, metal wire bonding.
  • the functional chip 2 includes, but is not limited to, the above-mentioned high-frequency chips. That is to say, the functional chip 2 can also be other types of chips, and those skilled in the art can flexibly set the type of the functional chip 2 according to needs, and this application does not make specific limitations here.
  • the encapsulation layer 3 can be formed on the substrate 1 using materials and processes well known to those skilled in the art, so as to encapsulate each of the functional chips 2 on the substrate 1 .
  • the material of the encapsulation layer 3 includes, but is not limited to, polymer materials such as injection-molded plastics and the like.
  • the first electrical connection part 6 can be used as an integral input terminal/output terminal of the electronic package structure to provide transmission of power, signal, ground and the like.
  • wiring trenches 4 are opened on the packaging layer 3 .
  • the wiring groove 4 is located at the wire bonding position of the functional chip 2 and the substrate 1 . That is to say, the wiring groove 4 is opened at the position where the leads electrically connected between the functional chip 2 and the substrate 1 are located for rewiring. Afterwards, a second wire bonding (Second Wire Bonding) process is performed in the wiring trench 4 to realize multi-layer wire distribution. It can be seen that the purpose of opening the wiring trench 4 on the packaging layer 3 is to provide a basis for subsequent rewiring.
  • the wires electrically connected between the functional chip 2 and the substrate 1 can be broken first, and then the wires are bonded to the The first electrical connection part 6 .
  • the first electrical connection portion 6 is not disposed inside the wiring trench 4 .
  • the wiring trench 4 should be filled with encapsulation material to form the covering layer 5 .
  • the covering layer 5 can fix the position of each lead wire.
  • the covering layer 5 is equivalent to performing secondary encapsulation.
  • the rewiring layer further includes a second electrical connection part 7, the second electrical connection part 7 is disposed in the wiring trench 4, and embedded into the cover layer 5; the second electrical connection part 7 is electrically connected between the substrate 1 and the first electrical connection part 6 by wire bonding, or is electrically connected to the functional chip 2 and the first electrical connection part 6 .
  • the second electrical connection part 7 is also introduced during the process of forming the rewiring layer.
  • the process involved is: first electrically connect at least one of the functional chip 2 and the substrate 1 to the introduced second electrical connection part 7 by wire bonding, and then connect the first
  • the second electrical connection portion 7 is electrically connected to the first electrical connection portion 6 by wire bonding, and then the wiring groove 4 is filled with a packaging material, that is, a secondary packaging process is performed to form the Overlay 5.
  • a packaging material that is, a secondary packaging process is performed to form the Overlay 5.
  • the second electrical connection part 7 is embedded in the covering layer 5 , while the first electrical connecting part 6 is exposed on the surface of the covering layer 5 .
  • the interior of the wiring trench 4 forms a ladder-like structure, and the ladder-like structure includes a first ladder layer and a layer below the first ladder layer.
  • the wiring trench 4 may be formed by means of laser.
  • the wiring trench 4 is formed by using a Laser trench process. That is to say, the wiring trench 4 can be formed on the encapsulation layer 3 by eg laser perforation technology. It should be noted that the wiring trench 4 does not penetrate through the encapsulation layer 3 .
  • the wiring trench 4 is, for example, arranged in a direction perpendicular to the substrate 1 .
  • the formation of the wiring groove 4 by means of laser has the advantages of fast speed, and the inner wall surface of the formed wiring groove is flat and free of burrs.
  • the second electrical connection part 7 is a transfer pad.
  • the second electrical connection part 7 is used as an electrical adapter.
  • the first electrical connection portion 6 can be led out to the surface of the cover layer 5 by means of the second electrical connection portion 7 .
  • the first electrical connection part 6 is an input/output pad.
  • the first electrical connection portion 6 serves as an I/O terminal of the electronic package structure.
  • the second electrical connection portion 7 can lead out the first electrical connection portion 6 to a side away from the substrate 1 through wires/welding wires in a wire bonding manner.
  • the first electrical connection part 6 is used as an input/output terminal (I/O terminal) of the entire electronic package structure, and the second electrical connection part 7 is used as an electrical adapter.
  • first electrical connection part 6 and the second electrical connection part 7 may be a pad, or may be a conductive sheet (such as a metal sheet, etc.), and those skilled in the art may The specific situation can be flexibly adjusted, and this application does not make specific restrictions on it.
  • the surface of the cover layer 5 is flush with the surface of the encapsulation layer 3 .
  • the formed electronic packaging structure has a good appearance and is easy to assemble.
  • the encapsulation layer 3 is made of the same material as the covering layer 5 .
  • the covering layer 5 includes, but is not limited to, polymer materials such as injection-molded plastics.
  • the material of the covering layer 5 may also be different from that of the encapsulation layer 3 .
  • Those skilled in the art can make adjustments according to specific conditions, and this application does not make specific limitations here.
  • one or more functional chips 2 are provided.
  • the functional chip 2 is a high-frequency chip. That is to say, each of the functional chips 2 arranged on the substrate 1 may be a high-frequency chip.
  • the functional chip 2 may be an RF radio frequency chip, a GPS positioning chip, a DRAM memory chip, a Bluetooth chip, and the like.
  • the functional chip 2 includes, but is not limited to, the high-frequency chip of the above-mentioned type.
  • a method for manufacturing an electronic packaging structure is provided, which can be used for manufacturing the above-mentioned electronic packaging structure.
  • 1 to 5 show the flow of the manufacturing method of the electronic packaging structure.
  • Step S1 as shown in FIG. 1 , a substrate 1 is provided, a functional chip 2 is arranged on the substrate 1 , and the functional chip 2 is electrically connected to the substrate 1 by wire bonding.
  • the step 1 is a wire bonding process, the purpose of which is to electrically connect the functional chip 2 to the substrate 1 .
  • a welding pad is provided on the functional chip 2, and a welding pad is also provided on the substrate 1, and the two welding pads can be electrically connected through leads/bonding wires, Thus, the electrical conduction between the functional chip 2 and the substrate 1 is realized.
  • Step S2 as shown in FIG. 2 , forming an encapsulation layer 3 covering the functional chip 2 on the substrate 1 .
  • the step 2 is a packaging process (ie molding).
  • the encapsulation layer 3 can be used to encapsulate the functional chip 2 on the substrate 1 and can protect the functional chip 2 . Moreover, after the packaging process (molding), the position of the leads between the functional chip 2 and the substrate 1 can also be fixed.
  • Step 3 remove part of the encapsulation layer 3 at the position where the functional chip 2 is wire-bonded with the substrate 1 to form a wiring trench 4, and disconnect the functional chip 2 from the substrate 1. lead wires for electrical connection between the substrates 1 .
  • step 3 slots are made at the positions where the leads electrically connected between the functional chip 2 and the substrate 1 are located.
  • the design of the wiring trench 4 provides a basis for subsequent rewiring.
  • Step 4 electrically connect the substrate 1 and/or the functional chip 2 to the first electrical connection part 6 in the wiring trench 4 by means of secondary wire bonding .
  • the wire bonding process is continued after the formation of the wiring trench 4 , which facilitates subsequent implementation of multi-layer wire distribution. That is, the step 4 can actually be regarded as a second wire bonding process (Second Wire Bonding).
  • Step 5 filling the packaging material in the wiring trench 4 to form a covering layer 5 covering the leads, and exposing the first electrical connection portion 6 on the surface of the covering layer 5 , to form a redistribution layer.
  • the first electrical connection portion 6 is, for example, equivalent to an I/O terminal of the entire electronic packaging structure, which can be used for electrical connection with an external circuit.
  • the encapsulation material can be used to wrap the lead wires/welding wires etc. connected to the first electrical connection part 6 , so as to form the rewiring layer.
  • wire bonding is used to lead out the first electrical connection part 6, and the first electrical connection part 6 is far away from the substrate 1 and exposed on the surface of the electronic packaging structure, wherein The lead position is also fixed through the secondary packaging process, which can realize multi-layer lead distribution.
  • the solution provided by the embodiment of the present application can save the manufacturing cost of forming the rewiring layer in the chip package, and can simplify the manufacturing process of the chip package.
  • the traditional redistribution layer (RDL) solution in order to minimize the I/O terminal density of the package structure, often uses a variety of sputtering and deposition methods, which are usually completed in the fab, and the equipment cost is high.
  • the solution of the present application can directly complete the rewiring layer solution by using low-cost WB equipment, which overcomes the defects of the traditional technology.
  • the wiring trench 4 may be formed by means of laser. That is, the Laser trench process is adopted.
  • the wiring trench 4 can be formed on the encapsulation layer 3 by eg laser perforation technology.
  • the wiring trench 4 does not penetrate through the encapsulation layer 3 .
  • the wiring trenches 4 are, for example, arranged in a direction perpendicular to the substrate 1 .
  • the formation of grooves by means of laser has the advantages of fast speed, and the inner wall surface of the formed grooves is flat and free of burrs.
  • the step of performing secondary wire bonding in the wiring trench further includes the following steps:
  • a second electrical connection part 7 is introduced into the wiring groove 4, and the second electrical connection part 7 is connected to the substrate 1 and the functional chip by wire bonding. 2 is electrically connected, and then the second electrical connection part 7 is electrically connected to the first electrical connection part 6 by wire bonding.
  • the first electrical connection part 6 when the first electrical connection part 6 is drawn out by wire bonding, the first electrical connection part 6 can also be drawn out to the on the surface of layer 5.
  • the second electrical connection part 7 is configured as a transfer pad, and is connected with a lead wire/bonding wire; the first electrical connection part 6 is configured as an input/output pad, which serves as an I/O terminal.
  • the surface of the finally formed rewiring layer should be flush with the surface of the previously formed encapsulation layer 3 . In this way, the appearance of several electronic packages is better.
  • an electronic device is also provided.
  • the electronic device includes the electronic packaging structure described in any one of the above.
  • the electronic device is, for example, a smart phone, a tablet computer, a wearable device, etc., which is not limited in this application.
  • references to the terms “one embodiment,” “some embodiments,” “exemplary embodiments,” “example,” “specific examples,” or “some examples” are intended to mean that the implementation A specific feature, structure, material, or characteristic described by an embodiment or example is included in at least one embodiment or example of the present application.
  • schematic representations of the above terms do not necessarily refer to the same embodiment or example.

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

本申请实施例提供了一种电子封装结构、电子封装结构的制作方法以及电子设备；其中，所述电子封装结构包括：基板，功能芯片，封装层以及重新布线层；所述功能芯片设置在所述基板上，并与所述基板电连接；所述封装层形成在所述基板上，并覆盖所述功能芯片，所述封装层上开设有布线沟槽；所述重新布线层包括覆盖层和第一电连接部，在所述布线沟槽内通过引线键合将所述基板和/或所述功能芯片与所述第一电连接部电连接，所述覆盖层填充在所述布线沟槽内，所述第一电连接部外露于所述覆盖层的表面。本申请实施例为电子封装结构提供了一种能与外部电路进行电连接的方案，采用引线键合工艺直接引出电连接部至封装结构的外表面，具有工艺简单的特点。图5为摘要附图。

Description

电子封装结构、电子封装结构的制作方法以及电子设备
本申请要求于2021年11月25日提交中国专利局，申请号为202111418202.4，申请名称为“电子封装结构、电子封装结构的制作方法以及电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及芯片的封装技术领域，更具体地，本申请涉及一种电子封装结构、电子封装结构的制作方法以及电子设备。
背景技术
随着电子科技的快速发展，各种电子产品层出不穷，电子产品的功能越来越多，对于芯片尺寸的要求也越来越高。在一些高性能芯片的封装制程中通常涉及采用重新布线技术形成重新布线层(redistribution layer，RDL)，以调整组件的输出、输入位置。
SIP封装(System In a Package系统级封装)是将多种功能芯片，例如包括处理器、存储器等功能芯片集成在一个封装体内，从而实现一个基本完整的功能。近年来，SIP封装结构被广泛应用于各种类型的电子产品中。在相关的技术中，SIP封装结构在与外部电路进行电连接时，主要的方案为植球(Ball in mold)与激光烧烛(Laser ablation)相结合。现有的方案需要在PCB板上先电连接功能芯片，再增加植球制程(即SBM制程)，后续还要对PCB板上的封装层进行研磨减薄以露出锡球。多道工艺除了步骤繁琐之外，耗时也较长。
因此，有必要提供一种改进的电子封装结构，至少解决上述问题。
发明内容
本申请旨在至少解决现有技术中存在的技术问题之一，提出一种电子封装结构、电子封装结构的制作方法以及电子设备。
本申请第一实施例提供一种电子封装结构，包括：
基板；
功能芯片，所述功能芯片设置在所述基板上，并与所述基板电连接；
封装层，所述封装层形成在所述基板上，并覆盖所述功能芯片，所述封装层上开设有布线沟槽；以及
重新布线层，所述重新布线层包括覆盖层和第一电连接部，在所述布线沟槽内通过引线键合将所述基板和/或所述功能芯片与所述第一电连接部电连接，所述覆盖层填充在所述布线沟槽内，所述第一电连接部外露于所述覆盖层的表面。
在一实施例中，所述重新布线层还包括第二电连接部，所述第二电连接部设置于所述布线沟槽内，并嵌入至所述覆盖层之中；
所述第二电连接部通过引线键合电连接在所述基板与所述第一电连接部之间，或电连接在所述功能芯片与所述第一电连接部之间。
在一实施例中，所述布线沟槽的内部形成阶梯状结构，所述阶梯状结构包括第一阶梯层和位于所述第一阶梯层下方的第二阶梯层；
所述第二电连接部设置于所述第二阶梯层上；
所述第一电连接部设置于所述第一阶梯层上。
在一实施例中，所述第二电连接部为转接焊盘。
在一实施例中，所述第一电连接部为输入/输出焊盘。
在一实施例中，所述覆盖层的表面与所述封装层的表面相齐平。
在一实施例中，所述封装层与所述覆盖层的材质相同。
在一实施例中，所述功能芯片设置为一个或者多个，且所述功能芯片为高频芯片。
在一实施例中，通过镭射的方式形成所述布线沟槽。
本申请的实施例中，为电子封装结构提供了一种与外部电路进行电连接的方案，通过采用引线键合的方式引出电连接部至电子封装结构的表面上，再通过封装工艺固定引线位置形成了重新布线层，其能更好地实现电子封装制程中各功能芯片等的重新布线。本申请实施例提供的方案可实现多层引线分布，还可以简化芯片封装的制造流程，及减少制造时间和制造费用。
本申请第二实施例提供了一种电子封装结构的制作方法。所述电子封装结构的制作方法包括：
提供基板，将功能芯片排布在所述基板上，并通过引线键合的方式将所述功能芯 片与所述基板电连接；
在所述基板上形成覆盖所述功能芯片的封装层；
在所述功能芯片与所述基板引线键合的位置移除部分所述封装层，以形成布线沟槽，以及断开所述功能芯片与所述基板之间电连接的引线；
在所述布线沟槽内通过二次引线键合的方式将所述基板和/或所述功能芯片与所述第一电连接部电连接；以及
将封装材料填充于所述布线沟槽中形成包覆引线的覆盖层，并且使所述第一电连接部外露于所述覆盖层的表面上，以形成重新布线层。
在一实施例中，在所述布线沟槽内进行二次引线键合的步骤中，还包括：
在所述布线沟槽内引入第二电连接部，将所述第二电连接部通过引线键合的方式与所述基板和所述功能芯片中的至少一者进行电连接，再将所述第二电连接部通过引线键合与第一电连接部进行电连接。
本申请第三实施例提供一种电子设备。所述电子设备包括：如上所述的电子封装结构。
本申请的附加方面和优点将在下面的描述中部分给出，部分将从下面的描述中变得明显，或通过本申请的实践了解到。
附图说明
本申请的上述和/或附加的方面和优点从结合下面附图对实施例的描述中将变得明显和容易理解，其中：
图1-图5是根据本申请实施例的SIP封装结构的制作方法的流程图。
附图标记：
1、基板；2、功能芯片；3封装层；4、布线沟槽；5、覆盖层；6、第一电连接部；7、第二电连接部。
具体实施方式
下面详细描述本申请的实施例，参考附图描述的实施例是示例性的，下面详细描述本申请的实施例。
在本申请的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、 “水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”、“轴向”、“径向”、“周向”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
在本申请的描述中，“多个”的含义是两个或两个以上。
本申请实施例提供一种电子封装结构、电子封装结构的制作方法以及电子设备。
根据本申请的一个实施例，提供了一种电子封装结构。
所述电子封装结构例如为SIP封装。
所述SIP封装结构可为电子设备领域熟知的系统级封装。例如WiFi、蓝牙等通信芯片的封装体等。当然，也可以是其他类型的功能芯片，本申请在此不再详细列举。
本申请实施例提供的电子封装结构可应用于多种类型的电子设备中。
其中，所述电子设备例如可以是耳机、麦克风、扬声器、音响、电视、智能手机等，本申请在此不再详细列举。
图1至图5示出了本申请实施例提供的电子封装结构的制作流程示意图。其中的图5示出的是制作好的所述电子封装结构的一种具体结构形式，本申请实施例提供的电子封装结构并不限于该结构形式。
以下结合图1至图5对本申请实施例提供的电子封装结构进行较为详细地描述。
本申请实施例提供的电子封装结构，如图1至图5所示，其包括有：基板1，功能芯片2，封装层3以及重新布线层；
所述功能芯片2设置在所述基板1上，并与所述基板1电连接；
所述封装层3形成在所述基板1上，并覆盖所述功能芯片2，所述封装层3上开设有布线沟槽4；
所述重新布线层包括覆盖层5和第一电连接部6，在所述布线沟槽4内通过引线键合将所述基板1和/或所述功能芯片2与所述第一电连接部6电连接，所述覆盖层5填充在所述布线沟槽4内，所述第一电连接部6外露于所述覆盖层5的表面。
也就是说，在本申请实施例提供的方案中，其是通过采用引线键合的方式引出了第一电连接部6，所述第一电连接部6可用于与外部电路或者电信号建立电连接关系。也即，通过引线键合引出的第一电连接部6可相当于整个电子封装结构与外部电路进行电性连接的电连接件。这样通过所述第一电连接部6能使电子封装结构方便地电连 接到外部电路。
本申请实施例为电子封装结构提供了一种与外部电路进行电连接的方案，其中通过采用引线键合引出用于外接的电连接部，以此来代替传统植球(Ball in mold+Laser ablation)的方案。本申请实施例中的工艺较为简单。
在本申请实施例提供的方案中，通过采用引线键合的工艺引出所述第一电连接部6至所述电子封装结构的表面上，再通过使用封装工艺(即molding)固定引线的位置，这就形成了重新布线层，其能更好地实现封装制程中各功能芯片等的重新布线。本申请实施例提供的方案可以实现多层引线分布，还可简化芯片封装的制造流程，及减少制造时间和制造费用。
其中，所述基板1例如为印刷电路板PCB。
所述基板1是所述功能芯片2的支撑体，也是所述功能芯片2电气连接的载体。
其中，所述功能芯片2例如为高频芯片。
进一步地，所述功能芯片2例如为RF射频芯片、GPS定位芯片、DRAM存储芯片、蓝牙芯片等。并且，所述功能芯片2例如通过金属引线键合的方式与所述基板1进行电性连接。
所述功能芯片2包括但不限于上述类型的高频芯片。也就是说，所述功能芯片2也可以是其他类型的芯片，本领域技术人员可根据需要灵活设置所述功能芯片2的类型，本申请在此不作具体限制。
其中，所述封装层3可以采用本领域技术人员熟知的材料和工艺形成在所述基板1上，以将各所述功能芯片2封装在所述基板1上。
所述封装层3的材料包括但并不限于注塑塑料等高分子材料等。
其中，所述第一电连接部6可以作为所述电子封装结构的整体输入端/输出端，以提供电源、信号、接地等的传输。
本申请实施例所提供的方案中，在所述封装层3上开设有布线沟槽4。
需要说明的是，如图2所示，所述布线沟槽4是位于所述功能芯片2与所述基板1二者引线键合的位置。也就是说，在所述功能芯片2与所述基板1之间电连接的引线所在的位置处开设所述布线沟槽4，用以进行重新布线。之后在所述布线沟槽4内通过二次引线键合(Second Wire Bonding)工艺，即能实现多层引线分布。可见，在所述封装层3上开设所述布线沟槽4的目的在于后续重新布线提供基础。
此外，在所述布线沟槽4内进行二次引线键合工艺时，例如可以先打断所述功能芯片2与所述基板1之间电连接的引线，再将该引线键合至所述第一电连接部6。而需要注意的是，所述第一电连接部6并不是设置在所述布线沟槽4内部的。
在完成引线键合引出所述第一电连接部6之后，还要向所述布线沟槽4内填充封装材料，用以形成所述覆盖层5。所述覆盖层5可以固定各引线的位置。所述覆盖层5相当于进行二次封装。
在本申请的一些例子中，如图4和图5所示，所述重新布线层还包括、第二电连接部7，所述第二电连接部7设置于所述布线沟槽4内，并嵌入至所述覆盖层5之中；所述第二电连接部7通过引线键合电连接在所述基板1与所述第一电连接部6之间，或者电连接在所述功能芯片2与所述第一电连接部6之间。
也就是说，本申请实施例提供的方案，在形成所述重新布线层的过程中，还引入了所述第二电连接部7。其中所涉及的工艺是：先将所述功能芯片2和所述基板1中的至少一者通过引线键合的方式电连接至引入的所述第二电连接部7上，再将所述第二电连接部7通过引线键合的方式电连接至所述第一电连接部6，之后利用封装材料对所述布线沟槽4进行填充，也即进行二次封装工艺，即可形成所述覆盖层5。需要注意的是，所述第二电连接部7是嵌设在所述覆盖层5中的，而所述第一电连接部6是外露在所述覆盖层5的表面上的。
在本申请的一些例子中，如图2和图3所示，所述布线沟槽4的内部形成阶梯状结构，所述阶梯状结构包括第一阶梯层和位于所述第一阶梯层下方的第二阶梯层；所述第二电连接部7设置于所述第二阶梯层上；所述第一电连接部6设置于所述第一阶梯层上。
在本申请实施例所提供的方案中，通过合理布局所述布线沟槽4内部的结构形态，有助于合理布设用于重新布线所需的各电连接结构的位置，以便于借助所述第二电连接部7通过引线键合顺利地将所述第一电连接部6引出至所述电子封装结构之外作为I/O端。
在本申请的一些例子中，可通过镭射的方式形成所述布线沟槽4。
即采用Laser trench工艺形成所述布线沟槽4。也就是说，可以通过例如激光穿孔技术，在所述封装层3上形成所述布线沟槽4。而需要注意的是所述布线沟槽4并没有贯通所述封装层3。
其中，所述布线沟槽4例如设置在垂直于所述基板1的方向上。
此外，通过镭射的方式形成所述布线沟槽4具有速度快，及成型的布线沟槽内壁面平整、无毛边等优势。
在本申请的一些例子中，所述第二电连接部7为转接焊盘。
也就是说，所述第二电连接部7作为电转接件使用。能借助所述第二电连接部7将所述第一电连接部6引出至所述覆盖层5的表面。
在本申请的一些例子中，所述第一电连接部6为输入/输出焊盘。
也就是说，所述第一电连接部6作为电子封装结构的I/O端。
如图4和图5所示，所述第二电连接部7可通过引线/焊线以引线键合的方式向远离所述基板1的一侧引出所述第一电连接部6。在这样的情况下，所述第一电连接部6就作为整个电子封装结构的输入/输出端(I/O端)，而所述第二电连接部7就为电转接件使用。
需要说明的是，所述第一电连接部6及所述第二电连接部7的类型可以为焊盘，也可以为导电片(例如，金属片等)等形式，本领域技术人员可以根据具体情况灵活调整，本申请对此不作具体限制。
在本申请的一些例子中，如图5所示，所述覆盖层5的表面与所述封装层3的表面相齐平。这样使得形成的电子封装结构外观形态较好，也易于装配。
在本申请的一些例子中，所述封装层3与所述覆盖层5的材质相同。
例如，所述覆盖层5包括但并不限于注塑塑料等高分子材料等。
当然，所述覆盖层5的材质也可以与所述封装层3的材质不同。本领域技术人员可以根据具体情况进行调整，本申请在此不作具体限制。
在本申请的一些例子中，所述功能芯片2设置为一个或者多个。
可选的是，所述功能芯片2为高频芯片。也就是说，在所述基板1上排布的各所述功能芯片2可以为高频芯片。
例如，所述功能芯片2可为RF射频芯片、GPS定位芯片、DRAM存储芯片、蓝牙芯片等。
当然，所述功能芯片2包括但不限于上述类型的高频芯片。
根据本申请的另一个实施例，提供了一种电子封装结构的制作方法，其可用于制作上述的电子封装结构。
图1至图5示出了所述电子封装结构的制作方法的流程。
以下结合图1至图5对本申请实施例提供的电子封装结构的制作方法进行详细说明。
本申请实施例提供的一种电子封装结构的制作方法，其包括如下步骤：
步骤S1、如图1所示，提供基板1，将功能芯片2排布在所述基板1上，并通过引线键合的方式将所述功能芯片2与所述基板1电连接。
也就是说，所述步骤1为引线键合工艺，其目的就是将所述功能芯片2与所述基板1进行电性连接。
例如，继续参见图1，在所述功能芯片2上设置有焊垫，在所述基板1上也设置有焊垫，这两个所述焊垫之间可通过引线/焊线进行电连接，从而实现了所述功能芯片2与所述基板1之间的电性导通。
步骤S2、如图2所示，在所述基板1上形成覆盖所述功能芯片2的封装层3。
也就是说，在完成所述步骤1之后，接着要在所述基板1上设置封装结构，即上述提到的封装层3。也即，所述步骤2为封装工序(即molding)。
所述封装层3可用以将所述功能芯片2封装在所述基板1上，可起到保护所述功能芯片2的作用。而且，通过该封装工艺(molding)之后，还可以固定所述功能芯片2与所述基板1之间的引线位置。
步骤3、如图3所示，在所述功能芯片2与所述基板1引线键合的位置移除部分所述封装层3，以形成布线沟槽4，以及断开所述功能芯片2与所述基板1之间进行电连接的引线。
也就是说，所述步骤3中，其是在所述功能芯片2与所述基板1之间电连接的引线所在的位置进行开槽。
所述布线沟槽4的设计为了后续重新布线提供了基础。
步骤4、如图4所示，在所述布线沟槽4内通过二次引线键合的方式将所述基板1和/或所述功能芯片2与所述第一电连接部6进行电连接。
也就是说，在所述布线沟槽4形成之后继续进行引线键合工艺，这有助于后续实现多层引线分布。也即，所述步骤4实际可认为是二次引线键合工序(Second Wire Bonding)。
步骤5、如图5所示，将封装材料填充于所述布线沟槽4中形成包覆引线的覆盖层5，并且使所述第一电连接部6外露于所述覆盖层5的表面上，以形成重新布线层。
其中，所述第一电连接部6例如相当于整个所述电子封装结构的I/O端，其可用于与外部电路进行电性连接。
其中，所述封装材料能够用于包裹住连接所述第一电连接部6的引线/焊线等，即可形成所述重新布线层。
本申请实施例提供的制作方法中，采用了引线键合引出所述第一电连接部6，所述第一电连接部6远离所述基板1并露出于所述电子封装结构的表面，其中还通过二次封装工艺固定引线位置，可以实现多层引线分布。
本申请实施例提供的方案可以节省芯片封装中形成重新布线层的制造费用，而且可以简化芯片封装的制造流程。
传统重新布线层(redistribution layer，RDL)方案，为最大程度降低封装结构I/O端密度，常借助多种溅镀、沉积方式，通常在晶圆厂完成，设备成本高。本申请的方案使用成本低的WB设备可以直接完成重新布线层方案，克服了传统技术的缺陷。
在所述移除部分所述封装层3的步骤中，例如可以通过镭射的方式形成所述布线沟槽4。也即，采用Laser trench工艺。
也就是说，可以通过例如激光穿孔技术，在所述封装层3上形成所述布线沟槽4。
而需要注意的是所述布线沟槽4并没有贯通所述封装层3。所述布线沟槽4例如设置在垂直于所述基板1的方向上。
此外，通过镭射的方式形成沟槽具有速度快，及成型的沟槽内壁面平整、无毛边等优势。
在本申请的一些例子中，在所述布线沟槽内进行二次引线键合的步骤中，还包括如下步骤：
如图3至图5所示，在所述布线沟槽4内引入第二电连接部7，将所述第二电连接部7通过引线键合的方式与所述基板1和所述功能芯片2中的至少一者进行电连接，再将所述第二电连接部7通过引线键合与第一电连接部6进行电连接。
也就是说，在通过引线键合引出所述第一电连接部6时，还可以通过所述第二电连接部7作为电转接件来将所述第一电连接部6引出至所述覆盖层5的表面上。其中，所述第二电连接部7设置为转接焊盘，且连接有引线/焊线；所述第一电连接部6设置为输入/输出焊盘，其作为I/O端。
如图5所示，最终形成的所述重新布线层的表面应当与之前形成的所述封装层3 的表面是相齐平的。这样话所述电子封装几个的外观形态较好。
根据本申请的又一个实施例，还提供了一种电子设备。
所述电子设备包括如上任一项所述的电子封装结构。所述电子设备例如为智能手机、平板电脑、可穿戴设备等，本申请对此不做限制。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示意性实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施例或示例。
尽管已经示出和描述了本申请的实施例，本领域的普通技术人员可以理解：在不脱离本申请的原理和宗旨的情况下可以对这些实施例进行多种变化、修改、替换和变型，本申请的范围由权利要求及其等同物限定。

Claims (12)

  1. 一种电子封装结构，其特征在于，包括：
    基板(1)；
    功能芯片(2)，所述功能芯片(2)设置在所述基板(1)上，并与所述基板(1)电连接；
    封装层(3)，所述封装层(3)形成在所述基板(1)上，并覆盖所述功能芯片(2)，所述封装层(3)上开设有布线沟槽(4)；以及
    重新布线层，所述重新布线层包括覆盖层(5)和第一电连接部(6)，在所述布线沟槽(4)内通过引线键合将所述基板(1)和/或所述功能芯片(2)与所述第一电连接部(6)电连接，所述覆盖层(5)填充在所述布线沟槽(4)内，所述第一电连接部(6)外露于所述覆盖层(5)的表面。
  2. 根据权利要求1所述的电子封装结构，其特征在于，所述重新布线层还包括第二电连接部(7)，所述第二电连接部(7)设置于所述布线沟槽(4)内，并嵌入至所述覆盖层(5)之中；
    所述第二电连接部(7)通过引线键合电连接在所述基板(1)与所述第一电连接部(6)之间，或电连接在所述功能芯片(2)与所述第一电连接部(6)之间。
  3. 根据权利要求1或2所述的电子封装结构，其特征在于，所述布线沟槽(4)的内部形成阶梯状结构，所述阶梯状结构包括第一阶梯层和位于所述第一阶梯层下方的第二阶梯层；
    所述第二电连接部(7)设置于所述第二阶梯层上；
    所述第一电连接部(6)设置于所述第一阶梯层上。
  4. 根据权利要求1-3中任一项所述的电子封装结构，其特征在于，所述第二电连接部(7)为转接焊盘。
  5. 根据权利要求1-4中任一项所述的电子封装结构，其特征在于，所述第一电连接部(6)为输入/输出焊盘。
  6. 根据权利要求1-5中任一项所述的电子封装结构，其特征在于，所述覆盖层(5)的表面与所述封装层(3)的表面相齐平。
  7. 根据权利要求1-6中任一项所述的电子封装结构，其特征在于，所述封装层(3)与所述覆盖层(5)的材质相同。
  8. 根据权利要求1-7中任一项所述的电子封装结构，其特征在于，所述功能芯片(2)设置为一个或者多个，且所述功能芯片(2)为高频芯片。
  9. 根据权利要求1-8中任一项所述的电子封装结构，其特征在于，通过镭射的方式形成所述布线沟槽(4)。
  10. 一种如权利要求1-9中任一项所述的电子封装结构的制作方法，其特征在于，包括：
    提供基板，将功能芯片排布在所述基板上，并通过引线键合的方式将所述功能芯片与所述基板电连接；
    在所述基板上形成覆盖所述功能芯片的封装层；
    在所述功能芯片与所述基板引线键合的位置移除部分所述封装层，以形成布线沟槽，以及断开所述功能芯片与所述基板之间电连接的引线；
    在所述布线沟槽内通过二次引线键合的方式将所述基板和/或所述功能芯片与所述第一电连接部电连接；以及
    将封装材料填充于所述布线沟槽中形成包覆引线的覆盖层，并且使所述第一电连接部外露于所述覆盖层的表面上，以形成重新布线层。
  11. 根据权利要求10所述的电子封装结构的制作方法，其特征在于，在所述布线沟槽内进行二次引线键合的步骤中，还包括：
    在所述布线沟槽内引入第二电连接部，将所述第二电连接部通过引线键合的方式与所述基板和所述功能芯片中的至少一者进行电连接，再将所述第二电连接部通过引线键合与第一电连接部进行电连接。
  12. 一种电子设备，其特征在于，包括：
    如权利要求1-9中任一项所述的电子封装结构。
PCT/CN2022/134373 2021-11-25 2022-11-25 电子封装结构、电子封装结构的制作方法以及电子设备 Ceased WO2023093854A1 (zh)

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