TWI578421B - 可堆疊半導體封裝構造及其製造方法 - Google Patents

可堆疊半導體封裝構造及其製造方法 Download PDF

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Publication number
TWI578421B
TWI578421B TW105113516A TW105113516A TWI578421B TW I578421 B TWI578421 B TW I578421B TW 105113516 A TW105113516 A TW 105113516A TW 105113516 A TW105113516 A TW 105113516A TW I578421 B TWI578421 B TW I578421B
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Taiwan
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layer
pads
carrier
wafer
semiconductor package
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TW105113516A
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English (en)
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TW201738977A (zh
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葉昀鑫
徐宏欣
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力成科技股份有限公司
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Priority to TW105113516A priority Critical patent/TWI578421B/zh
Priority to US15/263,391 priority patent/US10249585B2/en
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Publication of TWI578421B publication Critical patent/TWI578421B/zh
Publication of TW201738977A publication Critical patent/TW201738977A/zh

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    • H01L2225/1047—Details of electrical connections between containers
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    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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Description

可堆疊半導體封裝構造及其製造方法
本發明係有關於半導體晶片封裝領域，特別係有關於一種可堆疊半導體封裝構造及其製造方法，可應用於封裝堆疊結構(Package-On-Package,POP)。
在現今半導體封裝技術中，為了達到多功能、高作動功率的需求，發展出封裝堆疊結構，將複數個半導體封裝構造縱向堆疊之組合。兩個或兩個以上的半導體封裝構造係經個別封裝與測試之後再以表面黏著方式疊合，以不佔用表面接合面積並具有高密度整合之效果，特別適用於整合複雜的、多種的邏輯元件與記憶體。
在常見的封裝堆疊結構中，一頂部封裝構造係直接表面接合至一底部封裝構造，以省略中介電路板。在一種習知的底部封裝構造之製造方法中，提供一印刷電路板，其上設置有複數個頂部球墊(top side ball pad)，接著以植球方式固定複數個第一銲球在位置對應的頂部球墊上並安裝晶片，再形成模封膠體覆蓋第一銲球與晶片，之後藉由雷射鑽孔(laser drill)製程在封膠體上開孔，以顯露出第一銲球。頂部封裝構造表面接合至底部封裝構造， 使得頂部封裝構造的第二銲球迴焊連接位置對應的第一銲球，以製作成封裝堆疊結構。然而，此一封裝堆疊結構具有中介銲球的尺寸與銲球間距的限制。第一銲球與第二銲球迴焊熔合會造成中介銲球的尺寸變化，當銲球間距過於狹小，中介銲球之間將產生銲料橋接的電性短路，進而造成封裝堆疊結構的生產良率下降。
為了解決上述之問題，本發明之主要目的係在於提供一種可堆疊半導體封裝構造及其製造方法，可實現封裝堆疊架構中底部封裝構造的尺寸小型化、封裝厚度薄型化以及中介銲球的細間距。
本發明之次一目的係在於提供一種可堆疊半導體封裝構造及其製造方法，充份了運用扇出型晶圓/面板等級封裝製程中的暫時載板，使得暫時載板得以保留於封裝構造中，省略了習知扇出型晶圓/面板等級封裝製程的剝離載板步驟並增加了封裝構造的剛性。
本發明的目的及解決其技術問題是採用以下技術方案來實現的。本發明揭示一種可堆疊半導體封裝構造，包含一載板、一第一重配置線路層、一封膠層、複數個縱向導通機構、一第二重配置線路層以及一晶片。該載板係具有一模封表面。該第一重配置線路層係形成於該載板之該模封表面上，該第一重配置線路層係包含複數個第一接墊以及複數個第二接墊。該封膠層係形成於該載板之該模封表面上，以覆蓋該第一重配置線路層，該 封膠層係具有一外表面。該些縱向導通機構係設置於該封膠層中，以電性連接至該第一重配置線路層並導通至該外表面。該第二重配置線路層係形成於該封膠層之該外表面上，以電性連接至該些縱向導通機構，該第二重配置線路層係包含複數個第三接墊。其中該載板係具有複數個端子孔以及一晶片容置開孔，該些端子孔係一對一對準地顯露該些第二接墊，該晶片容置開孔係區域地顯露該些第一接墊。該晶片係經由該晶片容置開孔安裝至該封膠層，以電性連接該些第一接墊，並且該載板係具有一厚度，以使該晶片不突出於該載板。本發明另揭示上述可堆疊半導體封裝構造之製造方法。
本發明的目的及解決其技術問題還可採用以下技術措施進一步實現。
在前述可堆疊半導體封裝構造中，可更包含複數個中介銲球，係可更經由該些端子孔接合至該些第二接墊，該些中介銲球之迴焊高度係可微突出於該載板。
在前述可堆疊半導體封裝構造中，該晶片係可覆晶接合至該封膠層，並且一底部填充膠係可形成於該晶片與該封膠層之間之空隙。
在前述可堆疊半導體封裝構造中，可更包含複數個表面接合銲球，係可接合至該些第三接墊而突出於該封膠層。
在前述可堆疊半導體封裝構造中，可更包含一保護層，係可形成於該封膠層之該外表面上，以局部覆蓋該第二重配 置線路層，但不覆蓋該些第三接墊。
在前述可堆疊半導體封裝構造中，該載板係可為一無電性傳輸功能的硬質板片。
上述的技術手段係提供一新封裝架構，該封膠體與該些重配置線路層係以模封互連基板(MIS)製程製作於該載板之一表面上，並在不剝離該載板之情況下，由該載板之另一表面進行雷射鑽孔，以形成該些端子孔與該晶片容置開孔，該些中介銲球係可設置於該些端子孔中，該晶片係安裝在該晶片容置開孔中。藉此能解決該些中介銲球的銲料橋接問題以及減少晶片安裝時對該些中介銲球與該些端子孔內球接墊的干擾，例如該底部填充膠不會污染到該些中介銲球與該些端子孔內球接墊，故而本發明之可堆疊半導體封裝構造可實現封裝堆疊架構中底部封裝構造的尺寸小型化、厚度薄型化以及中介銲球的細間距，進一步達成封裝堆疊架構的成本降低。
100‧‧‧可堆疊半導體封裝構造
110‧‧‧載板
111‧‧‧模封表面
112‧‧‧端子孔
113‧‧‧晶片容置開孔
120‧‧‧第一重配置線路層
121‧‧‧第一接墊
122‧‧‧第二接墊
130‧‧‧封膠層
131‧‧‧外表面
140‧‧‧縱向導通機構
150‧‧‧第二重配置線路層
151‧‧‧第三接墊
160‧‧‧晶片
161‧‧‧底部填充膠
162‧‧‧凸塊
163‧‧‧銲料
170‧‧‧保護層
180‧‧‧中介銲球
190‧‧‧表面接合銲球
200‧‧‧頂部封裝構造
210‧‧‧基板
220‧‧‧模封膠體
230‧‧‧外接墊
第1圖：依據本發明之一具體實施例，一種可堆疊半導體封裝構造之截面示意圖。
第2圖：依據本發明之一具體實施例，該可堆疊半導體封裝構造應用於一封裝堆疊結構中之截面示意圖。
第3A至3L圖：依據本發明之一具體實施例，繪示在該可堆疊半導體封裝構造之製造方法中主要步驟之元件截面示意圖。
以下將配合所附圖示詳細說明本發明之實施例，然應注意的是，該些圖示均為簡化之示意圖，僅以示意方法來說明本發明之基本架構或實施方法，故僅顯示與本案有關之元件與組合關係，圖中所顯示之元件並非以實際實施之數目、形狀、尺寸做等比例繪製，某些尺寸比例與其他相關尺寸比例或已誇張或是簡化處理，以提供更清楚的描述。實際實施之數目、形狀及尺寸比例為一種選置性之設計，詳細之元件佈局可能更為複雜。
依據本發明之一具體實施例，一種可堆疊半導體封裝構造100舉例說明於第1圖之截面示意圖。第2圖係繪示該可堆疊半導體封裝構造應用於一封裝堆疊結構中之截面示意圖。該可堆疊半導體封裝構造100係包含一載板110、一第一重配置線路層120、一封膠層130、複數個縱向導通機構140、一第二重配置線路層150以及一晶片160。
請參閱第1圖，該載板110係具有一模封表面111。該載板110可為一無電性傳輸功能的硬質板片，例如玻璃片或半導體板片，其中該半導體板片具體可為未設置積體電路且為半導體材質之虛晶片，更具體地，該半導體板片不限定於單晶矽片，業可以是多晶矽片或非晶矽片。該載板110係具有等同或接近的封裝尺寸，該載板110之周邊係切齊或略內縮於該可堆疊半導體封裝構造100之周邊。由於不需要載板剝離(de-carrier)之步驟，該模封表面111係可不具有黏著層。
該第一重配置線路層120係形成於該載板110之該模封表面111上，該第一重配置線路層120係包含複數個第一接墊121以及複數個第二接墊122。其中該些第一接墊121係形成於該模封表面111之中央區域，以供該晶片160之電性連接；該些第二接墊122係形成於該模封表面111之外周區域，以供封裝堆疊結構中介銲球之接合。該第一重配置線路層120之主要層形成方式係包含電鍍成型，其係先以物理氣相沉積或濺鍍方式在該載板110上全面形成一晶種層，並覆蓋上一光阻層，經微影成像露出線路形成區，再予以電鍍形成該第一重配置線路層120，而未有線路之晶種層區域因其厚度遠小於線路電鍍厚度，故可利用電漿蝕刻方式去除。具體地，該第一重配置線路層120之複數層材質係為鈦/銅/銅，其中鈦層與第一銅層係作為晶種層，其厚度可介於0.05~0.3微米(μm)，第二銅層係作為主要層，其厚度可介於2~5微米(μm)
該封膠層130係形成於該載板110之該模封表面111上，以覆蓋該第一重配置線路層120，該封膠層130係具有一外表面131。該封膠層130之材質係包含熱固性環氧化合物，可利用模封方式形成。在此結構中，該些第一接墊121與該些第二接墊122之側周邊係嵌陷於該封膠層130中。
該些縱向導通機構140係設置於該封膠層130中，以電性連接至該第一重配置線路層120並導通至該外表面131。該些縱向導通機構140之具體結構係可選自於模封貫孔(Through Molding Via,TMV)與金屬柱栓(metal pillar plug)其中之一，其中模封貫孔係包含複數個金屬層，其係形成在該封膠層130之貫穿孔之孔壁，金屬柱栓係為複數個電鍍形成之柱體，其係埋設於該封膠層130之貫穿孔中。該些縱向導通機構140係可對準於該些第二接墊122。
該第二重配置線路層150係形成於該封膠層130之該外表面131上，以電性連接至該些縱向導通機構140，該第二重配置線路層150係包含複數個第三接墊151。該第二重配置線路層150之形成方式與材質係可相同於該第一重配置線路層120，該第二重配置線路層150之主要層形成方式係包含電鍍成型。在本實施例中，一保護層170係可形成於該封膠層130之該外表面131上，以局部覆蓋該第二重配置線路層150，但不覆蓋該些第三接墊151。在此結構中，該些第三接墊151之側周邊係浮突於該封膠層130。
該載板110係具有複數個端子孔112以及一晶片容置開孔113，該些端子孔112係一對一對準地顯露該些第二接墊122，該晶片容置開孔113係區域地顯露該些第一接墊121。該些端子孔112之截面形狀係較佳地為開口擴大之半錐形。該晶片容置開孔113之開口尺寸係可略大於該晶片160之表面覆蓋尺寸。
該晶片160係經由該晶片容置開孔113安裝至該封膠層130，以電性連接該些第一接墊121，並且該載板110係具有一厚度，以使該晶片160不突出於該載板110。在本實施例中，該 晶片160係覆晶接合至該封膠層130，並且一底部填充膠161係形成於該晶片160與該封膠層130之間之空隙。該晶片160之主動表面係可設置有複數個凸塊162，複數個銲料163係設置於該些凸塊162之端面，以接合該晶片160之該些凸塊162至該些第一接墊121。在該載板110之阻隔下，該底部填充膠161與該些銲料163皆不會污染到該些端子孔112。
請參閱第1圖，該可堆疊半導體封裝構造100更可包含複數個中介銲球180，係經由該些端子孔112接合至該些第二接墊122，該些中介銲球180之迴焊高度係微突出於該載板110。該些端子孔112係可作為該些中介銲球180在植球時之球定位孔。
再請參閱第1圖，該可堆疊半導體封裝構造100可另包含複數個表面接合銲球190，係接合至該些第三接墊151而突出於該封膠層130，用以表面接合至一外部印刷電路板。
請參閱第2圖，該可堆疊半導體封裝構造100係可應用於一封裝堆疊結構中，一頂部封裝構造200係可堆疊結合至該可堆疊半導體封裝構造100上。該頂部封裝構造200係包含一基板210以及一形成於該基板210上之模封膠體220。複數個外接墊230係形成於該基板210之另一表面，該基板210係可為一微型印刷電路板、微型陶瓷電路板、IC晶片載板或是預模線路基板，該些中介銲球180係以迴焊方式接合至該些外接墊230。
第3A至3L圖係繪示在該可堆疊半導體封裝構造100之製造方法中主要步驟之元件截面示意圖。關於上述可堆疊半導 體封裝構造100之製造方法係說明如後。
請參閱第3A圖，首先，提供一載板110，該載板110係具有一模封表面111，該載板110可為一無電性傳輸功能的硬質板片，例如玻璃板。在本步驟中，該載板110係可為晶圓型態，或可為面板型態。
請參閱第3B圖，形成一第一重配置線路層120於該模封表面111上，該第一重配置線路層120係包含複數個第一接墊121以及複數個第二接墊122，該第一重配置線路層120之主要層形成方式係包含電鍍成型，該些第一接墊121係形成於該模封表面111之中央區域，該些第二接墊122係形成於該模封表面111之外周區域。
請參閱第3C圖，以模封方式形成一封膠層130於該載板110之該模封表面111上，以覆蓋該第一重配置線路層120，該封膠層130係具有一外表面131。上述模封方式係可為轉移模封或是壓縮模封。
之後，請參閱第3D圖，設置複數個縱向導通機構140於該封膠層130中，以電性連接至該第一重配置線路層120並導通至該外表面131。該些縱向導通機構140之形成方法係包含鑽孔與孔內電鍍，其中鑽孔係在該封膠層130中形成貫穿孔，孔內電鍍係在該封膠層130之貫穿孔內形成導電層或導電柱。該些縱向導通機構140之導電型態係可包含孔內金屬層或是金屬導通柱，其材質係可包含銅。
請參閱第3E圖，形成一第二重配置線路層150於該封膠層130之該外表面131上，以電性連接至該些縱向導通機構140，該第二重配置線路層150係包含複數個第三接墊151。該些縱向導通機構140局部外露於該外表面131之區域，而該第二重配置線路層150係覆蓋上述區域，該些第三接墊151係可浮突於該外表面131。
接著，請參閱第3F圖，形成一保護層170於該封膠層130之該外表面131上，以局部覆蓋該第二重配置線路層150，但不覆蓋該些第三接墊151。該保護層170之材質係可包含聚亞醯胺(Polyimide,PI)。該保護層170之形成方法係可包含化學氣相沉積或印刷。
請參閱第3G圖，在該封膠層130與該載板110翻轉180度之後，以對該載板110雷射鑽孔的方式形成複數個端子孔112於該載板110中。該些端子孔112係一對一對準地顯露該些第二接墊122。
之後，請參閱第3H圖，經由該些端子孔112，接合複數個中介銲球180至該些第二接墊122，該些中介銲球180之迴焊高度係微突出於該載板110。該些中介銲球180之材質係可為錫鉛合金或無鉛銲料。該些中介銲球180之形成方法係可包含植球與迴焊，亦可包含銲料印刷與迴焊。
請參閱第3I圖，形成一晶片容置開孔113於該載板110中，該晶片容置開孔113係區域地顯露該些第一接墊121。更 具體地，該晶片容置開孔113之開孔形狀係可為對應晶片之矩形，該晶片容置開孔113之尺寸係可略大於晶片尺寸。該晶片容置開孔113之形成方法係可包含雷射鑽孔或是蝕刻。
接著，請參閱第3J圖，經由該晶片容置開孔113安裝一晶片160至該封膠層130，以電性連接該些第一接墊121，並且該載板110係具有一厚度，以使該晶片160不突出於該載板110。更具體地，該晶片160係覆晶接合至該封膠層130。該晶片160之主動表面係可設置有複數個凸塊162，複數個銲料163係位置對應地設置於該些凸塊162之端面，以表面接合至該些第一接墊121上。之後，請參閱第3K圖，形成一底部填充膠161於該晶片160與該封膠層130之間之空隙，以包覆在該晶片160下之該些凸塊162與該些銲料163。
請參閱第3L圖，複數個表面接合銲球190係接合至該些第三接墊151，並且突出於該封膠層130，用以表面接合至一外部印刷電路板。因此，上述可堆疊半導體封裝構造100係得以製作形成。
請再參閱第3L圖，一頂部封裝構造200係可堆疊設置於該可堆疊半導體封裝構造100。該頂部封裝構造200係包含一基板210以及一形成於該基板210表面之模封膠體220，複數個外接墊230係形成於該基板210之外表面。該基板210係可為一微型印刷電路板、微型陶瓷電路板、IC晶片載板或是預模線路基板。該頂部封裝構造200係可對準設置於該可堆疊半導體封裝構造100上，該 些中介銲球180係迴焊接合於該些外接墊230，藉以製得如第2圖所示之一封裝堆疊結構(POP)。
因此，本發明提供了一種可堆疊半導體封裝構造及其製造方法，可實現封裝堆疊架構中底部封裝構造的尺寸小型化、厚度薄型化以及中介銲球的細間距，進一步達成封裝堆疊架構的成本降低。
以上所揭露的僅為本發明較佳實施例而已，當然不能以此來限定本發明之權利範圍，因此依本發明權利要求所作的等同變化，仍屬本發明所涵蓋的範圍。
100‧‧‧可堆疊半導體封裝構造
110‧‧‧載板
111‧‧‧模封表面
112‧‧‧端子孔
113‧‧‧晶片容置開孔
120‧‧‧第一重配置線路層
121‧‧‧第一接墊
122‧‧‧第二接墊
130‧‧‧封膠層
131‧‧‧外表面
140‧‧‧縱向導通機構
150‧‧‧第二重配置線路層
151‧‧‧第三接墊
160‧‧‧晶片
161‧‧‧底部填充膠
162‧‧‧凸塊
163‧‧‧銲料
170‧‧‧保護層
180‧‧‧中介銲球
190‧‧‧表面接合銲球

Claims (11)

  1. 一種可堆疊半導體封裝構造，包含：一載板，係具有一模封表面、複數個端子孔以及一晶片容置開孔；一第一重配置線路層，係形成於該載板之該模封表面上，該第一重配置線路層係包含複數個第一接墊以及複數個第二接墊，該些第一接墊係經由該晶片容置開孔為區域地顯露，該些第二接墊係經由該些端子孔為一對一對準地顯露；一封膠層，係形成於該載板之該模封表面上，以覆蓋該第一重配置線路層，該封膠層係具有一外表面；複數個縱向導通機構，係設置於該封膠層中，以電性連接至該第一重配置線路層並導通至該外表面；一第二重配置線路層，係形成於該封膠層之該外表面上，以電性連接至該些縱向導通機構，該第二重配置線路層係包含複數個第三接墊；以及一晶片，係經由該晶片容置開孔安裝至該封膠層，以電性連接該些第一接墊，並且該載板係具有一厚度，以使該晶片不突出於該載板。
  2. 如申請專利範圍第1項所述之可堆疊半導體封裝構造，另包含複數個中介銲球，係經由該些端子孔接合至該些第二接墊，該些中介銲球之迴焊高度係微突出於該載板。
  3. 如申請專利範圍第1項所述之可堆疊半導體封裝構造，其中 該晶片係覆晶接合至該封膠層，並且一底部填充膠係形成於該晶片與該封膠層之間之空隙。
  4. 如申請專利範圍第1項所述之可堆疊半導體封裝構造，另包含複數個表面接合銲球，係接合至該些第三接墊而突出於該封膠層。
  5. 如申請專利範圍第4項所述之可堆疊半導體封裝構造，另包含一保護層，係形成於該封膠層之該外表面上，以局部覆蓋該第二重配置線路層，但不覆蓋該些第三接墊。
  6. 如申請專利範圍第1項所述之可堆疊半導體封裝構造，其中該第一重配置線路層、該封膠層與該第二重配置線路層係形成在該複數個端子孔與該晶片容置開孔形成之前，以使該些第一接墊與該些第二接墊之複數個接合表面共平面於該封膠體之一內表面。
  7. 如申請專利範圍第1至6項任一項所述之可堆疊半導體封裝構造，其中該載板係為一無電性傳輸功能的硬質板片。
  8. 一種可堆疊半導體封裝構造之製造方法，包含：提供一載板，該載板係具有一模封表面；形成一第一重配置線路層於該模封表面上，該第一重配置線路層係包含複數個第一接墊以及複數個第二接墊；形成一封膠層於該載板之該模封表面上，以覆蓋該第一重配置線路層，該封膠層係具有一外表面；設置複數個縱向導通機構於該封膠層中，以電性連接至該第一重配置線路層並導通至該外表面； 形成一第二重配置線路層於該封膠層之該外表面上，以電性連接至該些縱向導通機構，該第二重配置線路層係包含複數個第三接墊；形成複數個端子孔於該載板中，該些端子孔係一對一對準地顯露該些第二接墊；形成一晶片容置開孔於該載板中，該晶片容置開孔係區域地顯露該些第一接墊；以及經由該晶片容置開孔安裝一晶片至該封膠層，以電性連接該些第一接墊，並且該載板係具有一厚度，以使該晶片不突出於該載板。
  9. 如申請專利範圍第8項所述之可堆疊半導體封裝構造之製造方法，另包含之步驟為：在形成該些端子孔於該載板中之步驟之後與在形成該晶片容置開孔於該載板中之步驟之前，經由該些端子孔，接合複數個中介銲球至該些第二接墊，該些中介銲球之迴焊高度係微突出於該載板。
  10. 如申請專利範圍第8項所述之可堆疊半導體封裝構造之製造方法，其中該晶片係覆晶接合至該封膠層，並且一底部填充膠係形成於該晶片與該封膠層之間之空隙。
  11. 如申請專利範圍第8項所述之可堆疊半導體封裝構造之製造方法，另包含之步驟為：在形成該第二重配置線路層於該外表面之步驟之後與在形成該些端子孔於該載板中之步驟之前，形成一保護層於該封膠層之該外表面上，以局部覆蓋該第二重配置線路層，但不覆蓋該些第三接墊。
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