CN109817597A - 一种电池保护芯片封装结构 - Google Patents
一种电池保护芯片封装结构 Download PDFInfo
- Publication number
- CN109817597A CN109817597A CN201711163786.9A CN201711163786A CN109817597A CN 109817597 A CN109817597 A CN 109817597A CN 201711163786 A CN201711163786 A CN 201711163786A CN 109817597 A CN109817597 A CN 109817597A
- Authority
- CN
- China
- Prior art keywords
- chip
- packing
- metal block
- chip packing
- encapsulating structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Connection Of Batteries Or Terminals (AREA)
Abstract
Description
Claims (10)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201711163786.9A CN109817597A (zh) | 2017-11-21 | 2017-11-21 | 一种电池保护芯片封装结构 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201711163786.9A CN109817597A (zh) | 2017-11-21 | 2017-11-21 | 一种电池保护芯片封装结构 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN109817597A true CN109817597A (zh) | 2019-05-28 |
Family
ID=66599206
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201711163786.9A Pending CN109817597A (zh) | 2017-11-21 | 2017-11-21 | 一种电池保护芯片封装结构 |
Country Status (1)
Country | Link |
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CN (1) | CN109817597A (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110429075A (zh) * | 2019-07-19 | 2019-11-08 | 广东气派科技有限公司 | 高密度多侧面引脚外露的封装结构及其生产方法 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101276798A (zh) * | 2007-03-26 | 2008-10-01 | 国家半导体公司 | 隔离焊料垫 |
CN101764127A (zh) * | 2008-12-23 | 2010-06-30 | 日月光封装测试(上海)有限公司 | 无外引脚的半导体封装体及其堆迭构造 |
CN102136434A (zh) * | 2010-01-27 | 2011-07-27 | 马维尔国际贸易有限公司 | 在引线键合的芯片上叠置倒装芯片的方法 |
CN203733791U (zh) * | 2013-12-20 | 2014-07-23 | 南通富士通微电子股份有限公司 | 半导体叠层封装结构 |
CN205039149U (zh) * | 2014-09-30 | 2016-02-17 | 瑞萨电子株式会社 | 半导体器件 |
CN106601627A (zh) * | 2016-12-21 | 2017-04-26 | 江苏长电科技股份有限公司 | 先封后蚀电镀铜柱导通三维封装结构的工艺方法 |
US20170317041A1 (en) * | 2016-04-29 | 2017-11-02 | Powertech Technology Inc. | Stackable semiconductor package and manufacturing method thereof |
-
2017
- 2017-11-21 CN CN201711163786.9A patent/CN109817597A/zh active Pending
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101276798A (zh) * | 2007-03-26 | 2008-10-01 | 国家半导体公司 | 隔离焊料垫 |
CN101764127A (zh) * | 2008-12-23 | 2010-06-30 | 日月光封装测试(上海)有限公司 | 无外引脚的半导体封装体及其堆迭构造 |
CN102136434A (zh) * | 2010-01-27 | 2011-07-27 | 马维尔国际贸易有限公司 | 在引线键合的芯片上叠置倒装芯片的方法 |
CN203733791U (zh) * | 2013-12-20 | 2014-07-23 | 南通富士通微电子股份有限公司 | 半导体叠层封装结构 |
CN205039149U (zh) * | 2014-09-30 | 2016-02-17 | 瑞萨电子株式会社 | 半导体器件 |
US20170317041A1 (en) * | 2016-04-29 | 2017-11-02 | Powertech Technology Inc. | Stackable semiconductor package and manufacturing method thereof |
CN106601627A (zh) * | 2016-12-21 | 2017-04-26 | 江苏长电科技股份有限公司 | 先封后蚀电镀铜柱导通三维封装结构的工艺方法 |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110429075A (zh) * | 2019-07-19 | 2019-11-08 | 广东气派科技有限公司 | 高密度多侧面引脚外露的封装结构及其生产方法 |
CN110429075B (zh) * | 2019-07-19 | 2020-07-14 | 广东气派科技有限公司 | 高密度多侧面引脚外露的封装结构及其生产方法 |
WO2021012641A1 (zh) * | 2019-07-19 | 2021-01-28 | 广东气派科技有限公司 | 高密度多侧面引脚外露的封装结构及其生产方法 |
US11088053B2 (en) | 2019-07-19 | 2021-08-10 | Guangdong Chippacking Technology Co., Ltd. | Encapsulation structure with high density, multiple sided and exposed leads and method for manufacturing the same |
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Date | Code | Title | Description |
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PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
TA01 | Transfer of patent application right | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20191224 Address after: 518119 1 Yanan Road, Kwai Chung street, Dapeng New District, Shenzhen, Guangdong Applicant after: Shenzhen BYD Microelectronics Co., Ltd. Address before: BYD 518118 Shenzhen Road, Guangdong province Pingshan New District No. 3009 Applicant before: Biyadi Co., Ltd. |
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CB02 | Change of applicant information | ||
CB02 | Change of applicant information |
Address after: 518119 1 Yanan Road, Kwai Chung street, Dapeng New District, Shenzhen, Guangdong Applicant after: BYD Semiconductor Co.,Ltd. Address before: 518119 1 Yanan Road, Kwai Chung street, Dapeng New District, Shenzhen, Guangdong Applicant before: SHENZHEN BYD MICROELECTRONICS Co.,Ltd. |
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CB02 | Change of applicant information | ||
CB02 | Change of applicant information |
Address after: 518119 No.1 Yan'an Road, Kuiyong street, Dapeng New District, Shenzhen City, Guangdong Province Applicant after: BYD Semiconductor Co.,Ltd. Address before: 518119 No.1 Yan'an Road, Kuiyong street, Dapeng New District, Shenzhen City, Guangdong Province Applicant before: BYD Semiconductor Co.,Ltd. |
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RJ01 | Rejection of invention patent application after publication | ||
RJ01 | Rejection of invention patent application after publication |
Application publication date: 20190528 |