WO2021012641A1 - 高密度多侧面引脚外露的封装结构及其生产方法 - Google Patents

高密度多侧面引脚外露的封装结构及其生产方法 Download PDF

Info

Publication number
WO2021012641A1
WO2021012641A1 PCT/CN2020/071108 CN2020071108W WO2021012641A1 WO 2021012641 A1 WO2021012641 A1 WO 2021012641A1 CN 2020071108 W CN2020071108 W CN 2020071108W WO 2021012641 A1 WO2021012641 A1 WO 2021012641A1
Authority
WO
WIPO (PCT)
Prior art keywords
pins
base island
pin
package structure
boss
Prior art date
Application number
PCT/CN2020/071108
Other languages
English (en)
French (fr)
Inventor
饶锡林
文正国
杨建伟
黄乙为
斯毅平
刘方标
Original Assignee
广东气派科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 广东气派科技有限公司 filed Critical 广东气派科技有限公司
Priority to EP20844301.0A priority Critical patent/EP4002446A4/en
Priority to US17/256,602 priority patent/US11088053B2/en
Publication of WO2021012641A1 publication Critical patent/WO2021012641A1/zh

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49548Cross section geometry
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4821Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4825Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4821Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4842Mechanical treatment, e.g. punching, cutting, deforming, cold welding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4885Wire-like parts or pins
    • H01L21/4889Connection or disconnection of other leads to or from wire-like parts, e.g. wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4885Wire-like parts or pins
    • H01L21/4896Mechanical treatment, e.g. cutting, bending
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367Cooling facilitated by shape of device
    • H01L23/3677Wire-like or pin-like cooling fins or heat sinks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49503Lead-frames or other flat leads characterised by the die pad
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49517Additional leads
    • H01L23/4952Additional leads the additional leads being a bump or a wire
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49517Additional leads
    • H01L23/49524Additional leads the additional leads being a tape carrier or flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49548Cross section geometry
    • H01L23/49551Cross section geometry characterised by bent parts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49568Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561Batch processing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8536Bonding interfaces of the semiconductor or solid state body
    • H01L2224/85365Shape, e.g. interlocking features
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49575Assemblies of semiconductor devices on lead frames
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Definitions

  • the invention relates to the technical field of chip packaging, in particular to a high-density packaging structure with exposed pins on multiple sides and a production method thereof.
  • Semiconductor integrated circuits are the core of modern technology, the brains of intelligent products, and the basis for the development of modern science and technology; in addition, they are also the basis of human modern civilization, which fundamentally changes people’s lifestyles, such as artificial intelligence and the Internet of Things. , Internet, computers, TVs, refrigerators, mobile phones, various automatic control devices, etc., all rely on integrated circuits to realize their intelligent functions.
  • the manufacturing of integrated circuits is divided into design, chip manufacturing, packaging, and testing. Packaging is the key link.
  • the packaging form based on packaging technology is to meet the performance, volume, reliability, and shape of integrated circuits for various purposes. And the special requirements of cost.
  • Integrated circuit packaging technology includes: 1. Process and technology, through the use of grinding and cutting technology that can ensure the perfect lattice structure of the single crystal material to separate the integrated circuit wafer into a single chip that meets the requirements, using conductive glue or eutectic technology Fix the chip to the lead frame base island, connect the chip and the outer lead pins with micro-connection technology (micron level), and then use polymer materials or ceramic materials to protect the chip and leads; 2. Package structure research and development, products The volume requirements are getting smaller and smaller, and the electrical and thermal performance requirements are getting higher and higher.
  • the packaging types of integrated circuits can be summarized into two categories: hermetic ceramic packaging and plastic packaging.
  • the hermetic ceramic package is packaged in a way that the chip is isolated from the surrounding surroundings by a vacuum sealing device.
  • the typical hermetic ceramic package is applied to a high-performance packaging level.
  • Plastic encapsulation uses epoxy resin to encapsulate chips.
  • Plastic encapsulation technology has developed significantly in its application and efficacy. It can fully meet the needs of industrial and civilian products. The material cost is low and the production process of plastic encapsulation can be automated. , Thereby effectively reducing the cost, the current industrial and civilian products mainly use plastic packaging.
  • QFN Quad Flat No-lead Package
  • DFN Dual Flat No-lead Package
  • the packaging process is complicated, such as the lead frame requires an etching process Production, quality is difficult to control, environmental pollution, low efficiency, and expensive; the back needs to be pasted, the bonding efficiency is reduced by more than 30%, the loss of the wedge is more than 2 times; the cutting method is inefficient, the equipment is expensive, the quality is difficult to control, and the whole The process control is difficult and the efficiency is low when the machine is used. Due to the functional and volume requirements of modern products, especially computers, mobile phones, IPADs, and other portable devices, these two series of products are the packaging structures that account for the absolute majority of current mid-to-high-end packaging products.
  • the packaging form of integrated circuits has a significant impact on the performance (electrical and thermal performance), reliability, and cost of integrated circuit products.
  • performance electrical and thermal performance
  • cost Cost of integrated circuit products.
  • chip manufacturing technology from micrometers to nanometers
  • Moore's law of doubling the functions of chips per unit area every 18 months is gradually failing.
  • powerful cloud computing, Internet of Things and mobile networks in the Internet must rely on its core technology.
  • the breakthrough of integrated circuits, the improvement of integrated circuits in terms of large capacity, high speed, and low power consumption, will become more and more difficult in chip manufacturing, requiring a greater degree of packaging and technological breakthroughs.
  • the present invention provides a high-density package structure with exposed pins on multiple sides and a production method thereof, aiming to reduce the thickness and volume of the package structure, reduce the internal resistance and thermal resistance of the package, and/or improve the plastic packaging of the pins/base islands Stability and/or bonding/welding quality improves product performance and reliability.
  • a high-density package structure with exposed pins on multiple sides is provided.
  • the base island and the pins are provided at the bottom of the body, and the bottom surface of the pins is exposed on the bottom surface of the body, and the pins extend to multiple sides of the body and protrude Beyond the ontology
  • the body includes an integrated circuit provided on the base island and connected to the pins, and a plastic package body for packaging the integrated circuit, the base island and the pins;
  • the bottom surface of the plastic package and the bottom surface of the pin are on the same horizontal plane
  • the pin includes a first pin isolated from the base island.
  • the base island is exposed on the bottom surface of the body, and the bottom surface of the base island and the bottom surface of the plastic package are on the same horizontal plane.
  • the main body has four side surfaces, and a plurality of the pins respectively extend to two opposite sides or four side surfaces of the main body and protrude out of the main body.
  • the first pin includes a straight portion extending on a horizontal surface, and one end of the straight portion extends out of the body.
  • the first pin further includes a turning part extending on a horizontal plane, the turning part is connected to the other end of the straight part located in the body, and the turning part is located in the body,
  • the turning portion includes an inclined section and a parallel section, and the parallel section and the straight section are parallel to each other and connected by the inclined section;
  • L1 is the length of the straight section
  • L2 is the length of the inclined section
  • L3 is the length of the parallel section
  • is the angle between the inclined section and the straight section.
  • one end of the first pin located in the body has a first end surface facing the base island, and the base island has a second end surface facing the first end surface; There is a first groove, and/or, a second groove is provided on the second end surface.
  • the upper surface of the end of the first pin located in the body has a third groove, and/or the upper surface of the base island on the side close to the first pin has a fourth groove. Groove.
  • the upper surface of the end of the first pin located in the body is provided with a T-shaped boss
  • the T-shaped boss includes a boss supporting platform connected to the upper surface of the first pin and
  • the boss welding platform is arranged on the top of the boss support platform, and the width of the boss welding platform is greater than the width of the boss support platform.
  • the height A of the T-shaped boss and the height C of the first pin satisfy the following formula:
  • the integrated circuit, the base island and the pins are plastic-encapsulated to obtain a package structure body, wherein the base island and the pins are arranged at the bottom of the body, and the bottom surface of the pins is exposed On the bottom surface of the main body, and the pins extend to multiple sides of the main body and protrude out of the main body, and the bottom surface of the plastic package body and the bottom surface of the pins are on the same horizontal plane;
  • the base island and the pins are arranged at the bottom of the body, and the pins are exposed on the bottom surface of the body, and the pins extend out of the body from multiple sides, and the base island can be exposed on the bottom surface of the body;
  • the thickness and volume of the entire package structure are further reduced; the internal resistance and thermal resistance of the package are further reduced, with better heat dissipation performance and improved product frequency characteristics; and the pin density is increased, and the applicability is enhanced; and the planar component
  • the pin has higher strength and soldering force stability, ensuring more reliable product performance; the entire package structure is reduced in volume, and the material used is reduced, further reducing product costs; the overall coplanarity of the package structure is better, and the punching can be used Cutting process processing, processing complexity and difficulty are further reduced; the plastic packaging stability of the lead/base island and/or the quality of bonding/welding are improved.
  • Figure 1-1 is a schematic structural diagram of a high-density package structure with multiple side leads exposed according to an embodiment of the present invention
  • 1-2 is a cross-sectional view of a high-density package structure with exposed pins on multiple sides according to an embodiment of the present invention
  • FIG. 2-1 is a schematic structural diagram of a high-density package structure with exposed pins on multiple sides according to another embodiment of the present invention
  • 2-2 is a schematic bottom view of a high-density package structure with multiple side pins exposed according to another embodiment of the present invention
  • 2-3 is a schematic diagram of the pin structure of a high-density package with multiple side pins exposed according to another embodiment of the present invention.
  • FIG. 3 is a cross-sectional view of a high-density package structure with exposed pins on multiple sides according to another embodiment of the present invention.
  • Figure 4-1 is a schematic diagram of a plastic sealing tight groove in an embodiment of the present invention.
  • Figure 4-2 is a schematic diagram of another plastic sealing tight groove in an embodiment of the present invention.
  • Fig. 4-3 is a schematic diagram of another plastic sealing tight groove in the embodiment of the present invention.
  • 4-4 is a schematic diagram of a package structure including a boss according to an embodiment of the present invention.
  • 4-5 is a detailed structural diagram of a package structure including a boss according to an embodiment of the present invention.
  • 4-6 are schematic diagrams of the structural dimensions of the boss in an embodiment of the present invention.
  • Figure 5-1 is a schematic diagram of a package structure including a single base island according to an embodiment of the present invention.
  • 5-2 is a schematic diagram of a package structure including dual-base islands according to an embodiment of the present invention.
  • 5-3 is a schematic diagram of a package structure including three base islands according to an embodiment of the present invention.
  • Fig. 6 is a schematic diagram of a conventional package structure
  • Figure 7-1 is a schematic diagram of the packaging structure of an exceptional Luke Island in an embodiment of the present invention.
  • Fig. 7-2 is a schematic diagram of a package structure of an undisclosed base island according to an embodiment of the present invention.
  • 8-1 is a schematic diagram of a package structure with symmetrical pins exposed on four sides of an embodiment of the present invention
  • 8-2 is a schematic diagram of a package structure with symmetrical pins exposed on both sides of an embodiment of the present invention
  • 8-3 is a schematic diagram of a package structure with asymmetric pins exposed on four sides according to an embodiment of the present invention.
  • 9-1 is a schematic diagram of a package structure with T-shaped pins exposed on four sides in an embodiment of the present invention.
  • Fig. 9-2 is a schematic diagram of a package structure using bump pins in an embodiment of the present invention.
  • Fig. 10 is a flowchart of a method for producing a package structure according to an embodiment of the present invention.
  • the embodiment of the present invention provides a high-density, multi-side-lead exposed package structure, which includes a body 10 and a lead frame.
  • the body 10 of the base island 20 and the pin 30 includes an integrated circuit 11 and a plastic package body 12, and the body 10 may also include a metal wire 13 and a solder 14.
  • the base island 20 and the pins 30 are provided at the bottom of the body 10, and the bottom surface of the pins 30 is exposed on the bottom surface of the body 10, and the pins 30 face more of the body 10.
  • Two side surfaces extend and protrude beyond the body 10; the integrated circuit 11 is arranged on the base island 20 and connected to the pin 30, and the plastic package 12 is used to encapsulate the integrated circuit 11, the The base island 20 and the pin 30.
  • the metal wire 13 is used to connect the integrated circuit 11 and the pin 30, and the solder 14 is used to connect the integrated circuit 11 and the base island 20.
  • the pin 30 may adopt a planar member, that is, only extend on a horizontal surface; of course, in some embodiments, a non-planar member may also be used.
  • the entire bottom surface of the pin 30 may be exposed on the bottom surface of the local 10 or part of the bottom surface of the pin 30 may be exposed on the bottom of the local 10.
  • the base island 20 may be exposed on the bottom surface of the main body 10, or the base island 20 may not be exposed but all located inside the main body 10.
  • the bottom surface of the plastic package 12, and/or the bottom surface of the base island 20, and/or the bottom surface of the pin 30 may be on the same horizontal plane.
  • the body 10 may be square or rectangular, and may have four sides.
  • the plurality of pins 30 can respectively extend to two opposite sides or four sides of the main body 10, and protrude out of the main body 10; the pins 30 on opposite sides can be symmetrical or Asymmetry.
  • the base island 20 and the pins 30 can be made of metal materials, specifically copper alloys; the plastic package body 12 can be made of plastic materials.
  • the pin 30 may include a first pin 31 isolated from the base island 20, and the first pin 31 may It includes a straight portion 311 extending on a horizontal surface, one end of the straight portion 311 extends out of the main body 10, and the bottom surface of the straight portion 311 is exposed to the bottom surface of the main body 10.
  • the illustrated pin 30 may also include a second pin 32 connected to the base island 20.
  • the first pin 31 may further include a turning portion 312 extending on a horizontal surface, and the turning portion 312 and the straight portion 311 are located at the same place.
  • the other end of the main body 10 is connected, and the turning portion 312 is located in the main body 10.
  • the turning portion 312 is used to strengthen the connection strength between the first pin 30 and the plastic package 12.
  • the turning portion 312 may be a component perpendicular to the straight portion 311.
  • the turning portion 312 may also include an inclined section connected with the straight section 311 and a parallel section connected with the inclined section in sequence.
  • the turning portion 312 can also take other various shapes.
  • the turning portion includes an inclined section 312b and a parallel section 312a, and the parallel section 312a and the straight section 311 are parallel to each other and connected by the inclined section 312b;
  • the turning portion 312 and the straight portion 311 satisfy the following relationship:
  • L1 is the length of the straight section 311
  • L2 is the length of the inclined section 312b
  • L3 is the length of the parallel section 312a
  • is the angle between the inclined section 312b and the straight section 311 .
  • the ratio of the length of the straight portion 311 inside the body 10 to the length outside the body 10 is between 2:3 and 2:5, preferably 1:2.
  • the entire first pin 31 satisfies an excellent stress relationship and is not easily deformed; and the combination with the body 10 is better and has excellent firmness.
  • the parallel section 312a can be used to connect the metal wire 13 to realize the connection with the integrated circuit 11.
  • the parallel section 312a has an appropriate welding area and thermal conductivity, and the welding force is stable, which helps to improve welding. quality.
  • the integrated circuit 11 can be fixed on the front surface of the base island 20 with solder 14 through a die bonding or reflow process, and is connected with a wire (wire) 13
  • the pins 30 are connected.
  • the solder 14 may be, for example, a solder paste provided in a reflow soldering process.
  • one end of the first pin 31 located in the body 10 has a first end surface 33 facing the base island 20, and the base island 20 has The second end face 21 of the first end face 33; the first end face 33 is provided with a first groove 34, and/or the second end face 21 is provided with a second groove 22.
  • the first groove 34 and the second groove 22 can be provided on the side close to the bottom surface of the body 10, so that a T-shaped plastic seal can be formed between the first end surface 33 and the second end surface 21. ⁇ 40.
  • the plastic sealing groove 40 helps to firmly fix the base island 20 and the pins 30 in the plastic package body 12.
  • first groove 34 and the second groove 22 can also be provided on the side away from the bottom surface of the body 10, so that an inverted T-shaped shape can be formed between the first end surface 33 and the second end surface 21 Plastic seal tight groove 40.
  • the upper surface of one end (end) of the first pin 31 located in the body 10 may further have a third groove 35, and/or,
  • the upper surface of the base island 20 close to the first pin 31 may also have a fourth groove 23.
  • the third groove 35 and/or the fourth groove 23 can be used to form a grooved molded plastic sealing tight groove, which can further firmly fix the base island 20 and the pins 30 in the plastic package 12.
  • the upper surface of one end (end) of the first pin 31 located in the body 10 may also be provided with a boss 36.
  • the first pin 31 includes a straight portion 311, and an upper surface of one end of the straight portion 311 located in the body 10 is provided with a boss 36; or, the first pin 31 It also includes a turning portion 312 connected to the straight portion 311, and an upper surface of the turning portion 312 close to the integrated circuit 11 is provided with a boss 36.
  • the boss 36 is used to weld the metal wire 13 to realize the connection with the integrated circuit 11; on the other hand, it is inserted into the body 10 as a protrusion, and is well combined with the plastic package 12 to firmly fix the first pin 31 on In the body 10.
  • the boss 36 can be a T-shaped boss, including a boss support 362 and a boss welding platform 361, the boss support 362 is connected to the first pin 31
  • the boss welding platform 361 is set on the top of the boss support platform 362, and the width of the boss welding platform 361 is greater than the width of the boss support platform 362 so that the cross section of the boss 36 is T-shaped.
  • the upper surface of the boss welding table 361 is a welding surface (the boss welding surface) for welding the metal wire 13.
  • the boss welding platform 361 is a column, such as a cylinder, and the boss support 362 is also a main body, such as a cylinder, and the two can be coaxial cylinders, and the diameter of the boss welding platform 361 is larger than that of the boss.
  • the T-shaped boss has a large upper part and a smaller lower part, which can be firmly fixed in the plastic package body 12.
  • the above T-shaped boss structure design satisfies the following characteristics:
  • the T-shaped boss is composed of a boss support and a boss welding platform.
  • the total height is A
  • the height of the boss support 362 is B
  • the height of the boss welding table 361 is H
  • the diameter of the boss support 362 is E
  • the boss The diameter of the welding table 361 is D.
  • the height of the T-shaped boss must meet certain requirements. If the boss is too high, the welding force of the second welding point of the wire will be unstable, which will affect the welding quality. If the boss is too low, the advantages and effects of the boss structure are difficult to reflect. Manufacturing is also very difficult. Through theoretical calculation and experimental verification, it is concluded that when the height of the boss meets a certain ratio to the height of the pin, the stability of the boss (welding station welding force stability) is good, and the advantages of the boss structure It is clear.
  • the height A of the T-shaped boss and the height C of the pin (base island) satisfy the following formula:
  • the height of the T-shaped boss is designed to be between 50% and 71% of the overall thickness of the boss + pin, and the optimal height of the T-shaped boss is the golden ratio of the overall thickness of the boss + pin.
  • the T-shaped boss also satisfies the following formula:
  • the diameter D of the boss welding table is 100-300 times the diameter of the wire, or the ratio of the diameter D of the boss welding table to the diameter of the wire is between 100:1 and 300:1, so Achieve good welding performance.
  • the T-shaped boss structure design can be used as a welding pad, and it can also lock the plastic package body and fix the pins in the plastic package body.
  • the T-shaped boss structure design only needs to be silver-plated on the welding surface of the upper surface of the boss, which reduces the silver plating materials and saves costs.
  • the T-shaped boss structure design reduces the height difference between the integrated circuit and the pins, reduces the arc height of the bonding wire, and slows down the wire arc of the first solder joint (the solder joint on the integrated circuit)
  • the shape angle is conducive to the control of the bonding arc height, reduces the neck damage problem caused by the excessive arc of the first welding point of the bonding wire, and improves the bonding quality.
  • the T-shaped boss structure design has better stability and more stable bonding force, which is more conducive to the second solder joint between the bonding wire and the pin ( The solder joint located on the welding surface of the boss of the pin) is welded, which improves the welding quality of the second solder joint.
  • T-shaped boss structure design The structure is designed according to the thickness of the lead frame, the thickness of the chip and the diameter of the welding wire to ensure the best packaging structure effect at one time.
  • different numbers and shapes of base islands can be designed according to the requirements (functional complexity) of different products to meet relevant requirements, that is, the number and shape of the base islands 20 are not limited.
  • one base island 20 can be encapsulated in the body 10; as shown in Figure 5-2, two islands 20 can also be encapsulated in the body 10; as shown in Figure 5-3, the body 10 is also Three base islands 20 can be packaged; according to needs, more base islands 20 can be packaged in the body 10.
  • the packaging structure of the embodiment of the present invention can determine whether the base island 20 is exposed or not exposed according to the requirements of different products. As shown in FIG. 7-1, the base island 20 may be exposed on the bottom surface of the main body 10; or, as shown in FIG. 7-2, the base island 20 may not be exposed, but is located inside the main body 10.
  • the packaging structure of the embodiment of the present invention can determine the distribution of the pins 30 according to the requirements of different products.
  • the pins 30 can be distributed on two or four sides of the body 10, and the pins 30 on the opposite sides can be symmetrical. It can also be asymmetric.
  • the pins 30 can be distributed on the four sides of the body 10, and the pins 30 on opposite sides are symmetrical; as shown in Figure 8-2, the pins 30 can be distributed on both sides of the body 10.
  • the pins 30 can be distributed on the four sides of the body 10, and the pins 30 on opposite sides are asymmetrical.
  • the pins 30 may adopt various shapes, such as a strip shape, a T shape, or other shapes.
  • the pin 30 may be a straight long strip pin.
  • the pin 30 may be a T-shaped pin, that is, a straight portion 311 is vertically connected to a turning portion 312.
  • the pin 30 can also be an internal raised pin (internal raised pin), that is, the pin 30 can include a straight portion 311, and the straight portion 311 can be connected to an upper convex portion 313. Therefore, the pin 30 of this form can be better combined with the body 10 and is stronger.
  • the pin 30 shown in FIGS. 8-1 to 8-3 and FIG. 9-1 is a planar member
  • the pin 30 shown in FIG. 9-2 is a non-planar member.
  • the packaging structure of the present invention has a number of technical improvements:
  • Figure 6 is a traditional chip packaging structure. It can be seen from the figure that its base island 61 is located at the center of the plastic package 60 and is completely sealed by the plastic package; its pin 63 is bent into a Z-shape on the vertical surface, and includes a first part 631 located inside the plastic package. A second portion 632 that is connected to the first portion 631 and is bent downward, and a third portion 633 that is connected to the second portion and extends horizontally.
  • the traditional packaging structure has defects such as large size, thick product, large volume, and limited assembly space in the lower level.
  • the packaging structure of the present invention because the base island and the pins are arranged at the bottom of the body, and can use planar components, the vertical dimension is extremely small, so that the entire product is very thin, the thickness is reduced by about 1/2, and the entire product volume is reduced to About 40%, suitable for assembly in a smaller space, and can meet the requirements of high-integration and small-volume lower-level assembly, such as the assembly of high-end system-in-package modules.
  • the traditional packaging structure the base island is inside, there is no exposed, the heat dissipation is general, and the products that cannot meet the high heat dissipation requirements, the product scope is limited.
  • the packaging structure of the present invention has exposed base islands and better heat dissipation. It can be applied to products with high heat dissipation requirements and has wider applicability (such as LED power modules, 5G communication power modules, motor drive modules, etc.). Of course, it can also Flexible choice of exposed or non-exposed base island.
  • the pins are relatively distributed on both sides of the product, and the space on both sides is limited, so the number of pins is small.
  • the pins can be relatively distributed on multiple sides of the product, such as four sides, which fully utilizes the space on the four sides of the product, and greatly increases the number of pins under the condition that the product volume remains unchanged. Twice the packaging structure to meet the multiple output ports of more complex products, achieve high integration, complexity, and miniaturization, and enhance applicability.
  • the pins need to be folded into a Z shape.
  • the pins are formed by external mechanical force, the product pins are prone to deformation and damage to the plastic package.
  • the pins do not need to be Z-shaped, and directly protrude out as welding pins for assembly of lower-level modules, reducing the stress when the pins are bent, avoiding damage to the plastic package, and improving product quality.
  • the Z-shaped pin is unstable in the wire welding process, the pin welding position is suspended, the welding force during welding is unstable, and the welding is prone to poor welding, which affects the product yield, causes unstable production, and reduces Production output.
  • the pins are not bent and are extended and distributed on a plane. During the wire welding process, the pins are closely supported, and the welding force during welding is stable, resulting in poor welding and ensuring stable production. reliable quality.
  • the lead frame copper material used for the bent Z-shaped pins is more, and the utilization rate is not high.
  • the leads are not bent, and the copper material of the lead part formed by the original bending is subtracted, and the utilization rate of the lead frame copper material is increased by about 10%.
  • the base island and pins need to be stamped twice during the processing of the lead frame.
  • the coplanarity of the base island and the pins is greatly affected, and the processing difficulty increases. At the same time, the coplanarity will affect the product packaging. Yield and stability.
  • the base island and pins do not need to be punched twice during the processing of the lead frame, and the coplanarity of the base island and the pins will be maintained well, and the punching and etching processes can also be freely selected to process the lead frame , The processing complexity and difficulty are reduced.
  • the product arrangement density in the entire lead frame is not high, and at the same time, due to the long product pins, additional cross ribs are needed to support it, occupying the lead frame space and reducing the product arrangement density in the lead frame.
  • the packaging structure of the present invention the product pins are shortened, and the product arrangement density in the entire lead frame is increased by about 10%, which improves the output capacity of the production process based on the lead frame (such as plastic packaging, rib cutting, electroplating, etc.) ).
  • the traditional packaging structure has a large thickness and volume.
  • plastic packaging materials are used frequently.
  • the use of plastic packaging material is greatly reduced, about 50% of the original, and the cost of the plastic packaging material of the product is reduced.
  • the traditional packaging structure has fewer output pins, large base islands but low utilization rate, but it is only suitable for single chip, single base island packaged products, and the products are lower end.
  • the packaging structure of the present invention has many product output pins, and can be designed to arrange dual-base islands and multi-base islands to improve the utilization rate of base islands. It is used for packaging multi-chip packaged products and meets high-end complex products with high integration, such as CPU processors. Chip packaging.
  • the packaging structure of the present invention is also greatly optimized in terms of implementation conditions including equipment, process, materials, or other conditions.
  • the lead frame In the traditional packaging structure, the lead frame must have a base island as a support platform for the chip, and the pins are long. The base island and the pins need to be punched into a convex shape twice to provide conditions for mounting and soldering in the package.
  • the packaging structure of the present invention uses a special design of the lead frame: the design is simplified, the leads are shortened, the density is high, the leads are arranged around, and the base island and the leads do not need to be punched into a convex shape twice.
  • the traditional packaging structure uses traditional plastic packaging, using upper and lower molded products, and the base island and pins are not exposed.
  • the packaging structure of the present invention uses a semi-mold encapsulation, that is, the bottom surface of the base island and the pins are exposed outside the plastic encapsulation body; for the plastic encapsulation mold, the chip, the lead frame, and the metal wire can be plastic-encapsulated together for protection ,
  • the base island and the pins are on the same plane, one side is sealed by the plastic compound, and the other side is directly exposed, so there is no need to use the lower mold.
  • the packaging structure of the present invention can design a corresponding mold, use the anti-overflow glue boss between the pins, and press the lead frame pins tightly through the upper mold, and can directly plasticize without filming on the back of the lead frame Compared with traditional packaging processes such as QFN and DFN, this invention simplifies the packaging process, saves the lead frame back filming process, reduces the packaging difficulty, and solves the problem of lead frame back Product quality problems arising from the filming process on the back of the frame, such as poor welding and plastic overflow, also save material, labor, and equipment costs, and shorten the overall processing time of the product.
  • the cutting rib forming process has the steps of bending the leads into a Z shape.
  • the packaging structure of the present invention can directly cut off the lead to separate the lead frame, and the lead extending out of the plastic package body does not need to be folded into a Z shape, which reduces the process steps.
  • the lead frame base islands and pins can use T-shaped or inverted T-shaped structures to increase the locking and bonding force between the base islands and the pins, and the semi-plastic package and semi-exposed design of the base islands and pins can achieve high reliability. .
  • the packaging of the product with the special packaging structure of the present invention can be realized.
  • the packaging structure of the present invention has wide applicability.
  • Packaged products in which the pins of SOT, SOP, LQFP, etc. are folded into a Z shape can be converted to the package structure of the present invention.
  • the package structure of the present invention is suitable for the following parameters: plastic package size range: 0.6x0.8mm---8x8mm; pin number: 1---64 (single side); single base island or multiple bases Island, exposed base island or non-exposed base island, different base island shapes; double-sided or four-sided extension pins, including strip, T-shaped, internal convex and other different pin shapes;
  • the lead frame used is not limited to copper
  • the lead frame other metal material lead frames can also be used.
  • the thickness of the lead and base island of the package structure is 0.1mm---0.5mm.
  • the package structure of the present invention can reduce the internal resistance of the package by 10%-50%, reduce the thermal resistance of the package by 20%-60%, and improve the frequency characteristic.
  • the packaging structure of the present invention can be changed from corrosion process to mechanical processing, avoiding chemical processing, thus reducing electroplating procedures and effectively reducing the impact on the environment.
  • product separation can be changed from grinding in a deionized water environment to mechanical processing, avoiding the production of deionized water.
  • the base island and pins are installed on the bottom surface of the packaging structure body, so that the difficulty of the chip mounting and bonding process is reduced, and the bottom surface adopts punching processing, which can be automated production, and the difficulty is reduced, and the product layering is reliable
  • punching processing which can be automated production
  • the difficulty is reduced, and the product layering is reliable
  • the performance risk is reduced, and it is more suitable for automated AUTO (automatic) mold injection and automated test taping, which can effectively improve production efficiency.
  • the method may include the following steps:
  • the integrated circuit in step 92, can be fixed to the base island through a die bonding or reflow process, and can be connected to the pin through a metal wire.
  • the corresponding mold can be used to assist the molding, including: pressing the lead frame pins by the upper mold, and setting the anti-overflow glue boss between the pins, and then directly plasticizing, which is not in the lead Film on the back of the frame. Through this process, the problem of glue overflow on the back of the lead frame can be avoided.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Packages (AREA)

Abstract

一种高密度多侧面引脚外露的封装结构及其生产方法,封装结构包括本体(10),基岛(20)和引脚(30);所述基岛(20)和所述引脚(30)设于所述本体(10)的底部,且所述引脚(30)的底面裸露于所述本体(10)的底面,且所述引脚(30)向所述本体(10)的多个侧面延伸并伸出所述本体(10)之外;所述本体(10)包括设于所述基岛(20)并与所述引脚(30)连接的集成电路(11),以及用于封装所述集成电路(11)、所述基岛(20)和所述引脚(30)的塑封体(12);所述塑封体(12)的底面和所述引脚(30)的底面,处于同一水平面;所述引脚(30)包括与所述基岛(20)隔离的第一引脚(31)。可减小封装结构的厚度、体积,减少封装内阻和热阻,提高产品性能及其可靠性,同时增大了应用范围。

Description

高密度多侧面引脚外露的封装结构及其生产方法 技术领域
本发明涉及芯片封装技术领域,具体涉及一种高密度多侧面引脚外露的封装结构及其生产方法。
背景技术
半导体集成电路是现代技术的核心,是智能化产品的大脑,也是现代科学技术发展的基础;另外它还是人类现代文明的基础,从根本上改变人们生活方式的现代文明,如人工智能、物联网、互联网、电脑、电视、冰箱、手机、各种自动控制设备等等都依赖集成电路来实现其智能化功能。集成电路的制造分设计、芯片制造、封装、测试几个主要部分,封装是其中关键环节,建立在封装技术上的封装形式是为满足各种用途对集成电路的性能、体积、可靠性、形状和成本的特殊要求而研制的。
集成电路封装技术包括:1、工艺过程及技术,通过使用能够保证单晶材料完美晶格结构的研磨、切割技术将集成电路圆片分离成符合要求的单一芯片,用导电胶或共晶等技术将芯片固定到引线框基岛上,用微细连接技术(微米级)将芯片和外引线脚连接起来,然后用高分子材料或陶瓷材料将芯片和引线等保护起来;2、封装结构研发,产品体积要求越来越小,电性能、热性能要求越来越高。
集成电路的封装类型可以概括为两大类:密封陶瓷封装以及塑料封装。密封陶瓷封装是利用真空密封装置将芯片与环绕的包围物隔离的方式封装,典型的密封陶瓷封装应用于高效能的封装等级。而塑料封装则是利用环氧树脂将芯片封装,塑料封装技术在其应用和功效上得到了显著的发展,完全能够满足工业、民用产品需求,材料成本低且塑料封装的生产工艺能够进行自动化生产,从而有效地降低了成本,目前工业、民用产品主要采用塑料封装。
现在集成电路的封装形式多种。其中QFN(Quad Flat No-leadPackage,方形扁平无引脚封装)、DFN(Dual Flat No-leadPackage,两边扁平无引脚封装)是为满足高速度、大容量、低功耗,以及便携式终端产品的需求而研发的,它的特点是在同等体积里可以容纳更强大功能的芯片,而且耗电耗热小、频率特 性好、材料用量少,但封装工艺复杂,如,引线框需要用腐蚀工艺制作,质量难以控制、污染环境、效率低、成本昂贵;背面需要贴膜,键合效率下降30%以上,劈刀损耗2倍以上;分离采用切割方式效率低、设备昂贵、品质不易控制,而且整机企业使用时工艺控制难度大,效率低。由于现代产品尤其是计算机、手机、IPAD、其它便携式设备对功能及体积的要求,这两个系列的产品是在目前中高端封装产品中占绝对多数的封装结构。
集成电路的封装形式对集成电路产品的性能(电、热性能)、可靠性、成本具有重大影响。随着芯片制造技术从微米向纳米级发展,单位面积芯片功能每18个月翻番的摩尔定律在逐渐失效,未来功能强大的云计算、互联网中的物联网和移动网等等必须依赖其核心技术集成电路的突破,集成电路在大容量、高速度、低功耗方面的提高,在芯片制造上将变得越来越难,更大程度上需要封装形式及技术的突破。为了适应这种需求现在人们普遍采用的是DFN、QFN、BGA(Ball Grid Array,焊球阵列封装)等高端封装结构,但其制造工艺复杂、对环境影响大、设备投资昂贵、品质控制难、成本高。
总之,随着芯片尺寸的缩小对内阻、散热的要求越来越高,而且传统封装芯片越小,内阻越大、散热越差;尤其是移动互联网产品对集成电路产品结构非常严苛,要求体积和内阻、散热的矛盾体同时达到最优。
发明内容
本发明提供一种高密度多侧面引脚外露的封装结构及其生产方法,旨在减小封装结构的厚度、体积,减少封装内阻和热阻,和/或提升引脚/基岛的塑封稳定性、和/或键合/焊接的质量,提高产品性能及其可靠性。
一种高密度多侧面引脚外露的封装结构,
包括本体,基岛和引脚;
所述基岛和所述引脚设于所述本体的底部,且所述引脚的底面裸露于所述本体的底面,且所述引脚向所述本体的多个侧面延伸并伸出所述本体之外;
所述本体包括设于所述基岛并与所述引脚连接的集成电路,以及用于封装所述集成电路、所述基岛和所述引脚的塑封体;
所述塑封体的底面和所述引脚的底面,处于同一水平面;
所述引脚包括与所述基岛隔离的第一引脚。
优选地,所述基岛裸露于所述本体的底面,所述基岛的底面和所述塑封体的底面处于同一水平面。
优选地,所述本体具有四个侧面,多个所述引脚分别向所述本体的相对的二个侧面或四个侧面延伸,并伸出所述本体之外。
优选地,所述第一引脚包括一在水平面上延伸的平直部,该平直部的一端伸出所述本体。
优选地,所述第一引脚还包括一在水平面上延伸的转折部,该转折部与所述平直部的位于所述本体内的另一端连接,且该转折部位于所述本体内,所述转折部包括一倾斜段和一平行段,所述平行段与所述平直部彼此平行并通过所述倾斜段连接;
所述转折部与所述平直部满足如下关系:
L1=L2×cosθ+L3;
其中,L1是所述平直部的长度,L2是所述倾斜段的长度,L3是所述平行段的长度,θ是所述倾斜段与所述平直部的夹角。
优选地,所述第一引脚位于所述本体内的一端具有面向所述基岛的第一端面,所述基岛具有面向所述第一端面的第二端面;所述第一端面上设有第一凹槽,和/或,所述第二端面上设有第二凹槽。
优选地,所述第一引脚位于所述本体内的一端的上表面具有第三凹槽,和/或,所述基岛的靠近所述第一引脚的一侧的上表面具有第四凹槽。
优选地,所述第一引脚位于所述本体内的一端的上表面设有T型凸台,所述T型凸台包括连接于所述第一引脚的上表面的凸台支撑台和设于凸台支撑台顶部的凸台焊接台,且凸台焊接台的宽度大于凸台支撑台的宽度。
优选地,所述T型凸台的高度A与所述第一引脚的高度C满足以下公式:
1/2(A+C)<A<√2/2(A+C)。
一种前述的高密度多侧面引脚外露的封装结构的生产方法,其特征在于,包括以下步骤:
将金属引线框冲切形成基岛和引脚,所述引脚包括与所述基岛隔离的第一引脚;
将集成电路与所述基岛和所述引脚连接;
对所述集成电路、所述基岛和所述引脚进行塑封,得到封装结构本体,其 中,所述基岛和所述引脚设于所述本体的底部,且所述引脚的底面裸露于所述本体的底面,且所述引脚向所述本体的多个侧面延伸并伸出所述本体之外,且所述塑封体的底面和所述引脚的底面,处于同一水平面;
对封装结构本体进行冲切分离。
本发明包括但不限于以下有益效果:
本发明的封装结构,其基岛和引脚设于本体的底部,且引脚裸露于本体底面,且引脚自多侧侧面伸出本体之外,且基岛可以裸露于本体底面;使得:整个封装结构的厚度、体积进一步减小;进一步减小了封装内阻和热阻,具有更好的散热性能,并可改善产品频率特性;且提高了引脚密度,适用性增强;且平面构件的引脚,具有更高的强度和焊接受力稳定性,确保产品性能更可靠;整个封装结构体积缩小,用料减少,进一步降低产品成本;封装结构整体的共面性更好,可采用冲切工艺加工,加工复杂度和难度进一步降低;提升引脚/基岛的塑封稳定性、和/或键合/焊接的质量。
附图说明
为了更清楚地说明本发明实施例技术方案,下面将对实施例和现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其它的附图。
图1-1是本发明一个实施例提供的一种高密度多侧面引脚外露的封装结构的结构示意图;
图1-2是本发明一个实施例提供的一种高密度多侧面引脚外露的封装结构的剖视图;
图2-1是本发明另一个实施例提供的一种高密度多侧面引脚外露的封装结构的结构示意图;
图2-2是本发明另一个实施例提供的一种高密度多侧面引脚外露的封装结构的底面示意图;
图2-3是本发明另一个实施例提供的一种高密度多侧面引脚外露的封装结构的引脚结构示意图;
图3是本发明又一个实施例提供的一种高密度多侧面引脚外露的封装结构 的剖视图;
图4-1是本发明实施例中一种塑封锁紧槽的示意图;
图4-2是本发明实施例中另一种塑封锁紧槽的示意图;
图4-3是本发明实施例中又一种塑封锁紧槽的示意图;
图4-4是本发明一个实施例包含凸台的封装结构示意图;
图4-5是本发明一个实施例包含凸台的封装结构细节结构示意图;
图4-6是本发明一个实施例中凸台的结构尺寸示意图;
图5-1是本发明一个实施例包含单基岛的封装结构的示意图;
图5-2是本发明一个实施例包含双基岛的封装结构的示意图;
图5-3是本发明一个实施例包含三基岛的封装结构的示意图;
图6是一种传统的封装结构的示意图;
图7-1是本发明一个实施例外露基岛的封装结构的示意图;
图7-2是本发明一个实施例不露基岛的封装结构的示意图;
图8-1是本发明一个实施例四侧露出对称引脚的封装结构的示意图;
图8-2是本发明一个实施例两侧露出对称引脚的封装结构的示意图;
图8-3是本发明一个实施例四侧露不对称引脚的封装结构的示意图;
图9-1是本发明一个实施例中四侧露出T字形引脚的封装结构的示意图;
图9-2是本发明一个实施例中采用上凸引脚的封装结构的示意图;
图10是本发明一个实施例提供的一种封装结构的生产方法的流程图。
具体实施方式
为了使本技术领域的人员更好地理解本发明方案,下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分的实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都应当属于本发明保护的范围。
在本发明的描述中,需要理解的是,术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系,仅是为了便于描述本发明和简化描述,而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作,因此不 能理解为对本发明的限制。
此外,术语“第一”、“第二”、“第三”等是用于区别不同的对象,而不是用于描述特定顺序。此外,术语“包括”和“具有”以及它们任何变形,意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备没有限定于已列出的步骤或单元,而是可选地还包括没有列出的步骤或单元,或可选地还包括对于这些过程、方法、产品或设备固有的其它步骤或单元。
下面通过具体实施例,分别进行详细的说明。
请参考图1-1至1-2和图2-1至2-1,本发明实施例提供给一种高密度多侧面引脚外露的封装结构,包括本体10和引线框,其引线框包括基岛20和引脚30,其本体10包括集成电路11和塑封体12,本体10还可以包括金属丝13和焊接料14。
所述基岛20和所述引脚30设于所述本体10的底部,且所述引脚30的底面裸露于所述本体10的底面,且所述引脚30向所述本体10的多个侧面延伸并伸出所述本体10之外;所述集成电路11设于所述基岛20并与所述引脚30连接,所述塑封体12用于封装所述集成电路11、所述基岛20和所述引脚30。所述金属丝13用于连接所述集成电路11与所述引脚30,所述焊接料14用于连接所述集成电路11与所述基岛20。
其中,所述引脚30可采用平面构件,即,仅在水平面上延伸;当然,一些实施例中,也可以采用非平面构件。可以是所述引脚30的整个底面全部裸露于本地10的底面,也可以是所述引脚30的部分底面裸露于本地10的底面。
其中,所述基岛20可裸露于所述本体10的底面,或者,所述基岛20也可以不露出而是全部位于本体10的内部。
其中,所述塑封体12的底面,和/或所述基岛20的底面,和/或所述引脚30的底面,可处于同一水平面。
其中,所述本体10可以是正方形或长方形,可具有四个侧面。多个所述引脚30可分别向所述本体10的相对的二个侧面或四个侧面延伸,并伸出所述本体10之外;相对的两侧的引脚30可以相对称,也可以不对称。可选的,为了增加引脚数量,提高封装密度,优选向四个侧面延伸,即,本体10的四个侧面均伸出引脚30。
其中,所述基岛20和引脚30可采用金属材质,具体可采用铜合金;所述塑封体12可采用塑胶材料。
如图2-1和图2-2所示,本发明的一个实施例中,所述引脚30可包括与所述基岛20隔离的第一引脚31,所述第一引脚31可包括一在水平面上延伸的平直部311,该平直部311的一端伸出所述本体10之外,平直部311的底面裸露于本体10的底面。可选的,所示引脚30还可包括与基岛20相连接的第二引脚32。
如图2-2所示,本发明的一个实施例中,所述第一引脚31还可以包括一在水平面上延伸的转折部312,该转折部312与所述平直部311的位于所述本体10内的另一端连接,且该转折部312位于所述本体10内。该转折部312用于增强第一引脚30与塑封体12的连接力度。可选的,该转折部312可以是一与平直部311垂直的部件。可选的,该转折部312也可以依次包括一与平直部311连接的倾斜段以及与倾斜段连接的平行段。可选的,该转折部312还可以采用其它各种形状。
如图2-3所示,本发明的一个实施例中,
所述转折部包括一倾斜段312b和一平行段312a,所述平行段312a与所述平直部311彼此平行并通过所述倾斜段312b连接;
所述转折部312与所述平直部311满足如下关系:
L1=L2×cosθ+L3;
其中,L1是所述平直部311的长度,L2是所述倾斜段312b的长度,L3是所述平行段312a的长度,θ是所述倾斜段312b与所述平直部311的夹角。
进一步的,还满足:L3=L2;
进一步的,所述平直部311的位于所述本体10内部的长度与位于所述本体10外部的长度之比在2:3到2:5之间,优选为1:2。
如上,通过采用如上限定的转折部312,使得整个第一引脚31满足极佳的应力关系,不易变形;且与本体10的结合更好,具有极佳的牢固性。其中,平行段312a可被用来连接金属丝13,实现与集成电路11连接,通过采用上述限定,使得平行段312a具有大小合适的焊接面积和导热性能,焊接受力稳定,有助于提高焊接质量。
如图1-2所示,本发明一些实施例中,所述集成电路11可用焊接料14通过固晶或者回流焊工艺固定于所述基岛20的正面,并通过金属丝(线)13与所述引脚30相连接。所述焊接料14例如可以是回流焊工艺中设置的锡膏。
如图3所示,本发明的一个实施例中,所述第一引脚31的位于所述本体10内的一端具有面向所述基岛20的第一端面33,所述基岛20具有面向所述第一端面 33的第二端面21;所述第一端面33上设有第一凹槽34,和/或,所述第二端面21上设有第二凹槽22。
如图4-1所示,第一凹槽34和第二凹槽22可以设在靠近本体10底面一侧,从而,第一端面33和第二端面21之间可以形成T字形的塑封锁紧槽40。塑封锁紧槽40有助于将基岛20和引脚30牢牢的固定在塑封体12内。
如图4-2所示,第一凹槽34和第二凹槽22也可以设在远离本体10底面的一侧,从而,第一端面33和第二端面21之间可以形成倒T字形的塑封锁紧槽40。
如图4-3所示,一实施例中,所述第一引脚31的位于所述本体10内的一端(端部)的上表面还可以具有第三凹槽35,和/或,所述基岛20的靠近所述第一引脚31的一侧的上表面还可以具有第四凹槽23。利用第三凹槽35和/或第四凹槽23,可形成沟槽性型塑封锁紧槽,可进一步将基岛20和引脚30牢牢的固定在塑封体12内。
如图4-4所示,本发明的一个实施例中,所述第一引脚31的位于所述本体10内的一端(端部)的上表面还可以设有凸台36。具体来说,所述第一引脚31包括一平直部311,该平直部311的位于所述本体10内的一端的上表面设有凸台36;或者,所述第一引脚31还包括连接于平直部311的转折部312,所述转折部312的靠近集成电路11的一端的上表面设有凸台36。该凸台36一方面用来焊接金属丝13,实现与集成电路11连接;另一方面作为凸起部插入本体10内部,与塑封体12良好结合,将第一引脚31牢牢的固定在本体10内。
如图4-5所示,进一步的,所述凸台36可为T型凸台,包括凸台支撑台362和凸台焊接台361,凸台支撑台362连接于第一引脚31的上表面,凸台焊接台361设于凸台支撑台362的顶部,且凸台焊接台361的宽度大于凸台支撑台362的宽度使凸台36的截面呈T型。凸台焊接台361上表面为焊接面(凸台焊接面),用来焊接金属丝13。可选的,凸台焊接台361为柱体例如圆柱体,凸台支撑台362也为主体例如圆柱体,且两者可为同轴的圆柱体,且凸台焊接台361的直径大于凸台支撑台362的直径。T型凸台上大下小,可牢牢的固定在塑封体12内。
如图4-6所示,进一步的,上述T型凸台结构设计满足以下特性:
1.假设引脚和基岛的厚度均为C。T型凸台由凸台支撑台和凸台焊接台构成,总高度为A,且凸台支撑台362高度为B,凸台焊接台361高度为H,凸台支撑台362直径为E,凸台焊接台361直径为D。T型凸台的高度要要满足一定要求,凸 台过高,会出现金属丝第二焊点焊接受力不稳定,影响焊接质量,凸台过低,凸台结构的优点效果难以体现,加工制造也很困难,通过理论计算和实验验证得出,当凸台的高度满足与引脚高度一定比例后,凸台稳定性(焊接台焊接受力稳定性)好,同时凸台结构的优点效果很明显。
可选的,T型凸台的高度A与引脚(基岛)的高度C满足以下公式:
Figure PCTCN2020071108-appb-000001
优选的,
Figure PCTCN2020071108-appb-000002
即,A=0.618*(A+C)
也就是说,T型凸台的高度设计为凸台+引脚整体厚度的50%-71%之间,T型凸台的最佳高度为凸台+引脚整体厚度的黄金比例。
进一步的,T型凸台还满足以下公式:
A=B+H,
B=H=Ax1/2,
E<D<2E,
进一步的,凸台焊接台直径D为金属丝直径的100---300倍,或者说,凸台焊接台的直径D与金属丝的直径之比在100:1到300:1之间,以实现良好的焊接性能。
以上,对如图4-4至图4-6所示的凸台36的结构进行了说明。
该种设有凸台36、尤其是T型凸台的特殊引脚结构,可实现如下技术效果:
1.T型凸台结构设计,即可作为焊接焊盘使用,又可以起到锁紧塑封体、将引脚固定在塑封体内的作用。
2.T型凸台结构设计,只需要要在凸台上表面的焊接面进行镀银,减少了镀银材料,节约了成本。
3.T型凸台结构设计,减少了集成电路与引脚之间的高度差,降低了键合金属丝的弧高,减缓第一焊点(位于集成电路上的焊点)的金属丝弧形角度,利于键合弧高控制,降低键合金属丝的第一焊点因弧形过大造成的颈部损伤问题,提高了键合的质量。
4.T型凸台结构设计相比如图6所示的传统的Z性悬空设计机构,稳定性更好,键合受力更稳定,更利于键合金属丝与引脚的第二焊点(位于引脚的凸台 焊接面上的焊点)焊接,提高了第二焊点焊接质量。
5.T型凸台结构设计结构依据引线框的厚度、芯片的厚度及焊合金属丝的直径来设计,一次来保证最佳的封装结构效果。
需要说明的是,对于一些特殊要求的产品,T型凸台结构的设计可以有对应的调整,也属于本发明的范畴。
本发明实施例的封装结构,可根据不同产品的需求(功能复杂程度),设计不同数目、形状的基岛,以此来满足相关要求,即,不限定其中基岛20的数量和形状。如图5-1所示,本体10内可封装一个基岛20;如图5-2所示,本体10内也可封装两个基岛20;如图5-3所示,本体10内还可封装三个基岛20;根据需要,本体10内还可以封装更多个基岛20。
本发明实施例的封装结构,可根据不同产品的需求,决定基岛20外露或不外露。如图7-1所示,基岛20可裸露于本体10的底面;或者,如图7-2所示,基岛20也可以不裸露,而是位于本体10内部。
本发明实施例的封装结构,可根据不同产品的需求,决定引脚30的分布,引脚30可以分布于本体10的两侧或四侧,其相对的两侧的引脚30可以相对称,也可以不对称。如图8-1所示,引脚30可分布于本体10的四侧,且相对的两侧的引脚30相对称;如图8-2所示,引脚30可分布于本体10的两侧,且相对称;如图8-3所示,引脚30可分布于本体10的四侧,且相对的两侧的引脚30不对称。
本发明实施例的封装结构,其引脚30可采用各种不同的形状,如长条形、T字形或其它形状。如图8-1至8-3所示,引脚30可以是平直的长条形引脚。如图9-1所示,引脚30可以是T字形引脚,即,在一平直部311上垂直连接一转折部312。如图9-2所示,引脚30也可以采用内部上凸引脚(内凸引脚),即,引脚30可包括一平直部311,平直部311可连接一上凸部313,该种形式的引脚30可以更好与本体10结合,更牢固。其中,如图8-1至图8-3和图9-1所示的引脚30为平面构件,如图9-2所示的引脚30为非平面构件。
本发明的封装结构相对于现有技术有多项技术改进:
请参考图6,是一种传统的芯片封装结构。从图中可以看出,其基岛61位于塑封体60的中央位置,被塑封体完全密封;其引脚63在竖直面上弯折为Z字形,包括位于塑封体内部的第一部分631,与第一部分631连接的向下弯折的第二部分632,以及与第二部分连接的水平伸展的第三部分633。
传统的封装结构,具有尺寸大,产品厚,体积大,下级小空间装配有限制等缺陷。而本发明的封装结构,由于基岛和引脚设于本体的底部,且可以采用平面构件,竖直尺寸极小,使得整个产品很薄,厚度约缩小约1/2,整个产品体积缩小到约40%,适合更小空间装配,可满足高集成、小体积的下级装配要求,如高端系统级封装模块的组装。
传统的封装结构,基岛在内部,没有外露,散热性一般,无法满足高散热要求的产品,产品适用范围有限。而本发明的封装结构,基岛外露,散热性更好,可适用于散热要求高的产品,适用性更广(如LED功率模块,5G通信电源模块,电机驱动模块等),当然,也可灵活选择基岛外露或不外露。
传统的封装结构,引脚相对的分布在产品两侧,两侧空间有限,使引脚数目少。而本发明的封装结构,引脚相对的可分布在产品多侧,例如四侧,充分利用了产品的四侧空间,在产品体积不变的条件下,使引脚数目大幅度增加,是传统封装结构的2倍,满足了更复杂产品的多输出端口,实现高集成化、复杂化和小型化,适用性增强。
传统的封装结构,引脚需要拗折成Z形,引脚成形时受外部机械力,容易出现产品引脚变形、塑封体受损。而本发明的封装结构,引脚不需要成Z形,直接外露伸出作为下级模块组装的焊接引脚,减小引脚拗折时的应力,避免塑封体受损,提高产品的质量。
传统的封装结构,Z形引脚在金属丝焊接工艺中不稳定,引脚焊接位置悬空,焊接时的焊接受力不稳,容易出现焊接不良,影响产品良率,造成生产不稳定,降低了生产产量。而本发明的封装结构,引脚不拗折,为平面上延伸分布的结构,在金属丝焊接工艺中引脚被贴紧支撑,焊接时的焊接受力稳定,使焊接不良,保证生产稳定和质量可靠。
传统的封装结构,拗折的Z形引脚使用的引线框铜材更多,使用率不高。而本发明的封装结构,引脚不拗折,减去了原来拗折成形的引脚部分铜材,提高了引线框铜材的利用率大约10%。
传统的封装结构,引线框在加工过程中基岛、引脚需要二次冲压成型,基岛、引脚的共面性受影响大,加工难度增加,同时其共面性会影响产品封装时的良率和稳定性。而本发明的封装结构,引线框在加工过程中基岛、引脚不需要二次冲压,基岛、引脚的共面性会保持很好,也可自由选择冲压、蚀刻工艺 来加工引线框,加工复杂度和难度都降低。
传统的封装结构,整条引线框中的产品排布密度不高,同时由于产品引脚长,需要额外的横筋来支撑,占用引线框空间,降低了产品在引线框中的排列密度。而本发明的封装结构,产品引脚缩短,整条引线框中的产品排布密度提高约10%,提升了以引线框为单位的生产工艺的输出产能(如塑封、切筋、电镀等工艺)。
传统的封装结构,厚度、体积大,为形成塑封体,塑封料使用多。而本发明的封装结构,为形成塑封体,塑封料使用大幅减少,约为原来的50%,降低了产品的塑封料成本。
传统的封装结构,产品输出引脚少,基岛大但利用率低,但只适用于单芯片,单基岛的封装产品,产品较低端。而本发明的封装结构,产品输出引脚多,可设计排列双基岛、多基岛,提高基岛利用率,用于封装多芯片封装产品,满足高集成的高端复杂产品,如CPU处理器芯片的封装。
本发明的封装结构,相对于传统的封装结构,在实现条件包括设备、工艺、材料或其他条件上,也有较大优化。
传统的封装结构,引线框必须有基岛作为芯片的支撑台,引脚长,基岛和引脚需要二次冲压成凸起形状,为封装中的装片、焊接提供条件。而本发明的封装结构,使用引线框特殊设计:设计简化,引脚缩短,高密度,引脚四周排布,基岛和引脚不需要二次冲压成凸起形状。
传统的封装结构,使用传统的塑封,采用上下模塑封产品,被塑封的基岛和引脚都不外露。而本发明的封装结构,使用半模塑封,即,基岛和引脚的底面裸露于塑封体之外;则对塑封模具,可只用上模将芯片、引线框、金属丝塑封在一起保护,基岛、引脚在同一平面,一面被塑封料塑封,另一面直接外露,不需要使用下模。
传统的QFN、DFN等塑封模式,在引线框背部贴膜(前贴膜或后贴膜)是一个必不可少的工艺,用来保证塑封时塑封料不会在引线框的背部溢胶。而本发明的封装结构,可设计对应的模具,使用引脚间的防溢胶凸台,通过上模将引线框引脚压紧,在不需要在引线框背部贴膜的情况下,直接可以塑封产品,而引线框背部不会出现溢胶的问题,相比传统的QFN、DFN等封装工艺,该发明简化了封装工艺,省去了引线框背部贴膜工艺,降低了封装难度,解决了因 引线框背部贴膜工艺出现的产品质量问题,如焊接不良、塑封溢料等问题,同时也节约了材料、人工、设备成本,缩短了产品的整体加工时间。
传统的封装结构,切筋成形工艺有引脚拗折成Z形的步骤。而本发明的封装结构,可直接切断引脚分离引线框,伸出塑封体外的引脚不需要拗折成Z形,减少了工艺步骤。
传统的封装结构,必须使用塑封料全包裹的形式。而本发明的封装结构,引线框基岛、引脚可使用T形或倒T形结构,增加其与塑封料的锁紧结合力,使基岛和引脚半塑封半裸露设计实现高可靠性。
如上,通过将特殊引线框设计、塑封模具设计、塑封锁紧设计、切筋工艺设计结合在一起,可以实现本发明特殊的封装结构产品的封装。
本发明的封装结构,适用性广。SOT、SOP、LQFP等引脚拗折成Z形的封装产品,可转为采用本发明的封装结构。优选的,本发明的封装结构,适用于以下参数:塑封体尺寸范围:0.6x0.8mm---8x8mm;引脚数量:1只---64只(单侧);单基岛或多基岛、露基岛或不露基岛,不同基岛形状;双侧或四侧外伸引脚,包括条形、T形、内部上凸等不同引脚形状;使用的引线框不仅限于铜材引线框,也可使用其它金属材质引线框,该封装结构的引脚、基岛厚度为0.1mm---0.5mm。
本发明的封装结构,可以使得封装内阻减小10%~50%,封装热阻减小20%~60%,频率特性改善。
本发明的封装结构,相比QFN、DFN产品金属结构包括基岛和引脚可以由腐蚀工艺改为机械加工,避免化学加工过程,因此可减少电镀工序,并能够有效的减少对环境的影响。
本发明的封装结构,产品分离可以由去离子水环境下研磨改为机械加工,避免去离子水的生产。
本发明的封装结构,将基岛和引脚装设于封装结构本体底面,使得装片键合工艺难度下降,而底面采用冲切加工,可以采用自动化生产,且难度下降,产品分层等可靠性风险下降,更适合于自动化的AUTO(自动)模注塑及自动化的测试编带,能够有效提高生产效率。
请参考图10,本发明一些实施例中,还提供一种用于生产如上文所述的高密度多侧面引脚外露的封装结构的生产方法,该方法可包括以下步骤:
91、将金属引线框冲切形成基岛和引脚,所述引脚包括与所述基岛隔离的 第一引脚,所述基岛和所述引脚均可以为平面构件;
92、将集成电路与所述基岛和所述引脚连接;
93、对所述集成电路、所述基岛和所述引脚进行塑封,得到封装结构本体,其中,所述基岛和所述引脚设于所述本体的底部,且可以裸露于所述本体的底面,且所述引脚向所述本体的多个侧面延伸并伸出所述本体之外,且所述塑封体的底面和所述引脚的底面,处于同一水平面;
94、对封装结构本体进行冲切分离。例如,对封装结构本体底面进行冲切分离,得到需要的封装结构。
其中,步骤92中,可通过固晶或者回流焊工艺将集成电路固定于基岛,并可通过金属丝连接于引脚。
其中,步骤93的塑封步骤中,可使用对应的模具辅助塑封,包括:通过上模将引线框引脚压紧,并在引脚间设置防溢胶凸台,然后直接塑封,其中,不在引线框背部进行贴膜。通过该种工艺,可避免引线框背部出现溢胶问题。
在上述实施例中,对各个实施例的描述都各有侧重,某个实施例中没有详细描述的部分,可以参见其它实施例的相关描述。
上述实施例仅用以说明本发明的技术方案,而非对其限制;本领域的普通技术人员应当理解:其依然可以对上述各实施例所记载的技术方案进行修改,或者对其中部分技术特征进行等同替换;而这些修改或者替换,并不使相应技术方案的本质脱离本发明各实施例技术方案的精神和范围。

Claims (10)

  1. 一种高密度多侧面引脚外露的封装结构,其特征在于,
    包括本体,基岛和引脚;
    所述基岛和所述引脚设于所述本体的底部,且所述引脚的底面裸露于所述本体的底面,且所述引脚向所述本体的多个侧面延伸并伸出所述本体之外;
    所述本体包括设于所述基岛并与所述引脚连接的集成电路,以及用于封装所述集成电路、所述基岛和所述引脚的塑封体;
    所述塑封体的底面和所述引脚的底面,处于同一水平面;
    所述引脚包括与所述基岛隔离的第一引脚。
  2. 根据权利要求1所述的封装结构,其特征在于,
    所述基岛裸露于所述本体的底面,所述基岛的底面和所述塑封体的底面处于同一水平面。
  3. 根据权利要求1所述的封装结构,其特征在于,
    所述本体具有四个侧面,多个所述引脚分别向所述本体的相对的二个侧面或四个侧面延伸,并伸出所述本体之外。
  4. 根据权利要求1所述的封装结构,其特征在于,
    所述第一引脚包括一在水平面上延伸的平直部,该平直部的一端伸出所述本体。
  5. 根据权利要求4所述的封装结构,其特征在于,
    所述第一引脚还包括一在水平面上延伸的转折部,该转折部与所述平直部的位于所述本体内的另一端连接,且该转折部位于所述本体内,所述转折部包括一倾斜段和一平行段,所述平行段与所述平直部彼此平行并通过所述倾斜段连接;
    所述转折部与所述平直部满足如下关系:
    L1=L2×cosθ+L3;
    其中,L1是所述平直部的长度,L2是所述倾斜段的长度,L3是所述平行段的长度,θ是所述倾斜段与所述平直部的夹角。
  6. 根据权利要求1所述的封装结构,其特征在于,
    所述第一引脚位于所述本体内的一端具有面向所述基岛的第一端面,所述基岛具有面向所述第一端面的第二端面;所述第一端面上设有第一凹槽,和/或,所述第二端面上设有第二凹槽。
  7. 根据权利要求1所述的封装结构,其特征在于,
    所述第一引脚位于所述本体内的一端的上表面具有第三凹槽,和/或,所述基岛的靠近所述第一引脚的一侧的上表面具有第四凹槽。
  8. 根据权利要求1所述的封装结构,其特征在于,
    所述第一引脚位于所述本体内的一端的上表面设有T型凸台,所述T型凸台包括连接于所述第一引脚的上表面的凸台支撑台和设于凸台支撑台顶部的凸台焊接台,且凸台焊接台的宽度大于凸台支撑台的宽度。
  9. 根据权利要求8所述的封装结构,其特征在于,
    所述T型凸台的高度A与所述第一引脚的高度C满足以下公式:
    1/2(A+C)<A<√2/2(A+C)。
  10. 一种如权利要求1至9中任一项所述的高密度多侧面引脚外露的封装结构的生产方法,其特征在于,包括以下步骤:
    将金属引线框冲切形成基岛和引脚,所述引脚包括与所述基岛隔离的第一引脚;
    将集成电路与所述基岛和所述引脚连接;
    对所述集成电路、所述基岛和所述引脚进行塑封,得到封装结构本体,其中,所述基岛和所述引脚设于所述本体的底部,且所述引脚的底面裸露于所述本体的底面,且所述引脚向所述本体的多个侧面延伸并伸出所述本体之外,且所述塑封体的底面和所述引脚的底面,处于同一水平面;
    对封装结构本体进行冲切分离。
PCT/CN2020/071108 2019-07-19 2020-01-09 高密度多侧面引脚外露的封装结构及其生产方法 WO2021012641A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP20844301.0A EP4002446A4 (en) 2019-07-19 2020-01-09 HIGH DENSITY EXPOSED MULTIFACE PIN ENCAPSULATION STRUCTURE AND PRODUCTION METHOD THEREFOR
US17/256,602 US11088053B2 (en) 2019-07-19 2020-01-09 Encapsulation structure with high density, multiple sided and exposed leads and method for manufacturing the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910656493.7 2019-07-19
CN201910656493.7A CN110429075B (zh) 2019-07-19 2019-07-19 高密度多侧面引脚外露的封装结构及其生产方法

Publications (1)

Publication Number Publication Date
WO2021012641A1 true WO2021012641A1 (zh) 2021-01-28

Family

ID=68411282

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/071108 WO2021012641A1 (zh) 2019-07-19 2020-01-09 高密度多侧面引脚外露的封装结构及其生产方法

Country Status (4)

Country Link
US (1) US11088053B2 (zh)
EP (1) EP4002446A4 (zh)
CN (1) CN110429075B (zh)
WO (1) WO2021012641A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113363169A (zh) * 2021-06-28 2021-09-07 常州港华半导体科技有限公司 一种整流器外壳自动封装装置
CN114628268A (zh) * 2022-05-12 2022-06-14 广东气派科技有限公司 一种防超时的芯片产品腐球检验工艺

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110429075B (zh) * 2019-07-19 2020-07-14 广东气派科技有限公司 高密度多侧面引脚外露的封装结构及其生产方法
CN114378716B (zh) * 2021-12-13 2023-04-11 西安赛尔电子材料科技有限公司 多直径及多高度的引线端面的打磨方法
CN117012656B (zh) * 2023-09-20 2023-12-05 广东气派科技有限公司 高密度大矩阵sot89封装结构的制备方法

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080191324A1 (en) * 2007-02-08 2008-08-14 Chipmos Technologies (Bermuda) Ltd. Chip package structure and method of fabricating the same
CN101383293A (zh) * 2008-09-26 2009-03-11 凤凰半导体通信(苏州)有限公司 一种微型引线框架半导体封装方法
CN102810488A (zh) * 2011-05-31 2012-12-05 飞思卡尔半导体公司 半导体传感器装置及其封装方法
CN103606539A (zh) * 2013-10-31 2014-02-26 华天科技(西安)有限公司 一种基于框架采用开孔优化技术的扁平封装件及其制作工艺
CN205355046U (zh) * 2015-12-24 2016-06-29 江苏长电科技股份有限公司 一种框架外露多芯片多搭混装平铺夹芯封装结构
CN106611753A (zh) * 2015-10-26 2017-05-03 无锡华润矽科微电子有限公司 芯片封装框架及芯片封装结构
CN109817597A (zh) * 2017-11-21 2019-05-28 比亚迪股份有限公司 一种电池保护芯片封装结构
CN110429075A (zh) * 2019-07-19 2019-11-08 广东气派科技有限公司 高密度多侧面引脚外露的封装结构及其生产方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2570037B2 (ja) * 1990-12-03 1997-01-08 モトローラ・インコーポレイテッド 分離型ヒートシンク・ボンディングパッドを有する半導体パッケージ
TW200418149A (en) * 2003-03-11 2004-09-16 Siliconware Precision Industries Co Ltd Surface-mount-enhanced lead frame and method for fabricating semiconductor package with the same
US20100320592A1 (en) * 2006-12-29 2010-12-23 Sanyo Electric Co., Ltd. Semiconductor device and method for manufacturing the same
US9852966B2 (en) * 2011-09-30 2017-12-26 Mediatek Inc. Semiconductor package
US9673122B2 (en) * 2014-05-02 2017-06-06 Amkor Technology, Inc. Micro lead frame structure having reinforcing portions and method
US9564387B2 (en) * 2014-08-28 2017-02-07 UTAC Headquarters Pte. Ltd. Semiconductor package having routing traces therein
JP2017135230A (ja) * 2016-01-27 2017-08-03 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US9595455B1 (en) * 2016-06-09 2017-03-14 Nxp B.V. Integrated circuit module with filled contact gaps

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080191324A1 (en) * 2007-02-08 2008-08-14 Chipmos Technologies (Bermuda) Ltd. Chip package structure and method of fabricating the same
CN101383293A (zh) * 2008-09-26 2009-03-11 凤凰半导体通信(苏州)有限公司 一种微型引线框架半导体封装方法
CN102810488A (zh) * 2011-05-31 2012-12-05 飞思卡尔半导体公司 半导体传感器装置及其封装方法
CN103606539A (zh) * 2013-10-31 2014-02-26 华天科技(西安)有限公司 一种基于框架采用开孔优化技术的扁平封装件及其制作工艺
CN106611753A (zh) * 2015-10-26 2017-05-03 无锡华润矽科微电子有限公司 芯片封装框架及芯片封装结构
CN205355046U (zh) * 2015-12-24 2016-06-29 江苏长电科技股份有限公司 一种框架外露多芯片多搭混装平铺夹芯封装结构
CN109817597A (zh) * 2017-11-21 2019-05-28 比亚迪股份有限公司 一种电池保护芯片封装结构
CN110429075A (zh) * 2019-07-19 2019-11-08 广东气派科技有限公司 高密度多侧面引脚外露的封装结构及其生产方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113363169A (zh) * 2021-06-28 2021-09-07 常州港华半导体科技有限公司 一种整流器外壳自动封装装置
CN113363169B (zh) * 2021-06-28 2024-03-22 常州港华半导体科技有限公司 一种整流器外壳自动封装装置
CN114628268A (zh) * 2022-05-12 2022-06-14 广东气派科技有限公司 一种防超时的芯片产品腐球检验工艺
CN114628268B (zh) * 2022-05-12 2022-07-29 广东气派科技有限公司 一种防超时的芯片产品腐球检验工艺

Also Published As

Publication number Publication date
EP4002446A1 (en) 2022-05-25
US11088053B2 (en) 2021-08-10
CN110429075B (zh) 2020-07-14
EP4002446A4 (en) 2023-09-06
US20210183749A1 (en) 2021-06-17
CN110429075A (zh) 2019-11-08

Similar Documents

Publication Publication Date Title
WO2021012641A1 (zh) 高密度多侧面引脚外露的封装结构及其生产方法
US6621152B2 (en) Thin, small-sized power semiconductor package
TWI453838B (zh) 具有散熱器之無引線封裝
KR101208332B1 (ko) 반도체 패키지용 클립 구조 및 이를 이용한 반도체 패키지
TW201631722A (zh) 功率轉換電路的封裝模組及其製造方法
JP2003115573A (ja) デュアルダイパッケージ
CN116487362A (zh) 电子器件的封装结构及其制作方法
CN210224004U (zh) 一种射频器件
JP2017126733A (ja) 高密度集積回路パッケージ構造及び集積回路
JP3730469B2 (ja) 樹脂封止型半導体装置及びその製造方法
CN217655869U (zh) 半导体封装组件
CN220604667U (zh) 一种无框式大功率mos封装模块及电路结构
JP3132473B2 (ja) 半導体装置
CN212967685U (zh) 一种新型dfn封装结构
CN212182316U (zh) 一种无载体的半导体叠层封装结构
CN213583770U (zh) 半导体分立器件封装结构
CN216015357U (zh) 一种低内阻超薄型功率器件的封装结构
CN211295085U (zh) 一种多芯片串联封装结构
KR20050000972A (ko) 칩 스택 패키지
CN220984516U (zh) 一种功率器件封装结构
CN115939119B (zh) 功率模块和电子设备
CN115332234A (zh) 一种充分外露型双芯串联封装体、封装方法及pcb板
KR100370480B1 (ko) 반도체 패키지용 리드 프레임
CN116153886A (zh) 封装结构以及封装方法
JP3082562U (ja) マルチーチップパッケージ

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20844301

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 2020844301

Country of ref document: EP

Effective date: 20220221