CN103606539A - 一种基于框架采用开孔优化技术的扁平封装件及其制作工艺 - Google Patents

一种基于框架采用开孔优化技术的扁平封装件及其制作工艺 Download PDF

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CN103606539A
CN103606539A CN201310527641.8A CN201310527641A CN103606539A CN 103606539 A CN103606539 A CN 103606539A CN 201310527641 A CN201310527641 A CN 201310527641A CN 103606539 A CN103606539 A CN 103606539A
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魏海东
李万霞
石宏钰
谢建友
崔梦
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Huatian Technology Xian Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector

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Abstract

本发明公开了一种基于框架采用开孔优化技术的扁平封装件及其制作工艺，所述封装件主要由引线框架、粘片胶、芯片、键合线、上开孔、塑封体和下开孔组成；所述引线框架和芯片通过粘片胶连接，键合线从芯片连接到引线框架，所述引线框架上有上开孔和下开孔，塑封体包围了引线框架、粘片胶、芯片、键合线、上开孔和下开孔，芯片、键合线、引线框架构成了电路的电源和信号通道。所述封装件制作工艺的流程为：引线框架上开孔→晶圆减薄→划片→上芯→压焊→塑封→后固化→产品分离→检验→包装→入库。本发明使得集成电路框架与塑封体结合更加牢固，不受外界环境影响。

Description

一种基于框架采用开孔优化技术的扁平封装件及其制作工艺
技术领域
本发明属于集成电路封装技术领域，具体是一种基于框架采用开孔优化技术的扁平封装件及其制作工艺。 
背景技术
QFN（四面扁平无引脚封装）及DFN（双扁平无引脚封装）封装是在近几年随着通讯及便携式小型数码电子产品的产生(数码相机、手机、PC、MP3)而发展起来的、适用于高频、宽带、低噪声、高导热、小体积，高速度等电性要求的中小规模集成电路的封装。我们知道QFN/DFN封装有效地利用了引线脚的封装空间，从而大幅度地提高了封装效率。但目前大部分半导体封装厂商QFN/DFN的制造过程中都面临一些工艺困惑，原因是现有QFN/DFN工艺的塑封工序中，由于框架结构的局限性，使用的台阶状引线框架的防缺陷（分层）工艺措施也并非完全有效，导致QFN/DFN封装存在以下不足： 
1、框架的载体及引脚部分与塑封料的结合力不好，当受外界环境的影响，会造成产品产生缺陷(分层)；或外露载体（基岛）上有较厚的溢料，给后续去溢料带来困难，增加了产生分层缺陷的机率；
2、QFN、DFN系列扁平封装件使用的框架有较高的模具开发费用，致使成本增加，且台阶形状无法有效控制。
发明内容
为了克服上述现有技术存在的问题，本发明提供了一种基于框架采用开孔优化技术的扁平封装件及其制作工艺，使得集成电路框架与塑封体结合更加牢固，不受外界环境影响。 
一种基于框架采用开孔优化技术的扁平封装件主要由引线框架、粘片胶、芯片、键合线、上开孔、塑封体和下开孔组成；所述引线框架和芯片通过粘片胶连接，键合线从芯片连接到引线框架，所述引线框架上有上开孔和下开孔，塑封体包围了引线框架、粘片胶、芯片、键合线、上开孔和下开孔，芯片、键合线、引线框架构成了电路的电源和信号通道。 
一种基于框架采用开孔优化技术的扁平封装件的制作工艺的流程为：引线框架上开孔→晶圆减薄→划片→上芯（粘片）→压焊→塑封→后固化→产品分离→检验→包装→入库。  
附图说明
 图1为框架引脚开孔俯视图； 
图2为引线框架开孔后剖面图；
图3为产品上芯后剖面图；
图4为产品压焊后剖面图；
图5为产品塑封后剖面图；
图6为产品后固化后剖面图；
图7为成品剖面图。
图中，1为引线框架，2为粘片胶，3为芯片，4为键合线，5为上开孔，6为塑封体，7为下开孔。 
具体实施方式
下面结合附图对本发明做一具体描述。 
如图7所示，一种基于框架采用开孔优化技术的扁平封装件主要由引线框架1、粘片胶2、芯片3、键合线4、上开孔5、塑封体6和下开孔7组成；所述引线框架1和芯片3通过粘片胶2连接，键合线4从芯片3连接到引线框架1，所述引线框架1上有上开孔5和下开孔7，塑封体6包围了引线框架1、粘片胶2、芯片3、键合线4、上开孔5和下开孔7，芯片3、键合线4、引线框架1构成了电路的电源和信号通道。 
如图1到图7所示，一种基于框架采用开孔优化技术的扁平封装件的制作工艺的流程为：引线框架上开孔→晶圆减薄→划片→上芯（粘片）→压焊→塑封→后固化→产品分离→检验→包装→入库。 
如图1到图7所示，一种基于框架采用开孔优化技术的扁平封装件的制作工艺，按照以下步骤进行： 
    1、引线框架上开上开孔和下开孔；
2、减薄：晶圆减薄厚度50μm～200μm，粗糙度Ra 0.10mm～0.05mm ；
3、划片：150μm以上晶圆同普通QFN/dfn划片工艺，但厚度在150μm以下晶圆，使用双刀划片机及其工艺；
4、上芯（粘片）：既可采用粘片胶又可采用胶膜片（DAF）上芯；
5、压焊：压焊同常规QFN/DFN工艺相同；
6、塑封：同常规QFN/DFN工艺相同；
7、后固化、磨胶、锡化、打印、产品分离、检验、包装等均与常规QFN/DFN工艺相同。
传统冲压框架在塑封工序塑封料填充后，由于框架本身平整光滑，塑封料与框架之间的结合度低，极易出现分层的情况，封装件可靠性得不到保证。本发明采用的不同于以往的冲压框架，在框架上用冲孔或钻孔的方法开孔后，塑封时塑封料会自动填入上开孔和下开孔中，在框架与塑封料之间形成有效的防拖拉结构，大大降低封装件分层情况的发生机率，极大提高产品可靠性，优于传统半蚀刻冲压框架的塑封效果。 
 而且框架引脚上的半蚀刻开孔在塑封工序中，液化后的塑封料流入半蚀刻的开孔，直接扣住框架载体上的开孔，从而形成双重防拖拉结构，进一步保证的产品的可靠性。 
  

Claims (2)

1.一种基于框架采用开孔优化技术的扁平封装件，其特征在于：所述封装件主要由引线框架（1）、粘片胶（2）、芯片（3）、键合线（4）、上开孔（5）、塑封体（6）和下开孔（7）组成；所述引线框架（1）和芯片（3）通过粘片胶（2）连接，键合线（4）从芯片（3）连接到引线框架（1），所述引线框架（1）上有上开孔（5）和下开孔（7），塑封体（6）包围了引线框架（1）、粘片胶（2）、芯片（3）、键合线（4）、上开孔（5）和下开孔（7），芯片（3）、键合线（4）、引线框架（1）构成了电路的电源和信号通道。
2.一种基于框架采用开孔优化技术的扁平封装件的制作工艺，其特征在于：具体按照以下步骤进行：
一、引线框架上开上开孔和下开孔；
二、减薄：晶圆减薄厚度50μm～200μm，粗糙度Ra 0.10mm～0.05mm ；
三、划片：150μm以上晶圆同普通QFN/dfn划片工艺，但厚度在150μm以下晶圆，使用双刀划片机及其工艺；
四、上芯（粘片）：既可采用粘片胶又可采用胶膜片（DAF）上芯；
五、压焊：压焊同常规QFN/DFN工艺相同；
六、塑封：同常规QFN/DFN工艺相同；
七、后固化、磨胶、锡化、打印、产品分离、检验、包装等均与常规QFN/DFN工艺相同。
CN201310527641.8A 2013-10-31 2013-10-31 一种基于框架采用开孔优化技术的扁平封装件及其制作工艺 Pending CN103606539A (zh)

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CN105244294A (zh) * 2014-07-02 2016-01-13 恩智浦有限公司 暴露管芯的方形扁平无引脚（qfn）封装
CN105304506A (zh) * 2014-07-02 2016-02-03 恩智浦有限公司 暴露散热器的方形扁平无引脚（qfn）封装
CN105789068A (zh) * 2014-12-25 2016-07-20 无锡华润安盛科技有限公司 一种qfn封装器件的制备方法
CN110429075A (zh) * 2019-07-19 2019-11-08 广东气派科技有限公司 高密度多侧面引脚外露的封装结构及其生产方法

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Publication number Priority date Publication date Assignee Title
CN105244294A (zh) * 2014-07-02 2016-01-13 恩智浦有限公司 暴露管芯的方形扁平无引脚（qfn）封装
CN105304506A (zh) * 2014-07-02 2016-02-03 恩智浦有限公司 暴露散热器的方形扁平无引脚（qfn）封装
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CN110429075A (zh) * 2019-07-19 2019-11-08 广东气派科技有限公司 高密度多侧面引脚外露的封装结构及其生产方法
CN110429075B (zh) * 2019-07-19 2020-07-14 广东气派科技有限公司 高密度多侧面引脚外露的封装结构及其生产方法
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Application publication date: 20140226