CN103681578A - 一种基于框架采用引脚优化技术的扁平封装件及其制作工艺 - Google Patents

一种基于框架采用引脚优化技术的扁平封装件及其制作工艺 Download PDF

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CN103681578A
CN103681578A CN201310528002.3A CN201310528002A CN103681578A CN 103681578 A CN103681578 A CN 103681578A CN 201310528002 A CN201310528002 A CN 201310528002A CN 103681578 A CN103681578 A CN 103681578A
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chip
packaging part
bonding
lead frame
pin
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李万霞
魏海东
钟环清
李站
石宏钰
崔梦
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Huatian Technology Xian Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

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Abstract

本发明公开了一种基于框架采用引脚优化技术的扁平封装件及其制作工艺，所述封装件主要由引线框架、粘片胶、芯片、键合线和塑封体组成；所述引线框架和芯片通过粘片胶连接，键合线从芯片连接到引线框架上，塑封体包围了引线框架、粘片胶、芯片和键合线，芯片、键合线和引线框架构成了电路的电源和信号通道；所述封装件应用于宽度在0.10mm-0.18mm的引线框架引脚。所述制作工艺如下：框架缩小引脚→晶圆减薄→划片→上芯（粘片）→压焊→塑封→后固化→切割→检验→包装→入库。本发明使得集成电路框架与塑封体结合更加牢固，不受外界环境影响，在切割工序中能有效避免产品毛刺，进一步提高产品可靠性。

Description

一种基于框架采用引脚优化技术的扁平封装件及其制作工艺
技术领域
本发明属于集成电路封装技术领域，具体是一种基于框架采用引脚优化技术的扁平封装件及其制作工艺。 
背景技术
QFN（四面扁平无引脚封装）及DFN（双扁平无引脚封装）封装是在近几年随着通讯及便携式小型数码电子产品的产生(数码相机、手机、PC、MP3)而发展起来的、适用于高频、宽带、低噪声、高导热、小体积，高速度等电性要求的中小规模集成电路的封装。我们知道QFN/DFN封装有效地利用了引线脚的封装空间，从而大幅度地提高了封装效率。但目前大部分半导体封装厂商QFN/DFN的制造过程中都面临一些工艺困惑，原因是现有QFN/DFN工艺的塑封工序中，由于框架结构的局限性，使用的台阶状引线框架的防缺陷（分层）工艺措施也并非完全有效，导致QFN/DFN封装存在以下不足： 
QFN、DFN系列扁平封装件在切割过程中会有毛刺的风险，降低产品封装可靠性。框架与塑封料结合方面也容易引起分层，造成产品的不良。
发明内容
为了克服上述现有技术存在的问题，本发明的目的是提供一种基于框架引脚优化设计的扁平封装件制作工艺，集成电路框架与塑封体结合更加牢固，不受外界环境影响，在切割工序中能有效避免产品毛刺，进一步提高产品可靠性。 
一种基于框架采用引脚优化技术的扁平封装件，所述封装件主要由引线框架、粘片胶、芯片、键合线和塑封体组成；所述引线框架和芯片通过粘片胶链接，键合线从芯片连接到引线框架上，塑封体包围了引线框架、粘片胶、芯片和键合线，芯片、键合线和引线框架构成了电路的电源和信号通道；所述封装件应用于宽度在0.10mm-0.18mm的引线框架引脚。
一种基于框架采用引脚优化技术的扁平封装件的制作工艺流程如下：框架缩小引脚→晶圆减薄→划片→上芯（粘片）→压焊→塑封→后固化→切割→检验→包装→入库。
本发明采用一种基于框架引脚优化设计的扁平封装件制作工艺，在框架的引脚部分接近产品边缘的部分设计较窄常规引脚宽度稍短的宽度，使用此法产品在切割过程中会降低引脚与切割刀的摩擦，能降低毛刺发生的可能性，更能有效减少产品分层，保证了产品的封装良率，同时此种设计在塑封后固化之后能更紧密地跟塑封料结合，提高产品可靠性，再一次保证了产品的封装良率。
附图说明
图1为常规宽度为0.20mm-0.30mm的框架引脚设计俯视图； 
图2缩小宽度为0.10mm-0.18mm的框架引脚设计俯视图；
图3为引线框架剖面图；
图4为产品上芯后剖面图；
图5为产品压焊后剖面图；
图6为产品塑封后剖面图。
图中，1为引线框架，2为粘片胶，3为芯片，4为键合线，5为塑封体。
具体实施方式
以下结合附图对本发明做进一步的描述。 
如图6所示，一种基于框架采用引脚优化技术的扁平封装件，所述封装件主要由引线框架1、粘片胶2、芯片3、键合线4和塑封体5组成；所述引线框架1和芯片3通过粘片胶2链接，键合线4从芯片3连接到引线框架1上，塑封体5包围了引线框架1、粘片胶2、芯片3和键合线4，芯片3、键合线4和引线框架1构成了电路的电源和信号通道；所述封装件应用于宽度在0.10mm-0.18mm的引线框架引脚。
一种基于框架采用引脚优化技术的扁平封装件的制作工艺流程如下：框架缩小引脚→晶圆减薄→划片→上芯（粘片）→压焊→塑封→后固化→切割→检验→包装→入库。
如图1到图6所示，一种基于框架采用引脚优化技术的扁平封装件的制作工艺，具体按照如下步骤进行：
（1）、常规引线框架引脚长度为0.20mm-0.30mm，缩小到长度为0.10mm-0.18mm；
（2）、减薄：减薄厚度50μm～200μm，粗糙度Ra 0.10mm～0.05mm ；
（3）、划片：150μm以上晶圆同普通QFN/dfn划片工艺，但厚度在150μm以下晶圆，使用双刀划片机及其工艺；
（4）、上芯（粘片）：既可采用粘片胶又可采用胶膜片（DAF）上芯；
（5）、压焊：压焊同常规QFN/DFN工艺相同；
（6）、塑封：同常规QFN/DFN工艺相同；
传统冲压框架在塑封工序塑封料填充后，由于框架本身平整光滑，塑封料与框架之间的结合度低，极易出现分层的情况，封装件可靠性得不到保证。本发明采用的不同于以往的冲压框架，缩小引脚的宽度，在塑封时更能和塑封料紧密结合，提高产品封装良率，保证产品可靠性。
（7）、后固化、磨胶、锡化、打印与常规QFN/DFN工艺相同；
（8）、切割与常规QFN/DFN工艺相同；
此发明采用的优化引脚的设计，在产品切割的工序能有效减少产品引脚的受力面积，在切割后能有效避免毛刺，更能有效减少分层，进一步保证了产品的封装良率。
（9）、检验、包装等均与常规QFN/DFN工艺相同。

Claims (2)

1.一种基于框架采用引脚优化技术的扁平封装件，其特征在于：所述封装件主要由引线框架（1）、粘片胶（2）、芯片（3）、键合线（4）和塑封体（5）组成；所述引线框架（1）和芯片（3）通过粘片胶（2）连接，键合线（4）从芯片（3）连接到引线框架（1）上，塑封体（5）包围了引线框架（1）、粘片胶（2）、芯片（3）和键合线（4），芯片（3）、键合线（4）和引线框架（1）构成了电路的电源和信号通道；所述封装件应用于宽度在0.10mm-0.18mm的引线框架引脚。
2.一种基于框架采用引脚优化技术的扁平封装件的制作工艺，其特征在于：具体按照如下步骤进行：
（1）、常规引线框架引脚长度为0.20mm-0.30mm，缩小到长度为0.10mm-0.18mm；
（2）、减薄：减薄厚度50μm～200μm，粗糙度Ra 0.10mm～0.05mm ；
（3）、划片：150μm以上晶圆同普通QFN/dfn划片工艺，但厚度在150μm以下晶圆，使用双刀划片机及其工艺；
（4）、上芯（粘片）：既可采用粘片胶又可采用胶膜片（DAF）上芯；
（5）、压焊：压焊同常规QFN/DFN工艺相同；
（6）、塑封：同常规QFN/DFN工艺相同；
（7）、后固化、磨胶、锡化、打印与常规QFN/DFN工艺相同；
（8）、切割与常规QFN/DFN工艺相同；
（9）、检验、包装等均与常规QFN/DFN工艺相同。
CN201310528002.3A 2013-10-31 2013-10-31 一种基于框架采用引脚优化技术的扁平封装件及其制作工艺 Pending CN103681578A (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105810655A (zh) * 2014-12-31 2016-07-27 无锡华润安盛科技有限公司 一种引线框引脚切割结构及其切割方法

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US20070215995A1 (en) * 2006-03-14 2007-09-20 Chipmos Technologies (Bermuda) Ltd. Fabrication processes of leadframe-based BGA packages and leadless leadframe implemented in the processes
CN101694837A (zh) * 2009-10-17 2010-04-14 天水华天科技股份有限公司 一种双排引脚的四面扁平无引脚封装件及其生产方法
CN101958303A (zh) * 2010-09-04 2011-01-26 江苏长电科技股份有限公司 双面图形芯片正装单颗封装结构及其封装方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070215995A1 (en) * 2006-03-14 2007-09-20 Chipmos Technologies (Bermuda) Ltd. Fabrication processes of leadframe-based BGA packages and leadless leadframe implemented in the processes
CN101694837A (zh) * 2009-10-17 2010-04-14 天水华天科技股份有限公司 一种双排引脚的四面扁平无引脚封装件及其生产方法
CN101958303A (zh) * 2010-09-04 2011-01-26 江苏长电科技股份有限公司 双面图形芯片正装单颗封装结构及其封装方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105810655A (zh) * 2014-12-31 2016-07-27 无锡华润安盛科技有限公司 一种引线框引脚切割结构及其切割方法

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