CN202772132U - 一种基于冲压框架的多芯片堆叠式扁平封装件 - Google Patents

一种基于冲压框架的多芯片堆叠式扁平封装件 Download PDF

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CN202772132U
CN202772132U CN2012204255311U CN201220425531U CN202772132U CN 202772132 U CN202772132 U CN 202772132U CN 2012204255311 U CN2012204255311 U CN 2012204255311U CN 201220425531 U CN201220425531 U CN 201220425531U CN 202772132 U CN202772132 U CN 202772132U
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bonding line
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郭小伟
谌世广
崔梦
谢建友
刘卫东
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Huatian Technology Xian Co Ltd
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    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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Abstract

本实用新型涉及一种基于冲压框架的多芯片堆叠式扁平封装件，属于集成电路封装技术领域。采用一种新型的框架，该框架采用冲压法加工而成，并采用冲压或钻孔的方法在框架上形成通孔，用以替代蚀刻法在框架上蚀刻出台阶从而起到抗分层的作用，集成电路封装过程中塑封料填入孔中，从而在框架与塑封料之间形成有效的防拖拉结构，使塑封料与框架间的结合力更好，极大的降低了分层的可能行，显著提高产品可靠性。同时解决了以往研磨框架及半腐蚀框架费用高的缺陷，极大的降低了成本。

Description

一种基于冲压框架的多芯片堆叠式扁平封装件
技术领域
本实用新型涉及一种基于冲压框架的多芯片堆叠式扁平封装件，属于集成电路封装技术领域。
背景技术
QFN(四面扁平无引脚封装)及DFN(双扁平无引脚封装)封装是在近几年随着通讯及便携式小型数码电子产品的产生(数码相机、手机、PC、MP3)而发展起来的、适用于高频、宽带、低噪声、高导热、小体积，高速度等电性要求的中小规模集成电路的封装。我们知道QFN/DFN封装有效地利用了引线脚的封装空间，从而大幅度地提高了封装效率。但目前大部分半导体封装厂商QFN/DFN的制造过程中对于框架的选用都面临一些难题，现有框架为冲压框架和蚀刻框架两种，冲压框架，其模具采用机械法工形成，生产效率高，单颗产品成本较低，但对于一些特殊图形的引线框架，无法选用冲压法加工，例如QFN/DFN/QFP等载体外露的框架，载体与内引脚之间有一定的高度差，形成一定的台阶，冲压法难以实现及控制好该台阶；化学蚀刻框架，其模具费用低，开发周期短，可达到2周～1个月，封装时塑封、切割模具可共用，投入成本低，但其生产效率低，且单颗产品成本较高。
现有QFN/DFN工艺的塑封工序中，由于框架结构的局限性，导致QFN/DFN封装存在以下不足：
1.集成电路芯片和载体的结合力不好，当受外界环境变化的影响时，会造成产品内部产生分层缺陷，致使性能褪化，甚至失效。
2.载体背面和塑封料的结合力不好，当受外界环境的影响，会造成产品产生缺陷(分层)；或外露载体(基岛)上有较厚的溢料。
实用新型内容
针对上诉常规冲压框架、蚀刻框架的缺陷，本实用新型提供一种基于冲压框架的多芯片堆叠式扁平封装件，塑封料与框架的结合更牢固，抗分层效果更好。
本实用新型采用的技术方案：多芯片堆叠式封装件包括引线框架1、芯片A3与引线框架1之间的粘片胶A2、芯片A3、芯片A3与引线框架1之间的键合线A4、开孔5、塑封体6、芯片A3与芯片B8之间的粘片胶B7、芯片B8、芯片A3与芯片B8之间的键合线B9、芯片B8与引线框架1间的键合线C10；塑封体6包围了引线框架1、芯片A3与引线框架1之间的粘
片胶B7、芯片B8、芯片A3与芯片B8之间的键合线B9、芯片B8与引线框架1间的键合线C10；塑封体6包围了引线框架1、芯片A3与引线框架1之间的粘片胶A2、芯片A3、芯片A3与引线框架1之间的键合线A4、开孔5、塑封体6、芯片A3与芯片B8之间的粘片胶B7、芯片B8、芯片A3与芯片B8之间的键合线B9、芯片B8与引线框架1间的键合线C10；构成了电路整体，并且塑封体6对芯片A3、芯片B8、键合线A4、键合线B9、键合线C10起到了支撑和保护作用，芯片A3、芯片B8、键合线A4、键合线B9、键合线C10和引线框架1构成了电路的电源和信号通道。
所述的键合线A4、键合线B9、键合线C10为金线或者铜线；粘片胶A2和粘片胶B7可以用胶膜片(DAF)代换。
本实用新型有益效果：采用一种新型的框架，该框架采用冲压法加工而成，并采用冲压或钻孔的方法在框架上形成通孔，用以替代蚀刻法在框架上蚀刻出台阶从而起到抗分层的作用，集成电路封装过程中塑封料填入孔中，从而在框架与塑封料之间形成有效的防拖拉结构，使塑封料与框架间的结合力更好，极大的降低了分层的可能行，显著提高产品可靠性。同时解决了以往研磨框架及半腐蚀框架费用高的缺陷，极大的降低了成本。
附图说明
图1为本实用新型的结构示意图；
图中：1-引线框架、2-粘片胶A、3-芯片A、4-键合线A、5-开孔、6-塑封体、7-粘片胶B、8-芯片B、9-键合线B、10-键合线C。
具体实施方式
下面结合附图和实施例对本实用新型做进一步说明，以方便技术人员理解。
如图1所示：多芯片堆叠式封装件包括引线框架1、芯片A3与引线框架1之间的粘片胶A2、芯片A3、芯片A3与引线框架1之间的键合线A4、开孔5、塑封体6、芯片A3与芯片B8之间的粘片胶B7、芯片B8、芯片A3与芯片B8之间的键合线B9、芯片B8与引线框架1间的键合线C10；塑封体6包围了引线框架1、芯片A3与引线框架1之间的粘片胶A2、芯片A3、芯片A3与引线框架1之间的键合线A4、开孔5、塑封体6、芯片A3与芯片B8之间的粘片胶B7、芯片B8、芯片A3与芯片B8之间的键合线B9、芯片B8与引线框架1间的键合线C10；构成了电路整体，并且塑封体6对芯片A3、芯片B8、键合线A4、键合线B9、键合线C10起到了支撑和保护作用，芯片A3、芯片B8、键合线A4、键合线B9、键合线C10和引线框架1构成了电路的电源和信号通道。
所述的键合线A4、键合线B9、键合线C10为金线或者铜线；粘片胶A2和粘片胶B7可以用胶膜片(DAF)代换。
本实用新型通过附图进行说明的，在不脱离本实用新型范围的情况下，还可以对本实用新型专利进行各种变换及等同代替，因此，本实用新型专利不局限于所公开的具体实施过程，而应当包括落入本实用新型专利权利要求范围内的全部实施方案。

Claims (3)

1.一种基于冲压框架的多芯片堆叠式扁平封装件，其特征在于：多芯片堆叠式封装件包括引线框架、芯片A与引线框架之间的粘片胶A、芯片A、芯片A与引线框架之间的键合线A、开孔、塑封体、芯片A与芯片B之间的粘片胶B、芯片B、芯片A与芯片B之间的键合线B、芯片B与引线框架间的键合线C；塑封体包围了引线框架、芯片A与引线框架之间的粘片胶A、芯片A、芯片A与引线框架之间的键合线A、开孔、塑封体、芯片A与芯片B之间的粘片胶B、芯片B、芯片A与芯片B之间的键合线B、芯片B与引线框架间的键合线C；构成了电路整体，并且塑封体对芯片A、芯片B、键合线A、键合线B、键合线C起到了支撑和保护作用，芯片A、芯片B、键合线A、键合线B、键合线C和引线框架构成了电路的电源和信号通道。
2.根据权利要求1所述的一种基于冲压框架的多芯片堆叠式扁平封装件，其特征在于：所述的键合线A、键合线B、键合线C为金线或者铜线。
3.根据权利要求1所述的一种基于冲压框架的多芯片堆叠式扁平封装件，其特征在于：粘片胶A和粘片胶B可以用胶膜片代换。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103928430A (zh) * 2014-03-31 2014-07-16 华天科技（西安）有限公司 一种基于冲压框架带有通孔的扁平多芯片封装件

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103928430A (zh) * 2014-03-31 2014-07-16 华天科技（西安）有限公司 一种基于冲压框架带有通孔的扁平多芯片封装件

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