CN202042481U - 一种功率模块 - Google Patents

一种功率模块 Download PDF

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CN202042481U
CN202042481U CN2011200802610U CN201120080261U CN202042481U CN 202042481 U CN202042481 U CN 202042481U CN 2011200802610 U CN2011200802610 U CN 2011200802610U CN 201120080261 U CN201120080261 U CN 201120080261U CN 202042481 U CN202042481 U CN 202042481U
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chips
chip
power model
model
substrate
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张文雁
王望峰
赢勇勤
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BYD Semiconductor Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

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Abstract

本实用新型涉及集成电路封装领域，具体公开了一种功率模块，包括：基板，具有一承载面；多个独立封装的芯片，所述多个芯片固定设置于所述基板的承载面上，多个芯片电连接。本实用新型提供的一种功率模块，多个具有独立封装结构的芯片设置于所述基板的承载面上，由于芯片是经过独立封装的，解决了现有技术中没有封装的芯片放置在基板上后再塑封时容易将绑线冲歪冲断，并且效率低的问题。

Description

一种功率模块
技术领域
本实用新型涉及集成电路封装领域，具体涉及一种功率模块。 
背景技术
已知的功率模块封装技术，通常是将多种芯片和引线框架通过焊接直接粘贴在基板或者引线框架上；如图1所示，是IPM（Intelligent Power Module，智能功率模块）的封装结构示意图；包括引线框架5，该引线框架10包括引脚和本体；驱动芯片2设置于引线框架本体上；散热基板8，功率芯片4设置于散热基板8上，电阻3设置于散热基板上，电阻3通过绑线连接驱动芯片2和功率芯片4，引线框架本体、驱动芯片2、散热基板8、功率芯片4和电阻3均密封于树脂7内，树脂内的各元器件通过绑线电连接。通过注入塑封料模压封装整个功率模块，即为树脂7。模压对绑线线弧高度以及连线会有冲歪、冲断的可能。现有的技术是控制线弧的高度，线与线之间的间隙。所以焊连接线时，要实时的监测和控制连线的高度，影响生产的效率。这种封装形式还存在芯片和基板或者引线框架的相对位置移动以及绑线之间容易短接问题，并且如果功率模块中的一个元器件失效，则整个模块都失效了；并且工序多而复杂，导致成本高、生产效率低。 
实用新型内容
本实用新型为解决现有技术中多个芯片通过绑线后封装在一个模块中导致绑线易断、影响生产效率的问题。 
为解决上述技术问题，本实用新型提供如下技术方案： 
一种功率模块，包括：基板，具有一承载面；多个独立封装的芯片，所述多个芯片固定设置于所述基板的承载面上，多个芯片电连接。
进一步地，还包括用于密封多个芯片的树脂。 
优选地，所述基板为DBC板。 
优选地，所述基板为PCB板。
优选地，所述芯片为IGBT、快恢复二极管芯片。 
进一步地，所述多个芯片通过焊锡固定连接在所述基板的承载面上。 
进一步地，所述与基板承载面相对的一面设置有绝缘层。 
进一步地，所述绝缘层上设置有散热层。 
与现有技术相比，本实用新型具有如下有益效果：本实用新型提供的一种功率模块，多个具有独立封装结构的芯片设置于所述基板的承载面上，由于芯片是经过独立封装的，解决了现有技术中没有封装的芯片放置在基板上后再塑封时容易将绑线冲歪冲断，并且效率低的问题。 
附图说明
图1是现有技术中功率模块的封装结构示意图。 
图2是本实用新型实施例功率模块封装结构示意图。 
图3是本实用新型实施例功率模块基板的结构示意图。 
具体实施方式
为了使本实用新型所解决的技术问题、技术方案及有益效果更加清楚明白，以下结合附图及实施例，对本实用新型进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本实用新型，并不用于限定本实用新型。 
图2是本实用新型实施例功率模块封装结构示意图；提供一种功率模块，包括：基板30，具有一承载面；多个独立封装的芯片20，所述多个芯片20固定设置于所述基板30的承载面上，多个芯片20电连接。所述芯片20的电信号通过引脚10连接至基板外部。多个具有独立封装结构的芯片设置于所述基板的承载面上，由于芯片是经过独立封装的，解决了现有技术中没有封装的芯片放置在基板上后再塑封时容易将绑线冲歪冲断，并且效率低的问题。 
为了更好的保护芯片，该功率模块还包括用于密封多个芯片的树脂，可以采用但不限于塑封、注胶或灌胶等方式进行表面塑封膜覆盖，以实现最佳的绝缘、耐压、防静电、外观、应用装贴等要求。所述基板30 DBC板（Direct Bonding Copper，陶瓷覆铜板）、引线框架或者PCB板中的一种，也可以是其他单层或者多层金属或者非金属基板。在与基板30承载面相对的一面设置有绝缘层如图3是本实用新型实施例功率模块基板的结构示意图；图中绝缘层为图中31所示，在绝缘层31上还设置有散热层32。 
本实施例中的多个芯片为IGBT、快恢复二极管芯片；或者采用功率因素校正模块的芯片、太阳能逆变器模块的芯片。上述芯片均已各自独立封装，封装的芯片可以采用但不限于：QFN(  quad flat non-leaded package，四侧无引脚扁平封装，表面贴装型封装之一，现在多称为LCC。)、DFN(dual flat non-leaded package，双边或方形扁平封装)、WLP (wafer level package，晶圆尺寸封装)、DIP(dual in-line package，双列直插式封装)、SOP(small Out-Line package，小外形封装)、TSOP(Thin Small Outline Package，薄型小尺寸封装)、QFP(quad flat package，四侧引脚扁平封装)等封装形式；在封装过程中充分发挥上述封装形式的高密度优势、特征尺寸缩小、降低封装成本，同时依据已封装塑封体可以实现功率模块封装耐压、绝缘要求，独立封装芯片在封装过程中即可进行测试，筛选出制程中产生的不良芯片。上述多个芯片通过焊锡固定连接与所述基板的承载面上，如果其中某一个芯片出现问题损坏，那么可以方便的将该芯片取下换成新的良好的芯片，功率模块可以继续使用。 
本实用新型实施例提供的功率模块，是将单独封装好了的芯片连接到线路基板上，这样可避免芯片和基板的相对位置移动，且发现有失效的元器件时，可以及时更换元器件，以达到保持整个模块功能完整性；从而简化了工艺流程，减少相关工作人员的配备，这与市场要求的低成本，高效率，高良率，高可靠性相适应。 
以上所述仅为本实用新型的较佳实施例而已，并不用以限制本实用新型，凡在本实用新型的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本实用新型的保护范围之内。 

Claims (8)

1.一种功率模块，其特征在于，包括：
基板，具有一承载面；
多个独立封装的芯片，所述多个芯片固定设置于所述基板的承载面上，多个芯片电连接。
2.根据权利要求1所述的功率模块，其特征在于，还包括用于密封多个芯片的树脂。
3.根据权利要求1所述的功率模块，其特征在于， 所述基板为DBC板。
4.根据权利要求1所述的功率模块，其特征在于，所述基板为PCB板。
5.根据权利要求1所述的功率模块，其特征在于，所述芯片为IGBT、快恢复二极管芯片。
6.根据权利要求1所述的功率模块，其特征在于，所述多个芯片通过焊锡固定连接在所述基板的承载面上。
7.根据权利要求1至6任一项所述的功率模块，其特征在于，所述与基板承载面相对的一面设置有绝缘层。
8.根据权利要求7所述的功率模块，其特征在于，所述绝缘层上设置有散热层。
CN2011200802610U 2011-03-24 2011-03-24 一种功率模块 Expired - Lifetime CN202042481U (zh)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103811433A (zh) * 2012-11-13 2014-05-21 通用电气公司 一种表面安装封装件
CN104659006A (zh) * 2013-11-19 2015-05-27 西安永电电气有限责任公司 一种塑封式ipm引线框架结构

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103811433A (zh) * 2012-11-13 2014-05-21 通用电气公司 一种表面安装封装件
CN103811433B (zh) * 2012-11-13 2019-01-01 通用电气公司 一种表面安装封装件
CN104659006A (zh) * 2013-11-19 2015-05-27 西安永电电气有限责任公司 一种塑封式ipm引线框架结构
CN104659006B (zh) * 2013-11-19 2017-11-03 西安永电电气有限责任公司 一种塑封式ipm引线框架结构

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Address after: 518119 No.1 Yan'an Road, Kuiyong street, Dapeng New District, Shenzhen City, Guangdong Province

Patentee after: BYD Semiconductor Co.,Ltd.

Address before: 518119 No.1 Yan'an Road, Kuiyong street, Dapeng New District, Shenzhen City, Guangdong Province

Patentee before: SHENZHEN BYD MICROELECTRONICS Co.,Ltd.

CX01 Expiry of patent term
CX01 Expiry of patent term

Granted publication date: 20111116