CN103811433B - 一种表面安装封装件 - Google Patents

一种表面安装封装件 Download PDF

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Publication number
CN103811433B
CN103811433B CN201310572275.8A CN201310572275A CN103811433B CN 103811433 B CN103811433 B CN 103811433B CN 201310572275 A CN201310572275 A CN 201310572275A CN 103811433 B CN103811433 B CN 103811433B
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Prior art keywords
mount package
surface mount
double
ceramics substrate
external circuit
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CN103811433A (zh
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E.C.德尔加多
J.S.格拉泽
B.L.劳登
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General Electric Co
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General Electric Co
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Abstract

一种表面安装封装件，其包括至少一个半导体装置和POL封装和互连系统，所述POL封装和互连系统围绕所述至少一个半导体装置形成且被构造成使表面安装封装件能够安装到外部电路。POL系统包括上覆一个或多个半导体装置的第一表面的介电层和金属互连结构，该金属互连结构延伸通过穿过介电层形成的通路或开口以便电联接到一个或多个半导体装置上的连接垫。金属化层形成于包括平坦的平面结构的金属互连结构上方，并且双面陶瓷基板定位在一个或多个半导体装置的第二表面上，其中双面陶瓷基板被构造成当表面安装封装件接合到其上时使一个或多个半导体装置的漏极与外部电路电隔离并且将热量传导离开一个或多个半导体装置。

Description

一种表面安装封装件
技术领域
本发明大体上涉及用于封装半导体装置的结构，并且更特别地涉及提供低寄生电感、双面冷却和方便安装到外部电路的半导体装置封装结构。
背景技术
功率半导体装置是在诸如开关电源的电力电子电路中用作开关或整流器的半导体装置。大多数功率半导体装置仅在换向模式(即，它们或者接通或者关断)下使用，并且因此为此而进行优化。一种这样的功率半导体装置是高性能、宽带间隙碳化硅(SiC)MOSFET(金属-氧化物-半导体型场效应管)，其具有非常快的开关转换并可用作功率或高频率装置。相比其它低频率、低功率半导体装置，SiC MOSFET能够载送更大量的电流并且通常能够在关断状态下支持更大的反向偏置电压，使得SiCMOSFET非常适合在高端军事和医疗保健产品及其它尖端技术中使用。
在使用中，高电压功率半导体装置通常借助于封装结构而表面安装到外部电路，其中封装结构提供电连接到外部电路，并且也提供除去由装置产生的热量并保护装置不受外部环境影响的方式。由于与此类封装结构的冷却和电感缺陷相关联的局限性，大多数现有的封装结构仅适合低频率/低功率应用。例如，在现有封装结构中，诸如MOSFET的一个或多个半导体装置的漏极直接连接到封装结构的背垫金属（back metal）接头（tab），使得封装结构被认为具有“热接头”。带有热接头的封装件很难提供良好的热通道以便冷却一个或多个半导体装置，因为必须电绝缘互连于封装件的背面或接头的铜焊盘。此外，现有封装结构使用焊线来形成从半导体装置到封装件引脚的连接，这种非平面焊线互连有助于增加封装件的电感。由于在引脚焊接到板时形成的传导回路，封装件的引出脚的构造方式也有助于封装件的总电感--其中在板和封装件之间具有固有间距。
因此，需要一种通过提供一个或多个半导体装置的低电感互连和改善的冷却而适合高频率和高功率应用这两者的半导体装置封装件。还需要此类半导体装置封装件以提供封装件到外部电路的方便的表面安装和附连，同时解放设计者，使其不必在进行到电路的剩余部分的高电流连接的同时提供电压隔离。
发明内容
本发明的实施例通过提供半导体装置封装结构而克服了上述缺点，该结构提供低寄生电感、双面冷却和方便安装到外部电路。
根据本发明的一个方面，表面安装封装件包括：至少一个半导体装置，其包括基板，该基板具有形成于其上的多个连接垫；以及功率上覆(POL,power overly)封装和互连系统，其围绕至少一个半导体装置形成且被构造成使表面安装封装件安装到外部电路，其中POL封装和互连系统还包括上覆至少一个半导体装置的第一表面且借助于粘合剂层接合到该第一表面的介电层，其中介电层和粘合剂层包括穿过其中形成的多个通路（vias）或开口。POL封装和互连系统还包括：金属互连结构，其延伸通过穿过介电层和粘合剂形成的通路或开口以便电联接到至少一个半导体装置的多个连接垫；金属化层，其形成于金属互连结构上方且包括平坦的平面结构；以及双面陶瓷基板，其定位在与第一表面相对的至少一个半导体装置的第二表面上，双面陶瓷基板被构造成当表面安装封装件接合到其上时电隔离至少一个半导体装置的漏极与外部电路，并且被进一步构造成将热量传导离开至少一个半导体装置。
进一步的，所述POL封装和互连系统还包括构造成提供所述表面安装封装件连接到所述外部电路的栅极、源极和漏极连接接头。
进一步的，所述栅极、源极和漏极连接接头包括焊盘。
进一步的，所述栅极、源极和漏极连接接头与所述双面陶瓷基板结合形成所述表面安装封装件的平面的底部表面。
进一步的，所述栅极、源极和漏极连接接头电联接到所述金属互连结构和所述至少一个半导体装置。
进一步的，所述POL封装和互连系统还包括下列中的一个：介电顶层，其施加在所述金属化层上方；或顶部表面双面陶瓷基板，其施加在所述金属化层上方，所述顶部表面双面陶瓷基板被构造成减小通过所述表面安装封装件的顶部表面的热通道的热阻。
进一步的，所述介电顶层和所述顶部表面双面陶瓷基板中的所述一个被构造成为所述表面安装封装件提供平坦的顶部表面以适应其到接触冷却器的附连，从而提供所述表面安装封装件的双面冷却。
进一步的，所述双面陶瓷基板包括直接敷铜结构，所述直接敷铜结构包括陶瓷绝缘贴片，所述陶瓷绝缘贴片具有施加在其顶部表面和底部表面中每一个上的铜片。
进一步的，所述至少一个半导体装置包括高频率或高功率的半导体装置。
进一步的，所述至少一个半导体装置包括碳化硅SiC MOSFET和SiC二极管中的至少一个。
进一步的，所述POL封装和互连系统被构造成提供在所述表面安装封装件中的平面连接和到所述表面安装封装件的平面连接以减少在所述表面安装封装件中的电感回路。
根据本发明的另一方面，具有构造成安装到外部电路的顶部表面和底部表面的表面安装模块包括一个或多个功率半导体装置和功率上覆(POL)封装和互连系统，POL封装和互连系统围绕一个或多个功率半导体装置形成且被构造以提供表面安装模块到外部电路的安装。POL封装和互连系统还包括：介电层，其上覆一个或多个功率半导体装置的有源表面；金属化互连结构，其形成于介电层的上方且向下延伸穿过形成于介电层中的开口以便电联接到一个或多个功率半导体装置；以及多个连接垫，其形成于表面安装模块的底部表面上以提供到外部电路的连接，多个连接垫包括宽的平坦的可焊接垫。POL封装和互连系统还包括邻近多个连接垫定位的双面陶瓷基板，其中双面陶瓷基板被构造成在空间上分离和电隔离一个或多个功率半导体装置的浮动接头与外部电路，同时将热量传导离开一个或多个功率半导体装置并到表面安装模块的外部。金属化互连结构、多个连接垫和双面陶瓷基板为表面安装模块形成最小化表面安装模块的电感的、多个平面的互连件。
进一步的，所述多个连接垫包括栅极、源极和漏极连接接头，所述栅极、源极和漏极连接接头与所述双面陶瓷基板结合形成所述表面安装模块的平面的底部表面。
进一步的，所述金属化互连结构包括构造成适应接触冷却器到所述表面安装模块的附连的、平坦的平面的顶部表面。
进一步的，所述POL封装和互连系统还包括施加在所述金属化互连结构上方的介电顶层和顶部表面双面陶瓷基板中的一个，所述顶部表面双面陶瓷基板被构造成减小通过所述表面安装模块的顶部表面的热通道的热阻。
进一步的，所述双面陶瓷基板包括直接敷铜结构，所述直接敷铜结构包括：陶瓷贴片；以及铜片，其附连到所述陶瓷贴片的相对侧中的每一侧。
根据本发明的又一方面，表面安装封装件包括一个或多个功率半导体装置和功率上覆(POL)封装和互连系统，POL封装和互连系统围绕一个或多个功率半导体装置形成以供表面安装封装件安装到外部电路。POL封装和互连系统在一个或多个功率半导体装置、POL封装和互连系统的内部连接件与外部电路之间形成多个平面的互连件，以便最小化表面安装模块的电感。POL封装和互连系统被构造成当表面安装封装件安装到外部电路时电隔离一个或多个功率半导体装置的背面漏极接头与外部电路，同时将热量传导离开一个或多个功率半导体装置并到表面安装封装件的外部。
进一步的，所述POL封装和互连系统包括：介电层，其上覆所述一个或多个功率半导体装置的第一表面且借助于粘合剂层接合到所述第一表面，所述介电层和粘合剂层包括多个穿过其中形成的通路或开口；金属互连结构，其延伸通过穿过所述介电层和粘合剂形成的所述通路或开口以便电联接到所述一个或多个功率半导体装置的所述多个连接垫；金属化层，其形成于所述金属互连结构上方，所述金属化层包括平坦的平面结构；以及双面陶瓷基板，其定位在与所述第一表面相对的所述至少一个半导体装置的第二表面上，所述双面陶瓷基板被构造成当所述表面安装封装件接合到其上时使所述一个或多个功率半导体装置的漏极与所述外部电路电隔离并且被构造成将热量传导离开所述至少一个半导体装置。
进一步的，所述POL封装和互连系统还包括施加在所述金属化层上方的顶部表面双面陶瓷基板，所述顶部表面双面陶瓷基板被构造成减小通过所述表面安装封装件的顶部表面的热通道的热阻。
进一步的，所述POL封装和互连系统被构造成在所述表面安装封装件上提供平坦的平面的顶部表面和底部表面，以便提供所述表面安装封装件的双面冷却。
根据结合附图提供的本发明的优选实施例的以下详细描述，将更容易理解这些和其它优点和特征。
附图说明
附图示出用于执行本发明的目前想到的实施例。
在附图中：
图1是根据本发明的实施例的表面安装封装件的示意性俯视图。
图2是图1的表面安装封装件的示意性仰视图。
图3是图1的表面安装封装件沿线3-3截取的示意性横截面侧视图。
图4是图1的表面安装封装件沿线4-4截取的示意性横截面侧视图。
图5是根据本发明的另一个实施例的半导体装置封装件的示意性横截面侧视图。
图6是根据本发明的另一个实施例的半导体装置封装件的示意性横截面侧视图。
具体实施方式
本发明的实施例提供了具有平面互连件和浮动漏极接头的半导体装置封装件以减少封装件中的电感回路并且提供了良好的热通道以减小对半导体装置和封装件的热应力，同时也使得封装件能够更容易地安装到外部电路。
参看图1-4，示出了根据本发明的实施例的表面安装封装件或模块10的各种视图。表面安装封装件10包括在其中的一个或多个半导体装置12，半导体装置12包括基板13，基板具有形成于其上的多个连接垫15，根据各种实施例，半导体装置12可以是晶体管、晶粒（die）、二极管或其它电力电子装置的形式。如图1所示，碳化硅(SiC)MOSFET14和两个SiC二极管16设置在表面安装封装件10中，然而，应当认识到，可以在表面安装封装件10中包括更多或更少数量的半导体装置12。在一个示例性实施例中，包括在表面安装封装件10中的半导体装置12的数量使得封装件被视为“低数量（low count）”模块。如在实施例中进一步所示，还提供了类似于半导体装置12使用的垫片18。垫片18可由铜或用作电短路的类似的材料制成，或者可由用来提供机械支撑或充当表面安装封装件中的热导管的类似氧化铝或氮化铝的陶瓷制成。
一个或多个半导体装置12使用功率上覆(POL)封装和互连系统20进行封装，POL封装和互连系统20实现密实（rugged）而可靠的金属连接和互连件，该金属连接和互连件被构造成减小接触电阻并因此减小表面安装封装件中的电压损耗和传导损耗，使得POL系统20很适合在高频率和高功率应用中使用。POL系统20在半导体装置、封装件的内部连接、和外部板连接之间提供平面互连件，其中到半导体装置12上的接触垫的宽的铜带/垫和金属连接/通路或开口被用来进行连接。相比现有技术的互连系统，例如，引线结合和覆晶互连技术，POL系统20以更高的电流容量提供更好的热性能，特别是在瞬态电流尖脉冲（spike）期间。POL系统20还提供相对低的寄生电感和低的电迁移趋势。如图3和4所示，POL系统20在表面安装封装件10中提供薄型(low profile)、平面的互连结构。
如图3和4所示，在使用POL技术封装一个或多个半导体装置12的过程中，一个或多个粘合剂层22和介电层24(例如，介电的层合物或薄膜)提供用于附连到一个或多个半导体装置12的第一表面26(即，有源表面)。在执行这样的附连过程中，介电层24首先被施加到框架结构(未示出)，然后将粘合剂层22沉积到介电层24以适应一个或多个半导体装置12在其上的后续放置。介电层24呈层合物或薄膜的形式并且被置于框架结构上以在施加粘合剂层22(和背衬/防粘片，未示出)期间和穿过粘合剂层22和介电层合物24的通路或开口28的后续形成期间提供稳定性，其中这样的通路或开口28借助于例如激光烧蚀或激光钻孔工艺、等离子体蚀刻、光界定(photo-definition)或机械钻孔工艺形成，并且成形为与半导体装置12的接触垫30对齐。根据本发明的实施例，介电层24可由多种介电材料中的一种形成，例如聚四氟乙烯(PTFE)、聚砜材料(例如，)或诸如液晶聚合物(LCP)或聚酰亚胺材料的另一种聚合物膜。
POL系统20包括向下成形到通路或开口28中且上覆最顶层介电层（topmostdielectric layer）24的金属互连件32和金属化层34(即，铜顶层)。金属互连件32通常通过溅镀和电镀应用的组合形成，但应当认识到，也可使用其它金属沉积的无电镀法。例如，钛粘附层和铜晶种层可以首先通过溅镀工艺施加，然后是将铜的厚度增加至期望水平的电镀工艺。所施加的金属材料随后被图案化成具有所需形状的金属互连件32，金属互连件32充当穿过介电层24和粘合剂层22的竖直贯通件。如图3和4所示，根据一个实施例，金属互连件32形成到半导体装置12上的接触垫30的直接金属连接和电连接。
当热量从半导体装置12通过形成于通路或开口28中的导电的金属互连件32流出到顶部金属化层34时，金属化层34与金属互连件32联合提供来自表面安装封装件10的半导体装置12的热量的流出。如图3和4所示，金属化层34被构造成使得其向外表面36具有平坦的顶部几何形状。向外表面36的这种平面几何形状使得表面安装封装件10能够从两侧冷却，因为具有高热导率的接触冷却器(未示出)(如，铜、铝或复合材料散热器)可添加到表面安装封装件10的顶部表面38。根据本发明的一个实施例，并且如图3和4所示，介电顶层40被施加到金属化层34之上方以形成表面安装封装件10的顶部表面38，其中接触冷却器定位成邻近(接触)介电的顶层40，以便在表面安装封装件10的顶部表面38处提供冷却。
现在参看图2-4，表面安装封装件10的底部表面42显示为包括栅极、漏极和源极连接(即，“接头(tab)”)44、46、48以将表面安装封装件10中的半导体装置12连接到外部板或电路载体50。栅极连接44、漏极连接46和源极连接48中的每一个被构造为围绕表面安装模块10紧密构造的宽垫，以有助于减少不期望的电回路。连接44、46、48使得能够形成从电路板50到表面安装封装件10的内部平面的非常紧密的平面电连接，由此形成从电路板50到内部平面的非常短的路径，从而减少表面安装封装件10中的寄生电感。连接44、46、48充当允许将表面安装封装件10焊接到板或电路载体50的连接点。如图3和4所示，漏极连接46和源极连接48电连接到POL系统20的金属互连件32，金属互连件32向下延伸穿过形成于介电层24和粘合剂层22中的通路或开口28。栅极连接44借助于栅极引线52电联接到SiCMOSFET14。
双面陶瓷基板54也设置在表面安装封装件10中且形成表面安装封装件10的底部表面42的一部分。SiC MOSFET14和两个SiC二极管16焊接到双面陶瓷基板54的顶部表面56，而双面陶瓷基板54的底部表面58保持完全或部分暴露以提供从表面安装封装件10向外的有效热传递并且使表面安装封装件10能够焊接到外部板/电路载体50。
根据一个实施例，双面陶瓷基板54被构造为直接敷铜(DBC，direct bond copper)结构，其由陶瓷贴片(例如氧化铝)60构成，铜片62通过直接接合工艺结合到陶瓷贴片的两侧(即，铜图案在陶瓷贴片的晶粒侧上，平衡铜(balancing copper)在非晶粒侧上)。然而，虽然双面陶瓷基板54在上文和下文中被称为“DBC结构54”，但应当认识到，双面陶瓷基板54可由其它材料构成，其中使用铝代替铜作为例如金属层，并且因此这样的实施例被认为在本发明的范围内。因此，术语“DBC结构”在下文中的使用意味着涵盖包括陶瓷贴片(例如，氧化铝)的这样的双面陶瓷基板54：其通过包括硬钎焊或直接粘合技术的任何高温接合工艺将任何合适的金属材料(例如，铜或铝)片材结合到陶瓷贴片两侧。或者，应当认识到，也可以采用其它类似的结构，例如绝缘的金属基板(IMS)结构，该结构提供电绝缘但不具有理想的热导率，并且因此可能需要穿过其中形成的热通道。
在表面安装封装件10中包括DBC结构54用来电隔离/绝缘SiCMOSFET14的底部漏极表面64与外部电路50，同时仍然提供改善的热通道，以将热量传导离开MOSFET的漏极64。DBC结构54将SiCMOSFET背面漏极64构造为与外部电路50物理上分离的“浮动接头”。通过将DBC结构54包括在表面安装封装件10中实现的这种浮动接头构造使得更容易板安装表面安装封装件10，并且解放了设计者，使其不必在进行到电路的剩余部分的高电流连接的同时提供电压隔离。DBC结构54与连接44、46、48结合，在表面安装封装件10上提供了平面的底部表面，从而允许在焊料回流期间附连其它表面安装部件的同时将表面安装封装件10容易地安装和附连到电路板50。
现在参看图5，示出了根据本发明的另一个实施例的表面安装封装件70，其中需要/期望表面安装封装件中的半导体装置12的额外冷却。表面安装封装件70功能类似于图1-4所示表面安装封装件10；然而，表面安装封装件70的构造略微不同于表面安装封装件10的构造。具体而言，表面安装封装件70被构造成使得顶部表面双面陶瓷基板72设置在表面安装封装件70的顶部表面74上以减小通过封装件顶部的热通道的热阻。根据一个实施例，表面安装封装件10的顶侧介电层40(例如，聚酰亚胺层)(图1)被替换成具有比介电层更低的热阻的双面陶瓷基板72(例如，铜-陶瓷-铜DBC结构)，其中双面陶瓷基板72焊接到铜金属化层34。然后可以将顶侧散热器或其它接触冷却器(未示出)添加到双面陶瓷基板72并热连接到其上，同时借助于双面陶瓷基板72与表面安装封装件10电绝缘。半导体装置12的更有效的双面冷却可因此通过实施图5所示表面安装封装件结构而实现。
根据本发明的另一个实施例，应当认识到，图5的表面安装封装件70可被构造为“覆晶(flip-chip)”式模块，该模块使封装件的顶部表面74焊接到外部板或电路载体。也就是说，在表面安装封装件70的顶部表面74上加入顶部表面双面陶瓷基板72，该“加入”通过提供能焊接到电路载体的平的顶部表面74而为表面安装封装件70提供了覆晶封装功能。在其中图5的表面安装封装件70实现为覆晶式模块并且顶部表面74焊接到电路载体的实施例中，应当认识到，铜接头44、46、48将设置在表面安装封装件70的顶部表面74上而不是在封装件的底部表面上(如在图5中当前所示)，使得接头和顶部表面双面陶瓷基板72组合以提供平表面。
现在参看图6，示出了根据本发明的实施例的另外的表面安装封装件80。同样，表面安装封装件80功能类似于图1-4和5所示表面安装封装件10、70；然而，表面安装封装件80的构造与其略有不同。如图6所示，示出了其中单个介电层82作为POL系统84一部分提供的表面安装封装件80。包括仅单个介电层82用来进一步最小化表面安装封装件80的厚度，应当认识到，在封装件厚度的这种最小化和由包括仅单个介电层82导致的POL系统84中的电流密度的增加之间存在折中。
有利地，本发明的实施例因此提供了具有平面互连件和浮动漏极接头的表面安装封装件以减少封装件中的电感回路并且提供了更好的热通道以减小对一个或多个半导体装置和封装件的热应力，同时也使得封装件能够更容易地安装到外部电路。平面封装件中的浮动接头使得更容易将板安装封装件，并且解放了设计者，使其不必在进行到外部电路的剩余部分的高电流连接的同时提供电压隔离。浮动接头还允许设计者为封装件内部的半导体或半导体装置实现好得多的热通道和/或更好的冷却。另外，由于平面封装件包括坚固的直接金属连接而不是引线结合，并且还包括使封装件能够双面冷却的平坦的顶部几何形状，减小了封装件上的热应力。在其中需要额外冷却的表面安装封装件中，通过将材料以这样的方式（即，使得提供从装置顶部到顶侧冷却器的热通道）添加到封装件来实现这样的冷却。本发明的实施例还有利地提供了这样的表面安装封装件：其具有在半导体芯片、封装件的内部连接和板连接之间由包括在其中的平面互连件产生的低电感。所有连接都是平面的并且使用宽的铜带/垫来进行连接。由POL技术实现的此类铜连接和铜通路或开口(其可以模拟半导体晶粒上的钝化（passivation）开口)的使用共同作用，以减小接触电阻并因此减少电压损耗和传导损耗。此外，POL连接是到半导体垫的真正的金属连接并且因此比引线结合更加密实和可靠，引线结合是超声设置的铝线或金线。总之，这使得该封装件可用于高频率和高功率应用。
因此，根据本发明的一个实施例，表面安装封装件包括：至少一个半导体装置，其包括基板，该基板具有形成于其上的多个连接垫；以及功率上覆(POL)封装和互连系统，其围绕至少一个半导体装置形成且被构造成提供表面安装封装件安装到外部电路，其中POL封装和互连系统还包括上覆至少一个半导体装置的第一表面且借助于粘合剂层接合到该第一表面的介电层，其中介电层和粘合剂层包括穿过其中形成的多个通路或开口。POL封装和互连系统还包括：金属互连结构，其延伸通过穿过介电层和粘合剂形成的通路或开口以便电联接到至少一个半导体装置的多个连接垫；金属化层，其形成于金属互连结构上方且包括平坦的平面结构；以及双面陶瓷基板，其定位在与第一表面相对的至少一个半导体装置的第二表面上，双面陶瓷基板被构造成当表面安装封装件接合到其上时使至少一个半导体装置的漏极与外部电路电隔离，并且双面陶瓷基板被进一步构造成将热量传导离开至少一个半导体装置。
根据本发明的另一个实施例，具有构造成安装到外部电路的顶部表面和底部表面的表面安装模块包括一个或多个功率半导体装置和功率上覆(POL)封装和互连系统，POL封装和互连系统围绕一个或多个功率半导体装置形成且被构造成使表面安装模块安装到外部电路。POL封装和互连系统还包括：介电层，其上覆一个或多个功率半导体装置的有源表面；金属化互连结构，其形成于介电层的上方且向下延伸穿过形成于介电层中的开口以便电联接到一个或多个功率半导体装置；以及多个连接垫，其形成于表面安装模块的底部表面上以提供到外部电路的连接，多个连接垫包括宽的平坦的可焊接垫。POL封装和互连系统还包括邻近多个连接垫定位的双面陶瓷基板，其中双面陶瓷基板被构造成在空间上分离和电隔离一个或多个功率半导体装置的浮动接头与外部电路（即，使该浮动接头在空间上与该外部电路分离，并使该浮动接头电隔离该外部电路），同时将热量传导离开一个或多个功率半导体装置并到表面安装模块的外部。金属化互连结构、多个连接垫和双面陶瓷基板为表面安装模块形成多个平面的互连件，该多个平面的互连件最小化该表面安装模块的电感。
根据本发明的又一实施例，表面安装封装件包括一个或多个功率半导体装置和功率上覆(POL)封装和互连系统，POL封装和互连系统围绕一个或多个功率半导体装置形成以提供表面安装封装件到外部电路的安装。POL封装和互连系统在一个或多个功率半导体装置、POL封装和互连系统的内部连接件和外部电路之间形成多个平面的互连件，以便最小化表面安装模块的电感。POL封装和互连系统被构造成当表面安装封装件安装到外部电路时使一个或多个功率半导体装置的背面漏极接头与外部电路电隔离，同时将热量传导离开一个或多个功率半导体装置并到表面安装封装件的外部。
虽然已经结合仅有限数量的实施例详细描述了本发明，但应该容易理解，本发明不限于这样公开的实施例。相反，本发明可以修改以包含任何数量此前没有描述的变型、改动、替换或等同布置，但这些布置与本发明的精神和范围相称。另外，虽然已经描述了本发明的各种实施例，但应当理解，本发明的方面可仅包括所描述的实施例中的一些。因此，本发明不被视为受先前的描述限制，而仅受所附权利要求的范围限制。

Claims (20)

1.一种表面安装封装件，包括：
至少一个半导体装置，所述至少一个半导体装置中的每一个包括具有形成于其上的多个连接垫的基板；以及
功率上覆POL封装和互连系统，其围绕所述至少一个半导体装置形成且被构造以供所述表面安装封装件安装到外部电路，所述POL封装和互连系统包括：
介电层，其上覆所述至少一个半导体装置的第一表面且借助于粘合剂层接合到所述第一表面，所述介电层和粘合剂层包括多个穿过其中形成的通路或开口；
金属互连结构，其延伸通过穿过所述介电层和粘合剂而形成的所述通路或开口，以便电联接到所述至少一个半导体装置的所述多个连接垫；
金属化层，其形成于所述金属互连结构上方，所述金属化层包括平坦的平面结构；以及
双面陶瓷基板，其定位在与所述第一表面相对的所述至少一个半导体装置的第二表面上，所述双面陶瓷基板被构造成当所述表面安装封装件接合到其上时使所述至少一个半导体装置的漏极与所述外部电路电隔离并且被进一步构造成将热量传导离开所述至少一个半导体装置，
其中所述封装和互连系统包括顶部表面和底部表面，底部表面包括可安装到外部电路的平坦表面，
其中所述双面陶瓷基板构成所述封装和互连系统的平坦表面的一部分。
2.根据权利要求1所述的表面安装封装件，其特征在于，所述POL封装和互连系统还包括构造成提供所述表面安装封装件连接到所述外部电路的栅极、源极和漏极连接接头。
3.根据权利要求2所述的表面安装封装件，其特征在于，所述栅极、源极和漏极连接接头包括焊盘。
4.根据权利要求3所述的表面安装封装件，其特征在于，所述栅极、源极和漏极连接接头与所述双面陶瓷基板结合形成所述表面安装封装件的平面的底部表面。
5.根据权利要求2所述的表面安装封装件，其特征在于，所述栅极、源极和漏极连接接头电联接到所述金属互连结构和所述至少一个半导体装置。
6.根据权利要求1所述的表面安装封装件，其特征在于，所述POL封装和互连系统还包括下列中的一个：
介电顶层，其施加在所述金属化层上方；或
顶部表面双面陶瓷基板，其施加在所述金属化层上方，所述顶部表面双面陶瓷基板被构造成减小通过所述表面安装封装件的顶部表面的热通道的热阻。
7.根据权利要求6所述的表面安装封装件，其特征在于，所述介电顶层和所述顶部表面双面陶瓷基板中的所述一个被构造成为所述表面安装封装件提供平坦的顶部表面以适应其到接触冷却器的附连，从而提供所述表面安装封装件的双面冷却。
8.根据权利要求1所述的表面安装封装件，其特征在于，所述双面陶瓷基板包括直接敷铜结构，所述直接敷铜结构包括陶瓷绝缘贴片，所述陶瓷绝缘贴片具有施加在其顶部表面和底部表面中每一个上的铜片。
9.根据权利要求1所述的表面安装封装件，其特征在于，所述至少一个半导体装置包括功率半导体装置。
10.根据权利要求9所述的表面安装封装件，其特征在于，所述至少一个半导体装置包括碳化硅SiC MOSFET和SiC二极管中的至少一个。
11.根据权利要求1所述的表面安装封装件，其特征在于，所述POL封装和互连系统被构造成提供在所述表面安装封装件中的平面连接和到所述表面安装封装件的平面连接以减少在所述表面安装封装件中的电感回路。
12.一种包括构造成安装到外部电路的顶部表面和底部表面的表面安装模块，所述表面安装模块包括：
一个或多个功率半导体装置；以及
功率上覆POL封装和互连系统，其围绕所述一个或多个功率半导体装置形成且被构造成供所述表面安装模块安装到所述外部电路，所述POL封装和互连系统包括：
介电层，其上覆所述一个或多个功率半导体装置的有源表面；
金属化互连结构，其形成于所述介电层上方且向下延伸穿过形成于所述介电层中的开口以便电联接到所述一个或多个功率半导体装置；
多个连接垫，其形成于所述表面安装模块的所述底部表面上以提供到所述外部电路的连接，所述多个连接垫包括宽的平坦的可焊接垫；以及
双面陶瓷基板，其定位成邻近所述多个连接垫，所述双面陶瓷基板被构造成在空间上使所述一个或多个功率半导体装置的浮动接头与所述外部电路分离和使所述一个或多个功率半导体装置的浮动接头与所述外部电路电隔离，同时将热量传导离开所述一个或多个功率半导体装置并传导至所述表面安装模块的外部；
其中所述金属化互连结构、所述多个连接垫和所述双面陶瓷基板为所述表面安装模块形成最小化所述表面安装模块的电感的多个平面的互连件。
13.根据权利要求12所述的表面安装模块，其特征在于，所述多个连接垫包括栅极、源极和漏极连接接头，所述栅极、源极和漏极连接接头与所述双面陶瓷基板结合形成所述表面安装模块的平面的底部表面。
14.根据权利要求12所述的表面安装模块，其特征在于，所述金属化互连结构包括构造成适应接触冷却器到所述表面安装模块的附连的平坦的平面的顶部表面。
15.根据权利要求12所述的表面安装模块，其特征在于，所述POL封装和互连系统还包括施加在所述金属化互连结构上方的介电顶层和顶部表面双面陶瓷基板中的一个，所述顶部表面双面陶瓷基板被构造成减小通过所述表面安装模块的顶部表面的热通道的热阻。
16.根据权利要求12所述的表面安装模块，其特征在于，所述双面陶瓷基板包括直接敷铜结构，所述直接敷铜结构包括：
陶瓷贴片；以及
铜片，其附连到所述陶瓷贴片的相对侧中的每一侧。
17.一种表面安装封装件，包括：
一个或多个功率半导体装置；以及
功率上覆POL封装和互连系统，其围绕所述一个或多个功率半导体装置形成以供所述表面安装封装件安装到外部电路；
其中所述POL封装和互连系统在所述一个或多个功率半导体装置、所述POL封装和互连系统的内部连接件和所述外部电路之间形成多个平面的互连件以便最小化所述表面安装封装件的电感；并且
其中所述POL封装和互连系统被构造成当所述表面安装封装件安装到所述外部电路时使所述一个或多个功率半导体装置的背面漏极接头与所述外部电路电隔离，同时将热量传导离开所述一个或多个功率半导体装置并到所述表面安装封装件的外部。
18.根据权利要求17所述的表面安装封装件，其特征在于，所述POL封装和互连系统包括：
介电层，其上覆所述一个或多个功率半导体装置的第一表面且借助于粘合剂层接合到所述第一表面，所述介电层和粘合剂层包括多个穿过其中形成的通路或开口；
金属互连结构，其延伸通过穿过所述介电层和粘合剂形成的所述通路或开口以便电联接到所述一个或多个功率半导体装置的所述多个连接垫；
金属化层，其形成于所述金属互连结构上方，所述金属化层包括平坦的平面结构；以及
双面陶瓷基板，其定位在与所述第一表面相对的所述至少一个半导体装置的第二表面上，所述双面陶瓷基板被构造成当所述表面安装封装件接合到其上时使所述一个或多个功率半导体装置的漏极与所述外部电路电隔离并且被进一步构造成将热量传导离开所述至少一个半导体装置。
19.根据权利要求18所述的表面安装封装件，其特征在于，所述POL封装和互连系统还包括施加在所述金属化层上方的顶部表面双面陶瓷基板，所述顶部表面双面陶瓷基板被构造成减小通过所述表面安装封装件的顶部表面的热通道的热阻。
20.根据权利要求19所述的表面安装封装件，其特征在于，所述POL封装和互连系统被构造成在所述表面安装封装件上提供平坦的平面的顶部表面和底部表面，以便提供所述表面安装封装件的双面冷却。
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Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE112013007376T5 (de) * 2013-08-28 2016-05-19 Mitsubishi Electric Corporation Halbleitervorrichtung
US9674940B2 (en) 2014-08-14 2017-06-06 Samsung Electronics Co., Ltd. Electronic device and semiconductor package with thermally conductive via
US9613843B2 (en) 2014-10-13 2017-04-04 General Electric Company Power overlay structure having wirebonds and method of manufacturing same
US9583482B2 (en) 2015-02-11 2017-02-28 Monolith Semiconductor Inc. High voltage semiconductor devices and methods of making the devices
US9893646B2 (en) 2015-09-30 2018-02-13 General Electric Company System for a low profile, low inductance power switching module
DE102016219174A1 (de) * 2015-10-07 2017-04-13 Ceramtec Gmbh Zweiseitig gekühlter Schaltkreis
KR102382635B1 (ko) * 2016-06-09 2022-04-05 매그나칩 반도체 유한회사 전력 반도체의 웨이퍼 레벨 칩 스케일 패키지 및 제조 방법
KR101905995B1 (ko) 2016-11-09 2018-10-10 현대자동차주식회사 양면냉각형 파워모듈
US10804115B2 (en) 2017-08-03 2020-10-13 General Electric Company Electronics package with integrated interconnect structure and method of manufacturing thereof
US10541209B2 (en) 2017-08-03 2020-01-21 General Electric Company Electronics package including integrated electromagnetic interference shield and method of manufacturing thereof
US10541153B2 (en) 2017-08-03 2020-01-21 General Electric Company Electronics package with integrated interconnect structure and method of manufacturing thereof
EP3534394A1 (en) 2018-02-28 2019-09-04 Infineon Technologies Austria AG Semiconductor package and method of manufacturing a semiconductor package
US11538769B2 (en) 2018-12-14 2022-12-27 General Electric Company High voltage semiconductor devices having improved electric field suppression
US10892237B2 (en) 2018-12-14 2021-01-12 General Electric Company Methods of fabricating high voltage semiconductor devices having improved electric field suppression
US11177804B2 (en) * 2018-12-20 2021-11-16 Sanko Tekstil Isletmeleri San. Ve Tic. A.S. Wearable touch sensitive garment
US11398445B2 (en) 2020-05-29 2022-07-26 General Electric Company Mechanical punched via formation in electronics package and electronics package formed thereby
US11950394B2 (en) 2021-10-12 2024-04-02 Ge Aviation Systems Llc Liquid-cooled assembly and method
US20230223312A1 (en) * 2022-01-11 2023-07-13 Infineon Technologies Ag Semiconductor package having a thermally and electrically conductive spacer
CN114400210B (zh) * 2022-01-13 2024-03-05 西安交通大学 一种双面散热芯片倒装的气密性耐高温封装结构

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5637922A (en) * 1994-02-07 1997-06-10 General Electric Company Wireless radio frequency power semiconductor devices using high density interconnect
US20100230800A1 (en) * 2009-03-13 2010-09-16 Richard Alfred Beaupre Double side cooled power module with power overlay
US20110266665A1 (en) * 2010-04-30 2011-11-03 General Electric Company Press-pack module with power overlay interconnection
CN202042481U (zh) * 2011-03-24 2011-11-16 比亚迪股份有限公司 一种功率模块
CN102740604A (zh) * 2012-07-12 2012-10-17 苏州衡业新材料科技有限公司 制备电子电路绝缘金属基板的方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5959357A (en) * 1998-02-17 1999-09-28 General Electric Company Fet array for operation at different power levels
US6306680B1 (en) 1999-02-22 2001-10-23 General Electric Company Power overlay chip scale packages for discrete power devices
US6994897B2 (en) 2002-11-15 2006-02-07 General Electric Company Method of processing high-resolution flex circuits with low distortion
JP4268560B2 (ja) * 2004-04-27 2009-05-27 大日本印刷株式会社 電子部品内蔵モジュールおよびその製造方法
US7262444B2 (en) 2005-08-17 2007-08-28 General Electric Company Power semiconductor packaging method and structure
JP4550732B2 (ja) * 2005-12-20 2010-09-22 株式会社椿本チエイン 固体潤滑無給油チェーン
US8049338B2 (en) * 2006-04-07 2011-11-01 General Electric Company Power semiconductor module and fabrication method
DE102006021959B4 (de) * 2006-05-10 2011-12-29 Infineon Technologies Ag Leistungshalbleiterbauteil und Verfahren zu dessen Herstellung
US8138587B2 (en) * 2008-09-30 2012-03-20 Infineon Technologies Ag Device including two mounting surfaces
WO2010147202A1 (ja) * 2009-06-19 2010-12-23 株式会社安川電機 電力変換装置
CN102484109B (zh) * 2009-08-03 2014-12-10 株式会社安川电机 电力变换装置
US20110209908A1 (en) * 2009-08-06 2011-09-01 Advanced Chip Engineering Technology Inc. Conductor package structure and method of the same
US8120158B2 (en) * 2009-11-10 2012-02-21 Infineon Technologies Ag Laminate electronic device
JP6033215B2 (ja) * 2011-03-29 2016-11-30 ローム株式会社 パワーモジュール半導体装置
WO2012133098A1 (ja) * 2011-03-31 2012-10-04 日本ゼオン株式会社 半導体装置及びその製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5637922A (en) * 1994-02-07 1997-06-10 General Electric Company Wireless radio frequency power semiconductor devices using high density interconnect
US20100230800A1 (en) * 2009-03-13 2010-09-16 Richard Alfred Beaupre Double side cooled power module with power overlay
US20110266665A1 (en) * 2010-04-30 2011-11-03 General Electric Company Press-pack module with power overlay interconnection
CN202042481U (zh) * 2011-03-24 2011-11-16 比亚迪股份有限公司 一种功率模块
CN102740604A (zh) * 2012-07-12 2012-10-17 苏州衡业新材料科技有限公司 制备电子电路绝缘金属基板的方法

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