JP2014099606A - 分離タブを備える低プロファイル表面実装パッケージ - Google Patents
分離タブを備える低プロファイル表面実装パッケージ Download PDFInfo
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- JP2014099606A JP2014099606A JP2013232641A JP2013232641A JP2014099606A JP 2014099606 A JP2014099606 A JP 2014099606A JP 2013232641 A JP2013232641 A JP 2013232641A JP 2013232641 A JP2013232641 A JP 2013232641A JP 2014099606 A JP2014099606 A JP 2014099606A
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- Prior art keywords
- surface mount
- mount package
- package
- semiconductor device
- double
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- 239000004065 semiconductor Substances 0.000 claims abstract description 112
- 239000000758 substrate Substances 0.000 claims abstract description 56
- 239000000919 ceramic Substances 0.000 claims abstract description 51
- 238000004806 packaging method and process Methods 0.000 claims abstract description 41
- 229910052751 metal Inorganic materials 0.000 claims abstract description 22
- 239000002184 metal Substances 0.000 claims abstract description 22
- 238000001816 cooling Methods 0.000 claims abstract description 14
- 238000001465 metallisation Methods 0.000 claims abstract description 12
- 239000010410 layer Substances 0.000 claims description 60
- 229910052802 copper Inorganic materials 0.000 claims description 23
- 239000010949 copper Substances 0.000 claims description 23
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 22
- 239000012790 adhesive layer Substances 0.000 claims description 17
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 10
- 238000007667 floating Methods 0.000 claims description 9
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 7
- 239000000284 extract Substances 0.000 claims description 3
- 229910000679 solder Inorganic materials 0.000 claims description 2
- 238000009434 installation Methods 0.000 claims 1
- 230000003071 parasitic effect Effects 0.000 abstract description 5
- 238000000034 method Methods 0.000 description 7
- 239000000463 material Substances 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 230000008646 thermal stress Effects 0.000 description 3
- 229920000106 Liquid crystal polymer Polymers 0.000 description 2
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 description 2
- 238000005553 drilling Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 229920003223 poly(pyromellitimide-1,4-diphenyl ether) Polymers 0.000 description 2
- 229920001343 polytetrafluoroethylene Polymers 0.000 description 2
- 239000004810 polytetrafluoroethylene Substances 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 229920003295 Radel® Polymers 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229920004738 ULTEM® Polymers 0.000 description 1
- 229920001646 UPILEX Polymers 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 229940127554 medical product Drugs 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229920002492 poly(sulfone) Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920006254 polymer film Polymers 0.000 description 1
- -1 polytetrafluoroethylene Polymers 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
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Abstract
【解決手段】表面実装パッケージ10は、少なくとも1つの半導体装置12と、外部回路への表面実装パッケージの実装を可能にするように構成され、少なくとも1つの半導体装置の周囲に形成される、POLパッケージング及び相互接続システムとを含む。POLパッケージング及び相互接続システムは、(1つ又は複数の)半導体装置の第1面に重ねられた誘電層24と、半導体装置の接続パッドに電気的に結合されるよう、誘電層を貫通して形成されたビアホール28を通じて延在する金属相互接続構造32とを含む。平板状構造を備える金属化層34が金属相互接続構造上に形成され、両面セラミック基板は半導体装置の第2面上に位置し、表面実装パッケージが接合されたときに外部回路から半導体装置のドレインを電気的に絶縁し、半導体装置から熱を取り出すように構成されている。
【選択図】図3
Description
Claims (20)
- 表面実装パッケージであって、
少なくとも1つの半導体装置であって、複数の接続パッドが形成されている基板をその各々が備える、少なくとも1つの半導体装置と、
前記少なくとも1つの半導体装置の周囲に形成され、外部回路への前記表面実装パッケージの実装を提供するように構成された、パワーオーバレイ(POL)パッケージング及び相互接続システムであって、
前記少なくとも1つの半導体装置の第1面に重ねられて接着層によってこれに接合されている誘電層であって、前記誘電層及び接着層は、これらを貫通して形成された複数のビアホールを含む、誘電層と、
前記少なくとも1つの半導体装置の前記複数の接続パッドに電気的に結合されるように、前記誘電層及び接着層を貫通して形成された前記ビアホールを通じて延在する金属相互接続構造と、
前記金属相互接続構造上に形成されて平板状構造を備える金属化層と、
前記第1面の反対側の前記少なくとも1つの半導体装置の第2面上に位置する両面セラミック基板であって、前記表面実装パッケージが接合されたときに前記外部回路から前記少なくとも1つの半導体装置のドレインを電気的に絶縁するように構成されており、更に前記少なくとも1つの半導体装置から熱を取り出すように構成されている、両面セラミック基板と、
を備えるPOLパッケージング及び相互接続システムと、
を備える、表面実装パッケージ。 - 前記POLパッケージング及び相互接続システムは、前記表面実装パッケージから前記外部回路への接続を提供するように構成された、ゲート、ソース、及びドレイン接続タブを更に備える、請求項1に記載の表面実装パッケージ。
- 前記ゲート、ソース、及びドレイン接続タブは、半田パッドを含む、請求項2に記載の表面実装パッケージ。
- 前記ゲート、ソース、及びドレイン接続タブは、前記両面セラミック基板と一緒に、前記表面実装パッケージの平坦な底面を形成する、請求項3に記載の表面実装パッケージ。
- 前記ゲート、ソース、及びドレイン接続タブは、前記金属相互接続構造及び前記少なくとも1つの半導体装置に電気的に結合されている、請求項2に記載の表面実装パッケージ。
- 前記POLパッケージング及び相互接続システムは、
前記金属化層上に塗布された誘電最上層、又は
前記金属化層上に塗布された上面両面セラミック基板であって、前記表面実装パッケージの上面を通る熱経路の熱抵抗を低減するように構成されている、上面両面セラミック基板、
のうちの1つを更に備える、請求項1に記載の表面実装パッケージ。 - 前記誘電最上層及び前記上面両面セラミック基板のうちの前記1つは、接触式冷却器の取り付けを適合させるために、前記表面実装パッケージのための平坦な上面を呈するように構成されており、これによって、前記表面実装パッケージの両面冷却を提供する、請求項6に記載の表面実装パッケージ。
- 前記両面セラミック基板は、その上面及び底面に銅シートが塗布されたセラミック絶縁タイルを含む直接接合銅(DBC)構造を備える、請求項1に記載の表面実装パッケージ。
- 前記少なくとも1つの半導体装置は、高周波又は高パワー半導体装置を含む、請求項1に記載の表面実装パッケージ。
- 前記少なくとも1つの半導体装置は、炭化ケイ素(SiC)MOSFET及びSiCダイオードのうちの少なくとも1つを備える、請求項9に記載の表面実装パッケージ。
- 前記POLパッケージング及び相互接続システムは、前記表面実装パッケージ内のインダクタンスループを低減するために、前記表面実装パッケージに、及びその内部に平坦な接続を提供するように構成されている、請求項1に記載の表面実装パッケージ。
- 外部回路に実装されるように構成された上面及び底面を含む表面実装モジュールにおいて、
1つ以上のパワー半導体装置と、
前記1つ以上のパワー半導体装置の周囲に形成され、前記外部回路への前記表面実装モジュールの実装を提供するように構成された、パワーオーバレイ(POL)パッケージング及び相互接続システムであって、
前記1つ以上のパワー半導体装置の活性面に重ねられた誘電層と、
前記誘電層上に形成され、前記1つ以上のパワー半導体装置に電気的に結合されるように、前記誘電層に形成された開口部を通じて下方に延在する、金属化相互接続構造と、
前記外部回路への接続を提供するために前記表面実装モジュールの前記底面に形成された複数の接続パッドであって、幅広で平坦な半田付け可能パッドを含む、複数の接続パッドと、
前記複数の接続パッドに隣接して位置する両面セラミック基板であって、前記1つ以上のパワー半導体装置から熱を取り出して前記表面実装モジュールから追い出しながら、前記1つ以上のパワー半導体装置のフローティングタブを前記外部回路から空間的に分離して電気的に絶縁するように構成されている、両面セラミック基板と、
を備えるパワーオーバレイ(POL)パッケージング及び相互接続システムと、
を備え、
前記金属化相互接続構造、前記複数の接続パッド、及び前記両面セラミック基板は、前記表面実装モジュールのインダクタンスを最小化する、前記表面実装モジュールのための複数の平面相互接続を形成する、表面実装モジュール。 - 前記複数の接続パッドは、前記両面セラミック基板と一緒になって前記表面実装モジュールの平坦な底面を形成する、ゲート、ソース、及びドレイン接続タブを備える、請求項12に記載の表面実装モジュール。
- 前記金属化相互接続構造は、前記表面実装モジュールへの接触式冷却器の取り付けを適合させるように構成された、平面状の上面を備える、請求項12に記載の表面実装モジュール。
- 前記POLパッケージング及び相互接続システムは、前記金属化相互接続構造上に塗布された誘電最上層及び上面両面セラミック基板を更に備え、前記上面両面セラミック基板は、前記表面実装モジュールの上面を通る熱経路の熱抵抗を低減するように構成されている、請求項12に記載の表面実装モジュール。
- 前記両面セラミック基板は、
セラミックタイルと、
前記セラミックタイルの対向面の各面に取り付けられた銅シートと、
を含む直接接合銅(DBC)構造を備える、請求項12に記載の表面実装モジュール。 - 表面実装パッケージにおいて、
1つ以上のパワー半導体装置と、
外部回路への前記表面実装パッケージの実装を提供するために前記少なくとも1つの半導体装置の周囲に形成されたパワーオーバレイ(POL)パッケージング及び相互接続システムと、を備え、
前記POLパッケージング及び相互接続システムは、前記表面実装パッケージのインダクタンスを最小化するように、前記1つ以上のパワー半導体装置と、前記POLパッケージング及び相互接続システムの内部接続と、前記外部回路との間の複数の平面相互接続を形成し、
前記POLパッケージング及び相互接続システムは、前記1つ以上のパワー半導体装置から熱を取り出して前記表面実装パッケージから追い出しながら、前記表面実装パッケージが前記外部回路に実装されたときに前記1つ以上のパワー半導体装置の裏面ドレインタブを前記外部回路から電気的に絶縁するように構成されている、表面実装パッケージ。 - 前記POLパッケージング及び相互接続システムは、
前記1つ以上のパワー半導体装置の第1面に重ねられて接着層によってこれに接合されている誘電層であって、前記誘電層及び接着層は、これらを貫通して形成された複数のビアホールを含む、誘電層と、
前記1つ以上のパワー半導体装置の複数の接続パッドに電気的に結合されるように、前記誘電層及び接着層を貫通して形成されたビアホールを通じて延在する金属相互接続構造と、
前記金属相互接続構造上に形成されて平板状構造を備える金属化層と、
前記第1面の反対側の前記少なくとも1つの半導体装置の第2面上に位置する両面セラミック基板であって、前記表面実装パッケージが接合されたときに前記外部回路から前記少なくとも1つのパワー半導体装置のドレインを電気的に絶縁するように構成されており、更に前記少なくとも1つの半導体装置から熱を取り出すように構成されている、両面セラミック基板と、
を備える、請求項17に記載の表面実装パッケージ。 - 前記POLパッケージング及び相互接続システムは、前記金属化層上に塗布された上面両面セラミック基板を更に備え、前記上面両面セラミック基板は、前記表面実装パッケージの上面を通る熱経路の熱抵抗を低減するように構成されている、請求項18に記載の表面実装パッケージ。
- 前記POLパッケージング及び相互接続システムは、前記表面実装パッケージの両面冷却を提供するように、前記表面実装パッケージ上に平坦な上面及び底面を呈するように構成されている、請求項19に記載の表面実装パッケージ。
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
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Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6306680B1 (en) * | 1999-02-22 | 2001-10-23 | General Electric Company | Power overlay chip scale packages for discrete power devices |
JP2005317585A (ja) * | 2004-04-27 | 2005-11-10 | Dainippon Printing Co Ltd | 電子部品内蔵モジュールおよびその製造方法 |
JP2007053379A (ja) * | 2005-08-17 | 2007-03-01 | General Electric Co <Ge> | パワー半導体パッケージングの方法および構造 |
JP2007170493A (ja) * | 2005-12-20 | 2007-07-05 | Tsubakimoto Chain Co | 固体潤滑無給油チェーン |
US20070235810A1 (en) * | 2006-04-07 | 2007-10-11 | Delgado Eladio C | Power semiconductor module and fabrication method |
JP2010219529A (ja) * | 2009-03-13 | 2010-09-30 | General Electric Co <Ge> | 両面冷却式電力用被覆層付き電力モジュール |
WO2010147202A1 (ja) * | 2009-06-19 | 2010-12-23 | 株式会社安川電機 | 電力変換装置 |
WO2011016360A1 (ja) * | 2009-08-03 | 2011-02-10 | 株式会社安川電機 | 電力変換装置 |
US20110209908A1 (en) * | 2009-08-06 | 2011-09-01 | Advanced Chip Engineering Technology Inc. | Conductor package structure and method of the same |
WO2012133098A1 (ja) * | 2011-03-31 | 2012-10-04 | 日本ゼオン株式会社 | 半導体装置及びその製造方法 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5637922A (en) | 1994-02-07 | 1997-06-10 | General Electric Company | Wireless radio frequency power semiconductor devices using high density interconnect |
US5959357A (en) * | 1998-02-17 | 1999-09-28 | General Electric Company | Fet array for operation at different power levels |
US6994897B2 (en) | 2002-11-15 | 2006-02-07 | General Electric Company | Method of processing high-resolution flex circuits with low distortion |
DE102006021959B4 (de) * | 2006-05-10 | 2011-12-29 | Infineon Technologies Ag | Leistungshalbleiterbauteil und Verfahren zu dessen Herstellung |
US8138587B2 (en) * | 2008-09-30 | 2012-03-20 | Infineon Technologies Ag | Device including two mounting surfaces |
US8120158B2 (en) * | 2009-11-10 | 2012-02-21 | Infineon Technologies Ag | Laminate electronic device |
US8531027B2 (en) * | 2010-04-30 | 2013-09-10 | General Electric Company | Press-pack module with power overlay interconnection |
CN202042481U (zh) * | 2011-03-24 | 2011-11-16 | 比亚迪股份有限公司 | 一种功率模块 |
JP6033215B2 (ja) * | 2011-03-29 | 2016-11-30 | ローム株式会社 | パワーモジュール半導体装置 |
CN102740604A (zh) * | 2012-07-12 | 2012-10-17 | 苏州衡业新材料科技有限公司 | 制备电子电路绝缘金属基板的方法 |
-
2012
- 2012-11-13 US US13/675,084 patent/US9337163B2/en active Active
-
2013
- 2013-10-30 TW TW102139414A patent/TWI621240B/zh active
- 2013-11-05 EP EP13191628.0A patent/EP2731128B1/en active Active
- 2013-11-11 JP JP2013232641A patent/JP6310677B2/ja active Active
- 2013-11-13 CN CN201310572275.8A patent/CN103811433B/zh active Active
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6306680B1 (en) * | 1999-02-22 | 2001-10-23 | General Electric Company | Power overlay chip scale packages for discrete power devices |
JP2005317585A (ja) * | 2004-04-27 | 2005-11-10 | Dainippon Printing Co Ltd | 電子部品内蔵モジュールおよびその製造方法 |
JP2007053379A (ja) * | 2005-08-17 | 2007-03-01 | General Electric Co <Ge> | パワー半導体パッケージングの方法および構造 |
JP2007170493A (ja) * | 2005-12-20 | 2007-07-05 | Tsubakimoto Chain Co | 固体潤滑無給油チェーン |
US20070235810A1 (en) * | 2006-04-07 | 2007-10-11 | Delgado Eladio C | Power semiconductor module and fabrication method |
JP2010219529A (ja) * | 2009-03-13 | 2010-09-30 | General Electric Co <Ge> | 両面冷却式電力用被覆層付き電力モジュール |
WO2010147202A1 (ja) * | 2009-06-19 | 2010-12-23 | 株式会社安川電機 | 電力変換装置 |
WO2011016360A1 (ja) * | 2009-08-03 | 2011-02-10 | 株式会社安川電機 | 電力変換装置 |
US20110209908A1 (en) * | 2009-08-06 | 2011-09-01 | Advanced Chip Engineering Technology Inc. | Conductor package structure and method of the same |
WO2012133098A1 (ja) * | 2011-03-31 | 2012-10-04 | 日本ゼオン株式会社 | 半導体装置及びその製造方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9674940B2 (en) | 2014-08-14 | 2017-06-06 | Samsung Electronics Co., Ltd. | Electronic device and semiconductor package with thermally conductive via |
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US20140133104A1 (en) | 2014-05-15 |
CN103811433B (zh) | 2019-01-01 |
EP2731128A3 (en) | 2018-02-07 |
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