TWI703681B - 功率覆蓋結構及其製造方法 - Google Patents

功率覆蓋結構及其製造方法 Download PDF

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TWI703681B
TWI703681B TW107117243A TW107117243A TWI703681B TW I703681 B TWI703681 B TW I703681B TW 107117243 A TW107117243 A TW 107117243A TW 107117243 A TW107117243 A TW 107117243A TW I703681 B TWI703681 B TW I703681B
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semiconductor device
conductive
coupled
layer
thermally conductive
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TW201830590A (zh
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維盧派克夏 格達艾朗
辛夫 喬罕夏卡堤
艾倫 麥克考奈利保羅
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美商奇異電器公司
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Abstract

一種功率覆蓋(POL)結構包含一POL子模組。該POL子模組包含一介電層及一半導體裝置，該半導體裝置具有附接至該介電層之一頂部表面。該半導體裝置之該頂部表面具有形成於其上之至少一接觸襯墊。該POL子模組亦包含延伸穿過該介電層且電耦合至該半導體裝置之該至少一接觸襯墊之一金屬互連結構。一導電墊片耦合至該半導體裝置之一底部表面，且一導熱介面之一第一側耦合至該導電墊片。一散熱器耦合至該電絕緣導熱介面之一第二側。

Description

功率覆蓋結構及其製造方法
本發明之實施例一般而言係關於用於封裝半導體裝置之結構及方法，且特定而言係關於包含一改良導熱介面之一功率覆蓋(POL)封裝結構。 功率半導體裝置係在功率電子電路(諸如(例如)，開關式電源供應器)中用作為開關或整流器之半導體裝置。大多數功率半導體裝置僅用於整流模式(即，其等不是開就是關)中，且因此最佳用於此。許多功率半導體裝置用於高電壓功率應用中且經設計以承載大量電流且支撐一大電壓。在使用中，高電壓功率半導體裝置藉由一功率覆蓋(POL)封裝及互連系統連接至一外部電路。 圖1中展示一先前技術功率覆蓋(POL)結構10之大致結構。POL結構10之標準製造程序通常開始於將一或多個功率半導體裝置12藉由一黏著劑16放置在一介電層14上。接著將金屬互連件18 (例如，銅互連件)電鍍在介電層14上以形成至功率半導體裝置12之一直接金屬性連接。金屬互連件18可係一低外形(例如，小於200微米厚)、平坦互連結構之形式，其提供至功率半導體裝置12且來自功率半導體裝置12之一輸入/輸出(I/O)系統20之形成。為連接至一外部電路，諸如(例如)藉由製造至一印刷電路板之一二級互連，當前POL封裝使用焊料球柵格陣列(BGA)或平台柵格陣列(LGA)。 一散熱器22通常亦裝納於POL結構10中以提供移除由半導體裝置12產生之熱且保護裝置12免於外部環境之一方式。散熱器22使用一直接接合銅(DBC)基板24熱耦合至裝置12。如所示，DBC基板24位於半導體裝置12之上部表面與散熱器22之下部表面之間。 DBC基板24係一預製組件，其包含一非有機陶瓷基板26 (諸如(例如)，氧化鋁)，其中上部銅薄片28及下部銅薄片30經由一直接接合銅介面或硬焊層31接合至其兩側。在DBC基板24附接至半導體裝置12之前，圖案化DBC基板24之下部銅薄片30以形成數個導電接觸區域。一典型DBC基板可具有接近1 mm之一整體厚度。 在POL結構10之製造程序期間，將焊料32施覆至半導體裝置12之表面。接著將DBC基板24降低在焊料32上以使下部銅薄片30之經圖案化部分與焊料32對準。在將DBC基板24耦合至半導體裝置12之後，使用一底部填充技術將一介電有機材料34施覆在黏著層16與DBC基板24之間之空間中以形成一POL子模組36。接著將一導熱襯墊或導熱膏38施覆至DBC基板24之上部銅層28。 在一POL結構10中使用一DBC基板具有許多限制。首先，DBC基板之銅及陶瓷材料之材料特性對DBC基板之設計具有固有限制。例如，歸因於陶瓷之固有硬度及DBC基板24之銅與陶瓷材料之熱膨脹係數之差異，必須保持銅薄片28、30相對較薄以避免由銅材料中之溫度之大擺動引起之放置在陶瓷上之不容許應力。此外，由於面對半導體裝置12之DBC基板24之下部銅層之表面係平坦的，故DBC基板24不利於製造具有不同高度之半導體裝置之一POL封裝。 再者，製造DBC基板相對較昂貴且DBC基板係一預製組件。因為DBC基板24係一預製組件，所以基於施覆至陶瓷基板26之銅箔層之厚度預判銅薄片28、30之厚度。再者，因為DBC基板24係在與POL結構之剩餘組件之組裝之前製造，所以在DBC基板24耦合至半導體裝置12之後使用一底部填充技術施覆圍繞半導體裝置12之介電填充物或環氧樹脂基板。此底部填充技術耗費時間且可導致POL結構內之非所要空隙。 因此，期望提供具有克服倂有一DBC基板之已知POL結構之前述結構及處理限制之一改良導熱介面之一POL結構。進一步期望考量不同厚度之半導體裝置之此一POL結構同時減小POL結構之成本。
本發明之實施例藉由提供消除將一DBC基板用作為一POL子模組與一散熱器之間之一導熱介面之一功率覆蓋(POL)結構克服前述缺點。在半導體裝置與散熱器之間提供包含考量各種高度之半導體裝置之導電墊片之一改良導熱介面。 根據本發明之一態樣，一功率覆蓋(POL)結構包含一POL子模組。POL子模組包含一介電層及具有附接至介電層之一頂部表面之一半導體裝置。半導體裝置之頂部表面具有形成於其上之至少一接觸襯墊。POL子模組亦包含延伸穿過介電層且電耦合至半導體裝置之至少一接觸襯墊之一金屬互連結構。一導電墊片耦合至半導體裝置之一底部表面，且一導熱介面之一第一側耦合至導電墊片。一散熱器耦合至電絕緣導熱介面之一第二側。 根據本發明之另一態樣，形成一功率覆蓋(POL)結構之一方法包含：提供一半導體裝置、將半導體裝置之一第一表面貼附至一介電層、穿過介電層形成通孔及形成延伸穿過介電層中之通孔之一金屬互連結構以電連接至半導體裝置。該方法亦包含將一導電墊片之一第一表面貼附至半導體裝置之一第二表面及在導電墊片之一第二表面之頂上形成一導熱介面。此外，該方法包含在無一直接接合銅(DBC)基板位於一散熱器與導電墊片之間之情況下將散熱器熱耦合至導電墊片。 根據本發明之又一態樣，一功率覆蓋(POL)封裝結構包含一POL子模組。POL子模組包含：一介電層；一第一半導體裝置，其附接至介電層；及一互連結構，其電耦合至第一半導體裝置之一第一側。互連結構延伸穿過介電層以電連接至第一半導體裝置上之至少一接觸襯墊。一第一導電墊片具有耦合至第一半導體裝置之一第二側之一底部表面，且一導熱介面在無一直接接合銅(DBC)基板位於導熱介面與第一導電墊片之間之情況下耦合至第一導電墊片之一頂部表面。一散熱器直接耦合至導熱介面。 根據本發明之又一態樣，一半導體裝置封裝包含：一第一半導體裝置；一第二半導體裝置，其具有大於第一半導體裝置之一厚度之一厚度；及一絕緣基板，其耦合至第一半導體裝置及第二半導體裝置之第一表面。一金屬化層延伸穿過絕緣基板，使得金屬化層之一第一表面耦合至第一半導體裝置及第二半導體裝置之接觸襯墊。具有一第一側之一第一導電墊片經由一導電接觸層耦合至第一半導體裝置；具有一第一側之一第二導電墊片經由導電接觸層耦合至第一半導體裝置。第一導電墊片具有大於第二導電墊片之一厚度之一厚度，且第一導電墊片與第二導電墊片之第二側共面。 根據本發明之又一實施例，一半導體裝置封裝包含：一介電層，其具有穿過介電層形成之複數個通孔；及一半導體裝置，其具有耦合至介電層之一頂部表面之一第一表面。半導體裝置封裝亦包含耦合至介電層之一底部表面之一金屬互連結構。金屬互連結構延伸穿過介電層之複數個通孔以連接至半導體裝置之第一表面。半導體裝置封裝亦包含一導電墊片，其具有耦合至半導體裝置之一第二表面之一底部表面；及一有機導熱介面，其在無一直接接合銅(DBC)基板位於有機導熱介面與導電墊片之間之情況下耦合至導電墊片之一頂部表面。 自下文結合隨附圖式提供之本發明之較佳實施例之詳細描述將更易於明白此等及其他優點及特徵。
相關申請案之交叉參考 本申請案主張2013年3月14日申請之美國臨時專利申請案第61/784,834號之優先權，該案之揭示內容以引用方式併入本文中。 本發明之實施例提供一種具有一改良導熱介面裝納於其中之功率覆蓋(POL)結構，及一種形成此一POL結構之方法。POL結構包含考量各種高度之半導體裝置之導電墊片及增加囊封材料及方法之選項之一導熱介面。 參考圖2，展示根據本發明之一實施例之一半導體裝置總成或功率覆蓋(POL)結構40。POL結構40包含其中具有根據各種實施例可係一晶粒、二極體或其他功率電子裝置之形式之一或多個半導體裝置43、44、45之一POL子模組42。如圖2中所示，POL子模組42中設置三個半導體裝置43、44、45，然而，認知POL子模組42中可包含大於或小於半導體裝置43、44、45之數目之半導體裝置。除半導體裝置43、44、45之外，POL子模組42亦可包含任何數目之額外電路組件46，諸如(例如)一閘極驅動器。 半導體裝置43、44、45藉由一黏著層50耦合至一介電層48。根據各種實施例，介電層48可係一疊片或一薄膜形式，且可由複數種介電材料(諸如，Kapton®、Ultem®、聚四氟乙烯(PTFE)、Upilex®、聚碸材料(例如，Udel®、Radel®))之一者或另一聚合物薄膜(諸如，一液晶聚合物(LCP)或一聚醯亞胺材料)形成。 POL子模組42亦包含一金屬化層或互連結構52，該金屬化層或互連結構52藉由延伸穿過形成於介電層48中之通孔56以連接至各自半導體裝置43、44、45上之接觸襯墊58之一金屬互連件54而形成至半導體裝置43、44、45之一直接金屬性連接。 POL子模組42進一步包含一或多個導電板片或墊片60，該等導電板片或墊片60使用一導熱且導電接觸層62固定至半導體裝置43、44、45。根據多種實施例，導電接觸層62可係(例如)一焊接材料、一導電黏著劑，或一經燒結銀。導電墊片60係一金屬或合金材料(諸如(例如)，銅、鋁、鉬或其等之組合(諸如銅鉬或銅鎢))，及複合物(諸如，鋁矽、鋁碳化矽、鋁石墨、銅石墨及類似物)。 一介電填充材料64亦設置在POL子模組42中，以填充POL子模組42中半導體裝置43、44、45與導電墊片60之間及周圍之縫隙，以便將額外結構完整性提供至POL子模組42。根據多種實施例，介電填充材料64可係一聚合材料形式，諸如(例如)，一底部填充物(例如，毛細管底部填充物或非流動性底部填充物)、囊封劑、聚矽氧，或一模製化合物。 POL結構40亦包含一散熱器66以促進半導體裝置43、44、45之冷卻。散熱器66包括具有一高導熱性之一材料，諸如，銅、鋁，或一複合材料。散熱器66藉由形成於導電墊片60及介電填充材料64上方之一導熱介面基板或層68耦合至POL子模組42。 導熱介面層68係一導熱、電絕緣聚合或有機材料，諸如(例如)，一導熱襯墊、一導熱糊、一導熱膏，或一導熱黏著劑。導熱介面層68將散熱器66與導電墊片60電隔離。根據一實施例，導熱介面層68包括導電填充物、粒子，或懸浮在一樹脂或環氧樹脂基質中之纖維。例如，導熱介面層68可係填充有導熱、電絕緣填充物(諸如氧化鋁及/或氮化硼)之一環氧樹脂或矽樹脂。根據一實施例，導熱介面層68具有接近100 µm之一厚度。然而，熟習此項技術者將認知導熱介面層68之厚度可基於設計規格變化。導熱介面層68相較於一DBC基板提供優越熱效能，其係因為導熱介面層68不經受裝納於DBC基板中之陶瓷層之熱阻。 在其中導熱介面層68係一導熱糊、一導熱膏，或一導熱襯墊(諸如(例如)有機材料之一預形成薄片或薄膜)之實施例中，散熱器66在POL子模組42周邊周圍之數個位置處使用螺絲釘或其他緊固裝置(未展示)固定至POL子模組42，引起導熱介面層68夾置於導電墊片60與散熱器66之間。或者，在其中導熱介面層68係一聚合黏著劑之實施例中，在散熱器66位於導熱介面層68頂上之後，導熱介面層68在一膠黏狀態中被施覆至POL子模組42且固化，藉此在無額外緊固件之情況下將散熱器66接合至POL子模組42。 POL子模組42亦包含一輸入輸出(I/O)連接70以使POL結構40能夠表面安裝至一外部電路(諸如，一印刷電路板(PCB))，如關於圖5更詳細描述。根據一例示性實施例，儘管亦可使用其他合適二級焊料互連件(諸如，平台柵格陣列(LGA)襯墊)，然而I/O連接70係由經組態以附接/貼附至PCB以將POL結構40電耦合至PCB之球柵格陣列(BGA)焊料凸塊72形成。BGA焊料凸塊72提供在高應力條件下抵抗故障之一高可靠互連結構。如圖2中繪示，焊料凸塊72位於POL子模組42之一焊料遮罩層74中形成之開口中。 現參考圖3，展示根據本發明之一替代實施例之一POL結構76及POL子模組78。POL結構76及POL子模組78包含類似於圖2之POL結構40及POL子模組42中展示之組件之許多組件，且因此亦將使用用以指示圖2中之組件之數字指示圖3中之類似組件。 如所示，POL子模組78包含位於導電墊片60與散熱器66之間之一多層導熱介面80。多層導熱介面80包含一第一導熱介面層82、一陶瓷絕緣層84，及一第二導熱介面層86。POL子模組78與散熱器66之間之陶瓷絕緣層84之內含物將額外電隔離提供給高電壓應用。絕緣層84可由一陶瓷材料(諸如(例如)，氧化鋁或氮化鋁)構造。 如所示，第一導熱介面層82夾置於導電墊片60與陶瓷絕緣層84之間。根據一實施例，圖3之第一導熱介面層82包括類似於圖2之導熱介面層68之一導熱、電絕緣材料，該導熱介面層68容許將熱自導電墊片60傳遞至散熱器66同時將導電墊片60與散熱器66電隔離。在一例示性實施例中，第一導熱介面層82包括填充有導熱但電絕緣填充物(諸如，氧化鋁或氮化硼)之一環氧樹脂或矽樹脂。 在一替代實施例中，第一導熱介面層82包括形成為導電墊片60頂上之許多離散襯墊88 (如圖4中繪示)之一導電材料，諸如(例如)，焊料、導電黏著劑，或經燒結銀。根據多種實施例，鄰接襯墊88之間之橫向間隔90可留作為氣隙或由介電填充材料64填充。 現一起參考圖3及圖4，第二導熱介面層86夾置於陶瓷絕緣層84與散熱器66之間。根據一實施例，第二導熱介面層86包括類似於圖2之導熱介面層68之一導熱、電絕緣材料。在一替代實施例中，第二導熱介面層86係同時導熱且導電之一材料，諸如(例如)，填充有銀之一環氧樹脂或矽樹脂。 圖5繪示根據本發明之一實施例之倂有POL結構40 (圖2)及POL結構76 (圖3、圖4)之一POL總成92。如所示，POL結構40、76之各自I/O連接70耦合至一外部電路組件94，諸如(例如)，一印刷電路板(PCB)。根據本發明之多種實施例，儘管POL總成92中繪示兩個POL結構40、76，然而熟習此項技術者將認知POL總成92可包含任何數目之POL結構。此外，POL總成92可包含一單一類型之多種POL結構，諸如，兩個或兩個以上POL結構40或兩個或兩個以上POL結構76。 現參考圖6至圖16，根據本發明之一實施例提供製造圖2之POL子模組42及圖3及圖4之POL子模組78之一技術之程序步驟之詳細視圖。首先參考圖6，POL子模組42、78之建造程序開始於將一黏著層50施覆於介電層48上。在該技術之一下一步驟中，藉由黏著層50將一或多個半導體裝置44、45 (例如，兩個半導體裝置)固定至介電層48，如圖7中繪示。為將半導體裝置44、45固定至介電層48，將半導體裝置44、45之頂部表面96放置於黏著層50上。接著固化黏著劑50以將半導體裝置44、45固定在介電層48上。 接著穿過黏著層50及介電層48形成複數個通孔56，如圖8中繪示。根據本發明之實施例，可藉由一雷射燒蝕或雷射鑽孔程序、電漿蝕刻、光界定，或機械鑽孔程序形成通孔56。 儘管圖8中展示為將半導體裝置44、45放置在黏著層50上之後執行穿過黏著層50及介電層48形成通孔56，然而認知放置半導體裝置44、45可發生在形成通孔之後。或者，取決於藉由通孔大小強加之限制，可首先將半導體裝置44、45放置在黏著層50及介電層48上，隨後在對應於半導體裝置44、45上形成之複數個金屬化電路及/或連接襯墊接觸襯墊58之位置處形成通孔56。此外，可採用預鑽及後鑽通孔之一組合。 現參考圖9及圖10，在將半導體裝置44、45固定在介電層48上且形成通孔56之後，通孔56 (諸如通過一反應性離子蝕刻(RIE)去灰程序)經清潔及(隨後)金屬化以形成一金屬化或互連層54。儘管認知亦可使用金屬沈積之其他無電鍍方法，然而通常通過濺射及電鍍應用之一組合形成金屬化層54。例如，可首先經由一濺射程序施覆一鈦黏著層及銅晶種層，其後接著將銅之一厚度增加至一所要位準之一電鍍程序。接著隨後將經施覆金屬材料圖案化為具有一所要形狀且運作為穿過介電層48及黏著層50形成之垂直饋通之金屬互連件54。金屬互連件54自半導體裝置44、45之電路及/或連接襯墊接觸襯墊58延伸出，穿過通孔/開口56，且跨介電層48之一頂部表面98出去。 如圖11中所示，在經圖案化金屬互連件54上方施覆一焊料遮罩層74以提供一保護塗層及界定互連襯墊。在一替代實施例中，認知互連襯墊可具有一金屬修整以支援可焊性，諸如，Ni或Ni/Au。 現參考圖12，在製造技術之一下一步驟中，將一導電接觸層62施覆至半導體裝置44、45之一底部表面100。接著藉由導電接觸層62將導電墊片60之一底部表面102耦合至半導體裝置44、45。 根據本發明之一實施例，且如圖12中所示，半導體裝置44、45可具有多種厚度/高度。為使各自半導體裝置44、45之整體高度相等，導電墊片60可具有不同高度使得各半導體裝置44、45/導電墊片對60之整體厚度/高度相等且導電墊片60之一後表面係「平坦的」。 如圖13中所示，製造POL子模組42、78之建造技術繼續施覆一介電填充材料64，以填充POL子模組42、78中半導體裝置44、45與導電墊片60之間及周圍之縫隙，以便限制介電層48且將額外電絕緣及結構完整性提供至POL子模組42、78。在一實施例中，使用一包覆模製技術施覆且固化介電填充材料64。在固化介電填充材料64之後，使用一研磨操作移除介電填充材料64之一部分104以暴露導電墊片60。亦可使用此研磨操作移除導電墊片60之高度之任何變動，使得導電墊片60之一頂部表面106與介電填充材料64之一頂部表面108共面，如圖14中所示。或者，可使用一包覆模製或囊封技術來施覆介電填充材料64，使得在無一研磨步驟之情況下經固化介電填充材料64之頂部表面108與導電墊片60之頂部表面106齊平。在又一實施例中，可使用一底部填充技術施覆介電填充材料64。 在製造程序之一下一步驟中，將一導熱介面112之一第一側110施覆至導電墊片60及介電填充材料64之各自頂部表面106、108，如圖15中所示。在其中導熱介面112包括單一導熱介面層68 (圖2)之實施例中，在一步驟中將導熱介面112施覆至導電墊片60及介電填充材料64之頂部表面106、108。或者，導熱介面112可係如圖3及圖4中所示之一多層導熱介面80。亦參考圖3及圖4，使用其中將第一導熱介面層82施覆在介電填充材料64及導電墊片60之頂上、其次將陶瓷絕緣層84施覆在第一導熱介面層82之頂上且最後將第二導熱介面層86施覆至陶瓷絕緣層84之頂部表面之一建造技術將多層導熱介面80之單獨層依序施覆至導電墊片60及介電填充材料64之頂部表面106、108。 在製造技術之一下一步驟中，將I/O連接70施覆至焊料遮罩層74。在一實施例中，I/O連接70係焊料凸塊72，如圖16中所示。在建造技術之一替代實施例中，將I/O連接70組態為用於一貫穿孔組件之引線114，如圖17中所示。在完成POL子模組42、78之建造程序之後，將一散熱器66貼附至導熱介面112之一第二側116。POL子模組42、78可經單粒化以表面安裝至一外部電路，諸如PCB 94 (圖5)。 現參考圖18，繪示一POL子模組118之一替代實施例。POL子模組118包含類似於圖2之POL子模組42中展示之組件之許多組件，且因此亦將使用用以指示圖2中之組件之數字指示圖18中之類似組件。 如所示，POL子模組118包含藉由一黏著層50安裝至一介電層48之半導體裝置44。金屬互連件54延伸穿過形成於介電層48中之通孔56以連接至半導體裝置44上之接觸襯墊(未展示)。一導電墊片120藉由一導電接觸層62耦合至各半導體裝置44。類似於圖2之導電墊片60，導電墊片120包括一金屬或合金材料，諸如(例如)，銅、鋁、鉬或其等之組合。提供介電填充材料64以填充POL子模組118中半導體裝置44與導電墊片120之間及周圍之縫隙。一導熱介面112 (諸如導熱介面層68 (圖2)或多層導熱介面80 (圖3))設置在介電填充材料64及導電墊片120之頂上。 如圖18中所示，導電墊片120耦合至一引線框122。根據本發明之實施例，在導電墊片120放置在導電接觸層62中之前，將引線框122預附接至導電墊片120。例如，引線框122及導電墊片60可係自一共同銅板片預製的，或引線框122可藉由類似焊接、硬焊、熔接或其他類似方法之一高溫接合程序預附接至導電墊片60以組裝至POL子模組118中。或者，認知在完成POL子模組118之製造之後，可替代地後附接引線框122。 現參考圖19及圖20，繪示考量其中POL子模組124包含不同高度之半導體裝置126、128之情況之一POL子模組124之兩個替代實施例。再者，由於POL子模組124包含類似於圖2之POL子模組42中展示之組件之許多組件，故因此亦將使用用以指示圖2中之組件之數字指示圖19及圖20中之類似組件。 首先參考圖19，展示包含具有一階狀組態之一導電墊片130之一替代實施例。如所示，導電墊片130之一第一部分132具有一第一高度或厚度134，且導電墊片130之一第二部分136具有一第二高度或厚度138以考量半導體裝置126、128之不同高度同時維持導電墊片130之一平坦頂部表面140。 圖20中展示POL子模組124之一替代實施例，其中一第一導電墊片142使用一第一導電接觸層144 (諸如(例如)，類似於導電接觸層62 (圖2)之一焊料)耦合至半導體裝置126。第一導電墊片142經定大小使得第一導電墊片142之一上部表面146與半導體裝置128之一上部表面148共面。接著將一第二導電接觸層150施覆至第一導電墊片142及半導體裝置128之頂部表面。在一實施例中，第二導電接觸層150包括焊料。接著將經定大小以橫跨半導體裝置126、128之至少整體寬度之一第二導電墊片152貼附至第二導電墊片152，如所示。 有益地，因此本發明之實施例提供包含無一DBC基板之缺點之一導熱介面之一POL封裝及互連結構。例如，由於可在發生在施覆及固化介電填充材料64之後之一製造步驟中施覆導熱介面層68及多層導熱介面80，故可使用一囊封或包覆模製技術而非更可能導致空隙之一更多成本且更耗時之底部填充程序施覆介電填充材料64。再者，因為導熱介面係在封裝建造程序期間形成而非提供作為一預製組件，所以可基於所要操作特徵裁適導熱介面之尺寸及材料。此外，使用導電墊片60、120、130、142及/或152提供考量多種高度之半導體裝置之能力。 儘管已描述本發明之實施例包含用於高電壓功率應用中之功率半導體裝置，然而熟習此項技術者將認知本文中闡述之技術同樣適用於低功率應用及倂有非功率半導體裝置或具有延行至半導體裝置之僅一單一側之電連接之半導體裝置之晶片封裝。 因此，根據本發明之一實施例，一功率覆蓋(POL)結構包含一POL子模組。POL子模組包含一介電層及具有附接至介電層之一頂部表面之一半導體裝置。半導體裝置之頂部表面具有形成於其上之至少一接觸襯墊。POL子模組亦包含延伸穿過介電層且電耦合至半導體裝置之至少一接觸襯墊之一金屬互連結構。一導電墊片耦合至半導體裝置之一底部表面，且一導熱介面之一第一側耦合至導電墊片。一散熱器耦合至電絕緣導熱介面之一第二側。 根據本發明之另一實施例，形成一功率覆蓋(POL)結構之一方法包含：提供一半導體裝置、將半導體裝置之一第一表面貼附至一介電層、穿過介電層形成通孔及形成延伸穿過介電層中之通孔之一金屬互連結構以電連接至半導體裝置。該方法亦包含將一導電墊片之一第一表面貼附至半導體裝置之一第二表面及在導電墊片之一第二表面之頂上形成一導熱介面。此外，該方法包含在無一直接接合銅(DBC)基板位於一散熱器與導電墊片之間之情況下將散熱器熱耦合至導電墊片。 根據本發明之又一實施例，一功率覆蓋(POL)封裝結構包含一POL子模組。POL子模組包含：一介電層；一第一半導體裝置，其附接至介電層；及一互連結構，其電耦合至第一半導體裝置之一第一側。互連結構延伸穿過介電層以電連接至第一半導體裝置上之至少一接觸襯墊。一第一導電墊片具有耦合至第一半導體裝置之一第二側之一底部表面，且一導熱介面在無一直接接合銅(DBC)基板位於導熱介面與第一導電墊片之間之情況下耦合至第一導電墊片之一頂部表面。一散熱器直接耦合至導熱介面。 根據本發明之又一實施例，一半導體裝置封裝包含：一第一半導體裝置；一第二半導體裝置，其具有大於第一半導體裝置之一厚度之一厚度；及一絕緣基板，其耦合至第一半導體裝置及第二半導體裝置之第一表面。一金屬化層延伸穿過絕緣基板，使得金屬化層之一第一表面耦合至第一半導體裝置及第二半導體裝置之接觸襯墊。具有一第一側之一第一導電墊片經由一導電接觸層耦合至第一半導體裝置；具有一第一側之一第二導電墊片經由導電接觸層耦合至第一半導體裝置。第一導電墊片具有大於第二導電墊片之一厚度之一厚度，且第一導電墊片與第二導電墊片之第二側共面。 根據本發明之又一實施例，一半導體裝置封裝包含：一介電層，其具有穿過介電層形成之複數個通孔；及一半導體裝置，其具有耦合至介電層之一頂部表面之一第一表面。半導體裝置封裝亦包含耦合至介電層之一底部表面之一金屬互連結構。金屬互連結構延伸穿過介電層之複數個通孔以連接至半導體裝置之第一表面。半導體裝置封裝亦包含一導電墊片，該導電墊片具有耦合至半導體裝置之一第二表面之一底部表面且一有機導熱介面在無一直接接合銅(DBC)基板位於有機導熱介面與導電墊片之間之情況下耦合至導電墊片之一頂部表面。 儘管已結合僅有限數目之實施例詳細描述本發明，然而應易於瞭解本發明不限於此等所揭示實施例。反而，本發明可經修正以併有在此之前未描述但與本發明之精神及範疇相稱之任何數目之變動、變更、替代或等效配置。此外，儘管已描述本發明之多種實施例，然而應瞭解本發明之態樣可包含所描述實施例之僅一些。因此，本發明不應視為受前文描述限制，但僅受隨附申請專利範圍之範疇限制。
10‧‧‧功率覆蓋(POL)結構 12‧‧‧功率半導體裝置 14、48‧‧‧介電層 16、50‧‧‧黏著劑/黏著層 18‧‧‧金屬互連件 20‧‧‧輸入/輸出(I/O)系統 22、66‧‧‧散熱器 24‧‧‧直接接合銅(DBC)基板 26‧‧‧非有機陶瓷基板 28‧‧‧上部銅薄片/上部銅層 30‧‧‧下部銅薄片 31‧‧‧直接接合銅介面/硬焊層 32‧‧‧焊料 34‧‧‧介電有機材料 36、42、78、118、124‧‧‧POL子模組 38‧‧‧導熱襯墊/導熱膏 40‧‧‧半導體裝置總成/功率覆蓋(POL)結構 43、44、45、126、128‧‧‧半導體裝置 46‧‧‧額外電路組件 52‧‧‧金屬化層/互連結構 54‧‧‧金屬互連件/金屬化層/互連層 56‧‧‧通孔/開口 58‧‧‧接觸襯墊 60‧‧‧導電板片/導電墊片 62‧‧‧導熱且導電接觸層/導電接觸層 64‧‧‧介電填充材料 68‧‧‧導熱介面基板/層 70‧‧‧輸入輸出(I/O)連接 72‧‧‧球柵格陣列(BGA)焊料凸塊 74‧‧‧焊料遮罩層 76‧‧‧POL結構 80‧‧‧多層導熱介面 82‧‧‧第一導熱介面層 84‧‧‧陶瓷絕緣層 86‧‧‧第二導熱介面層 88‧‧‧離散襯墊/鄰接襯墊 90‧‧‧橫向間隔 92‧‧‧POL總成 94‧‧‧外部電路組件 96、98、106、108、140‧‧‧頂部表面 100、102‧‧‧底部表面 104‧‧‧部分 110‧‧‧第一側 112‧‧‧導熱介面 114‧‧‧引線 116‧‧‧第二側 120、130‧‧‧導電墊片 122‧‧‧引線框 132‧‧‧第一部分 134‧‧‧第一高度或厚度 136‧‧‧第二部分 138‧‧‧第二高度或厚度 142‧‧‧第一導電墊片 144‧‧‧第一導電接觸層 146、148‧‧‧上部表面 150‧‧‧第二導電接觸層 152‧‧‧第二導電墊片
圖式繪示當前預期用於實行本發明之實施例。 在圖式中： 圖1係倂有一DBC基板之一先前技術功率覆蓋(POL)結構之一示意性截面側視圖。 圖2係根據本發明之一實施例之一POL結構之一示意性截面側視圖。 圖3係根據本發明之另一實施例之一POL結構之一示意性截面側視圖。 圖4係根據本發明之又一實施例之一POL結構之一示意性截面側視圖。 圖5係根據本發明之一實施例之一POL總成之一示意性截面側視圖。 圖6至圖16係根據本發明之實施例之一製造/建造程序之各種階段期間之一POL子模組之示意性截面側視圖。 圖17係根據本發明之另一實施例之一引線POL子模組之一部分之一示意性截面側視圖。 圖18係根據本發明之又一實施例之一引線POL子模組之一部分之一示意性截面側視圖。 圖19係根據本發明之一實施例之具有一階狀導電墊片之一POL子模組之一部分之一示意性截面側視圖。 圖20係根據本發明之一實施例之具有一多層導電墊片總成之一POL子模組之一部分之一示意性截面側視圖。
40‧‧‧半導體裝置總成/功率覆蓋(POL)結構
42‧‧‧POL子模組
43、44、45‧‧‧半導體裝置
46‧‧‧額外電路組件
48‧‧‧介電層
50‧‧‧黏著層/黏著劑
52‧‧‧金屬化層/互連結構
54‧‧‧金屬互連件/金屬化層/互連層
56‧‧‧通孔/開口
58‧‧‧接觸襯墊
60‧‧‧導電板片/導電墊片
62‧‧‧導熱且導電接觸層/導電接觸層
64‧‧‧介電填充材料
66‧‧‧散熱器
68‧‧‧導熱介面基板或層
70‧‧‧輸入輸出(I/O)連接
72‧‧‧球柵格陣列(BGA)焊料凸塊
74‧‧‧焊料遮罩層

Claims (25)

  1. 一種功率覆蓋(POL)封裝結構，其包括：一POL子模組，該POL子模組包括：一介電層；一第一半導體裝置，其附接至該介電層；一互連結構，其電耦合至該第一半導體裝置之一第一側，該互連結構延伸穿過該介電層以電連接至該第一半導體裝置上之至少一接觸襯墊；一第一導電墊片，其具有電耦合至該第一半導體裝置之一第二側之一底部表面；及一導熱介面，其在無一直接接合銅(DBC)基板定位於該導熱介面與該第一導電墊片之間之情況下耦合至該第一導電墊片之一頂部表面，其中該導熱介面為電絕緣；及一散熱器，其直接耦合至該導熱介面。
  2. 如請求項1之POL封裝結構，其中該第一導電墊片包括銅。
  3. 如請求項1之POL封裝結構，其進一步包括圍繞該第一半導體裝置及該第一導電墊片之至少一部分之一填充材料。
  4. 如請求項1之POL封裝結構，其進一步包括具有附接至該介電層之一第一側之一第二半導體裝置。
  5. 如請求項4之POL封裝結構，其中該第一導電墊片之該底部表面耦合至該第二半導體裝置之一第二側。
  6. 如請求項5之POL封裝結構，其中該第二半導體裝置具有不同於該第一半導體裝置之一垂直高度之一垂直高度；其中該第一導電墊片之一第一部分耦合至該第一半導體裝置；其中該第一導電墊片之一第二部分耦合至該第二半導體裝置；且其中該第一導電墊片之該第一部分與該第一半導體裝置之一整體垂直高度實質上等於該第一導電墊片之該第二部分與該第二半導體裝置之一整體垂直高度。
  7. 如請求項4之POL封裝結構，其進一步包括具有耦合至該第二半導體裝置之一底部表面之一第二導電墊片。
  8. 如請求項4之POL封裝結構，其進一步包括：一印刷電路板；及一引線框，其耦合至該第一導電墊片，該引線框經組態以電連接該POL子模組至該印刷電路板。
  9. 如請求項1之POL封裝結構，其中該第一導電墊片包括一金屬及一合金材料之一者。
  10. 一種半導體裝置封裝，其包括：一第一半導體裝置；一第二半導體裝置，其具有大於該第一半導體裝置之一厚度之一厚度；一絕緣基板，其耦合至該第一半導體裝置及該第二半導體裝置之第一表面；一金屬化層，其延伸穿過該絕緣基板使得該金屬化層之一第一表面耦合至該第一半導體裝置及該第二半導體裝置之接觸襯墊；一第一導電墊片，其具有經由一導電接觸層耦合至該第一半導體裝置之一第一側；一第二導電墊片，其具有經由該導電接觸層耦合至該第二半導體裝置之一第一側；且其中該第一導電墊片具有大於該第二導電墊片之一厚度之一厚度；且其中該第一導電墊片與該第二導電墊片之第二側共面。
  11. 如請求項10之半導體裝置封裝，其進一步包括耦合至該第一導電墊片之該第二側及該第二導電墊片之該第二側之一導熱介面層。
  12. 如請求項11之半導體裝置封裝，其中該導熱介面層係電絕緣及導熱。
  13. 如請求項11之半導體裝置封裝，其中該導熱介面係導電及導熱。
  14. 如請求項11之半導體裝置封裝，其中該導熱介面層包括懸浮在一樹脂基質(a matrix of resin)中之複數個導電纖維。
  15. 如請求項11之半導體裝置封裝，其中該導熱介面層之一第一部分耦合至該第一導電墊片，且該導熱介面層之一第二部分耦合至該第二導電墊片；且其中該導熱介面層之該第一部分與該第二部分之間形成一縫隙，使得該導熱介面層之該第一部分與該導熱介面層之該第二部分電隔離。
  16. 如請求項11之半導體裝置封裝，其中該導熱介面層包括一多層基板，該多層基板包括：包括一電絕緣且導熱材料之一第一導熱介面層，其具有直接耦合至該第一導電墊片及該第二導電墊片之一第一側；一陶瓷基板，其具有直接耦合至該第一導熱介面層之一第二側之一第一側；及包括一電絕緣且導熱材料之一第二導熱介面層，其直接耦合至該陶瓷基板之一第二側。
  17. 如請求項11之半導體裝置封裝，其中該導熱介面層包括一多層基板，該多層基板包括：包括一電絕緣且導熱材料之一第一導熱介面層，其具有直接耦合至該第一導電墊片及該第二導電墊片之一第一側； 一陶瓷基板，其具有直接耦合至該第一導熱介面層之一第二側之一第一側；及包括一導電且導熱材料之一第二導熱介面層，其直接耦合至該陶瓷基板之一第二側。
  18. 一種半導體裝置封裝，其包括：一介電層，其具有穿過該介電層形成之複數個通孔；一半導體裝置，其具有耦合至該介電層之一頂部表面之一第一表面；一金屬互連結構，其耦合至該介電層之一底部表面，該金屬互連結構延伸穿過該介電層之該複數個通孔以連接至該半導體裝置之該第一表面；一導電墊片，其具有電耦合至該半導體裝置之一第二表面之一底部表面；及一有機導熱介面，其在無一直接接合銅(DBC)基板位於該有機導熱介面與該導電墊片之間之情況下耦合至該導電墊片之一頂部表面，其中該有機導熱介面為電絕緣。
  19. 如請求項18之半導體裝置封裝，其中該有機導熱介面係導電及導熱。
  20. 如請求項18之半導體裝置封裝，其中該有機導熱介面係導熱及電絕緣。
  21. 如請求項18之半導體裝置封裝，其中該有機導熱介面包括懸浮在一樹脂基質中之複數個導電纖維。
  22. 如請求項18之半導體裝置封裝，其進一步包括位於該介電層與該有機導熱介面之間之一絕緣底部填充材料。
  23. 如請求項18之半導體裝置封裝，其中該導電墊片包括一導熱且導電材料。
  24. 如請求項18之半導體裝置封裝，其中該有機導熱介面包括一多層基板，該多層基板包括：包括一有機材料之一第一層，其具有耦合至該導電墊片之一第一側；一陶瓷基板，其具有直接耦合至該第一層之一第二側之一第一側；及包括一電絕緣且導熱材料之一第二層，其直接耦合至該陶瓷基板之一第二側。
  25. 如請求項18之半導體裝置封裝，其中該有機導熱介面包括一多層基板，該多層基板包括：包括一有機材料之一第一層，其具有耦合至該導電墊片之一第一側；一陶瓷基板，其具有直接耦合至該第一層之一第二側之一第一側；及 一導電且導熱材料之一第二層，其包括直接耦合至該陶瓷基板之一第二側。
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