JP3823974B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
- Publication number
- JP3823974B2 JP3823974B2 JP2004036441A JP2004036441A JP3823974B2 JP 3823974 B2 JP3823974 B2 JP 3823974B2 JP 2004036441 A JP2004036441 A JP 2004036441A JP 2004036441 A JP2004036441 A JP 2004036441A JP 3823974 B2 JP3823974 B2 JP 3823974B2
- Authority
- JP
- Japan
- Prior art keywords
- metal body
- semiconductor element
- bonding material
- region
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/37001—Core members of the connector
- H01L2224/37099—Material
- H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/37147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/3754—Coating
- H01L2224/37599—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/3754—Coating
- H01L2224/37599—Material
- H01L2224/376—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/3754—Coating
- H01L2224/37599—Material
- H01L2224/376—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/37638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/37644—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/848—Bonding techniques
- H01L2224/84801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1301—Thyristor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
図1に、本発明の第1実施形態における半導体装置を側面方向から内部を透過して見たときの内部構成を示す。また、図2に、図1の半導体装置を矢印方向で見たときの図を示す。図2では、第2の金属体5、第3の接合材10、モールド樹脂7を省略している。なお、図1は、半導体装置を図2中の矢印方向から見たときの図である。
図4、5に、本発明の第2実施形態における半導体装置を示す。図4、5は、図1、2にそれぞれ対応している。本実施形態は、第3の金属体6の外周に被保持部が設けられている点が、第1実施形態と異なっている。以下では、第1実施形態と異なる点のみ説明し、第1実施形態と同様の構造部については、図4、5において、図1、2と同一の符号を付すことで説明を省略する。
図8、9に、本発明の第3実施形態における半導体装置を示す。図8、9は、図4、5にそれぞれ対応している。なお、図8、9では、図4、5と同様の構造部については、図4、5と同一の符号を付している。
図11に、本発明の第4実施形態における半導体装置を示す。図11は、図3に対応している。なお、図11では、図3と同様の構造部については、図3と同一の符号を付している。
図12に、本発明の第5実施形態における半導体装置を示す。図12は、図3に対応している。なお、図12では、図3と同様の構造部については、図3と同一の符号を付している。
第1、第2、第4、第5実施形態では、2つの半導体素子1a、1bを用いる場合を例として説明したが、半導体素子1の数は2つに限らず、1つ、3つ、4つ等他の数でも良い。また、半導体素子1を3つ以上用いる場合では、全ての半導体素子1を1つの第3の金属体6に接合させたり、全ての半導体素子ではないが、複数の半導体素子1を1つの第1の金属体3に接合させたりすることができる。
7…モールド樹脂、8…第1の接合材、9…第2の接合材、10…第3の接合材、
11…第1の領域、12…第2の領域、12a…鍔形状部、14…凹部、
21…第1の保持治具、24…凸部。
Claims (3)
- 半導体素子(1)と、前記半導体素子(1)の裏面(2)側に設けられ電極と放熱体とを兼ねる第1の金属体(3)と、前記半導体素子(1)の表面(4)側に設けられ電極と放熱体とを兼ねる第2の金属体(5)と、前記半導体素子(1)の表面(4)と前記第2の金属体(5)との間に設けられた第3の金属体(6)と、前記半導体素子(1)、前記第1の金属体(3)、前記第2の金属体(5)、前記第3の金属体(6)を封止するモールド樹脂(7)とを備えた半導体装置の製造方法において、
前記第1の金属体(3)、第1の接合材(8)、前記半導体素子(1)、第2の接合材(9)、前記第3の金属体(6)、第3の接合材(10)および前記第2の金属体(5)を用意する工程と、
前記第1の金属体(3)、第1の接合材(8)、前記半導体素子(1)、第2の接合材(9)、前記第3の金属体(6)、第3の接合材(10)および前記第2の金属体(5)を順に積層した状態とし、かつ、前記第1の金属体(3)と前記第2の金属体(5)との間であって、前記半導体素子(1)が配置された領域を除く領域に、前記第1の金属体(3)と前記第3の金属体(6)とを保持する保持治具(21)を配置する工程と、
前記保持治具(21)を配置した状態で、前記積層された状態の前記第1の金属体(3)、前記第1の接合材(8)、前記半導体素子(1)、前記第2の接合材(9)、前記第3の金属体(6)、前記第3の接合材(10)および前記第2の金属体(5)に対して、加熱処理を施すことにより、前記第1の金属体(3)と前記半導体素子(1)、前記半導体素子(1)と前記第3の金属体(6)、前記第3の金属体(6)と前記第2の金属体(5)を、それぞれ接合する工程と、
前記半導体素子(1)、前記第1の金属体(3)、前記第2の金属体(5)、前記第3の金属体(6)をモールド樹脂(7)で封止する工程とを有し、
前記第3の金属体(6)を用意する工程では、前記積層した状態の前記第3の金属体(6)を、前記前記半導体素子(1)の前記表面(4)に対して略垂直な方向から見たとき、前記半導体素子(1)と対向し、前記半導体素子(1)と接合される第1の領域(11)と、前記第3の金属体(6)の外周に位置し、前記半導体素子(1)からはみ出ている第2の領域(12)とを備え、前記第1の領域(11)が前記第2の領域(12)よりも前記半導体素子(1)に向かって突出することで、前記第2の領域(12)が前記第1の領域(11)よりも薄くなっている形状の前記第3の金属体(6)を用意し、
前記保持治具(21)を配置する工程では、前記第1の領域(11)から離れた位置で前記第3の金属体(6)の前記第2の領域(12)を保持させるように、前記保持治具(21)を配置することで、前記第3の金属体(6)の前記第1の領域(11)と前記保持治具(21)との間に、前記第2の接合材(9)が溶融して前記第1の領域(11)から前記第2の領域(12)に流れた場合に、前記第2の領域(12)に前記第2の接合材(9)を溜めることができる空間が形成された状態とすることを特徴とする半導体装置の製造方法。 - 半導体素子(1)と、前記半導体素子(1)の裏面(2)側に設けられ電極と放熱体とを兼ねる第1の金属体(3)と、前記半導体素子(1)の表面(4)側に設けられ電極と放熱体とを兼ねる第2の金属体(5)と、前記半導体素子(1)の表面(4)と前記第2の金属体(5)との間に設けられた第3の金属体(6)と、前記半導体素子(1)、前記第1の金属体(3)、前記第2の金属体(5)、前記第3の金属体(6)を封止するモールド樹脂(7)とを備えた半導体装置の製造方法において、
前記第1の金属体(3)、第1の接合材(8)、前記半導体素子(1)、第2の接合材(9)、前記第3の金属体(6)、第3の接合材(10)および前記第2の金属体(5)を用意する工程と、
前記第1の金属体(3)、第1の接合材(8)、前記半導体素子(1)、第2の接合材(9)、前記第3の金属体(6)、第3の接合材(10)および前記第2の金属体(5)を順に積層した状態とし、かつ、前記第1の金属体(3)と前記第2の金属体(5)との間であって、前記半導体素子(1)が配置された領域を除く領域に、前記第1の金属体(3)と前記第3の金属体(6)とを保持する保持治具(21)を配置する工程と、
前記保持治具(21)を配置した状態で、前記積層された状態の前記第1の金属体(3)、前記第1の接合材(8)、前記半導体素子(1)、前記第2の接合材(9)、前記第3の金属体(6)、前記第3の接合材(10)および前記第2の金属体(5)に対して、加熱処理を施すことにより、前記第1の金属体(3)と前記半導体素子(1)、前記半導体素子(1)と前記第3の金属体(6)、前記第3の金属体(6)と前記第2の金属体(5)を、それぞれ接合する工程と、
前記半導体素子(1)、前記第1の金属体(3)、前記第2の金属体(5)、前記第3の金属体(6)をモールド樹脂(7)で封止する工程とを有し、
前記第3の金属体(6)を用意する工程では、前記半導体素子(1)と接合される面(6c)と、前記半導体素子(1)と接合される面(6c)に隣接する側面(6e)と、前記側面(6e)に設けられた凹部(14)とを備える前記第3の金属体(6)を用意し、
前記保持治具(21)を配置する工程では、前記第3の金属体(6)の前記凹部(14)を、前記保持治具(21)で保持させるように、前記保持治具(21)を配置することを特徴とする半導体装置の製造方法。 - 前記第1の金属体(3)、第1の接合材(8)、前記半導体素子(1)、第2の接合材(9)、前記第3の金属体(6)、第3の接合材(10)および前記第2の金属体(5)を順に積層した状態とする工程では、
1つの前記第1の金属体(3)と1つの前記第3の金属体(6)との間に複数の前記半導体素子(1a、1b)を配置することを特徴とする請求項1または2に記載の半導体装置の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004036441A JP3823974B2 (ja) | 2004-02-13 | 2004-02-13 | 半導体装置の製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004036441A JP3823974B2 (ja) | 2004-02-13 | 2004-02-13 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005228929A JP2005228929A (ja) | 2005-08-25 |
JP3823974B2 true JP3823974B2 (ja) | 2006-09-20 |
Family
ID=35003396
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004036441A Expired - Fee Related JP3823974B2 (ja) | 2004-02-13 | 2004-02-13 | 半導体装置の製造方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3823974B2 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8492256B2 (en) | 2010-04-14 | 2013-07-23 | Fuji Electric Co., Ltd. | Method of manufacturing semiconductor apparatus |
US9666437B2 (en) | 2013-09-27 | 2017-05-30 | Fuji Electric Co., Ltd. | Method for manufacturing semiconductor device |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006140403A (ja) * | 2004-11-15 | 2006-06-01 | Fuji Electric Holdings Co Ltd | 半導体装置の製造方法および製造装置 |
JP4952556B2 (ja) * | 2007-12-11 | 2012-06-13 | 株式会社デンソー | 半導体装置およびその製造方法 |
JP2009224582A (ja) * | 2008-03-17 | 2009-10-01 | Rohm Co Ltd | モジュールパッケージ |
DE112011105693T5 (de) * | 2011-09-29 | 2014-08-21 | Toyota Jidosha Kabushiki Kaisha | Halbleitervorrichtung |
US10269688B2 (en) | 2013-03-14 | 2019-04-23 | General Electric Company | Power overlay structure and method of making same |
US8987876B2 (en) * | 2013-03-14 | 2015-03-24 | General Electric Company | Power overlay structure and method of making same |
-
2004
- 2004-02-13 JP JP2004036441A patent/JP3823974B2/ja not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8492256B2 (en) | 2010-04-14 | 2013-07-23 | Fuji Electric Co., Ltd. | Method of manufacturing semiconductor apparatus |
US9666437B2 (en) | 2013-09-27 | 2017-05-30 | Fuji Electric Co., Ltd. | Method for manufacturing semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JP2005228929A (ja) | 2005-08-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8310044B2 (en) | Semiconductor device and method of manufacturing the same | |
JP5241177B2 (ja) | 半導体装置及び半導体装置の製造方法 | |
JP5570799B2 (ja) | 半導体装置及びその製造方法 | |
JP4635564B2 (ja) | 半導体装置 | |
US5437915A (en) | Semiconductor leadframe and its production method and plastic encapsulated semiconductor device | |
JP5543125B2 (ja) | 半導体装置および半導体装置の製造方法 | |
US20060108700A1 (en) | Semiconductor device, method and apparatus for fabricating the same | |
JP2004056138A (ja) | パッケージ組立体においてリードフレームを接合する方法、チップ積層パッケージの製造方法及びチップ積層パッケージ | |
JPH0794553A (ja) | 半導体装置およびその製造方法 | |
US20180286702A1 (en) | Semiconductor device and method of manufacturing the same | |
KR101486137B1 (ko) | 방열 장치 및 그 제조 방법 | |
JP5525024B2 (ja) | 半導体装置及び半導体装置の製造方法 | |
JP2018157157A (ja) | 半導体装置とその製造方法 | |
JP2003282819A (ja) | 半導体装置の製造方法 | |
JP3823974B2 (ja) | 半導体装置の製造方法 | |
JP2005167075A (ja) | 半導体装置 | |
JP4557804B2 (ja) | 半導体装置及びその製造方法 | |
JP6054345B2 (ja) | 半導体装置及び半導体装置の製造方法 | |
JP4888085B2 (ja) | 半導体装置の製造方法 | |
JP5826234B2 (ja) | 半導体装置及び半導体装置の製造方法 | |
JP4765918B2 (ja) | 半導体装置の製造方法 | |
JP2016181607A (ja) | 半導体装置及びその製造方法 | |
US11302670B2 (en) | Semiconductor device including conductive post with offset | |
JP2012015446A (ja) | 半導体装置の製造方法 | |
JP2016111255A (ja) | 半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20060216 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20060228 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20060428 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20060606 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20060619 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090707 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100707 Year of fee payment: 4 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110707 Year of fee payment: 5 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120707 Year of fee payment: 6 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120707 Year of fee payment: 6 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130707 Year of fee payment: 7 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |