CN102339818B - 功率模块及其制造方法 - Google Patents

功率模块及其制造方法 Download PDF

Info

Publication number
CN102339818B
CN102339818B CN201010230160.7A CN201010230160A CN102339818B CN 102339818 B CN102339818 B CN 102339818B CN 201010230160 A CN201010230160 A CN 201010230160A CN 102339818 B CN102339818 B CN 102339818B
Authority
CN
China
Prior art keywords
heat
power
power device
sink unit
material layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201010230160.7A
Other languages
English (en)
Other versions
CN102339818A (zh
Inventor
曾剑鸿
洪守玉
叶奇峰
林逸程
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Delta Electronics Inc
Delta Optoelectronics Inc
Original Assignee
Delta Optoelectronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Delta Optoelectronics Inc filed Critical Delta Optoelectronics Inc
Priority to CN201010230160.7A priority Critical patent/CN102339818B/zh
Priority to US13/049,322 priority patent/US8472196B2/en
Publication of CN102339818A publication Critical patent/CN102339818A/zh
Application granted granted Critical
Publication of CN102339818B publication Critical patent/CN102339818B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334Auxiliary members in encapsulations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49517Additional leads
    • H01L23/4952Additional leads the additional leads being a bump or a wire
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49562Geometry of the lead-frame for devices being provided for in H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49575Assemblies of semiconductor devices on lead frames
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/11Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/115Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/003Constructional details, e.g. physical layout, assembly, wiring or busbar connections
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601Structure
    • H01L2224/0603Bonding areas having different sizes, e.g. different heights or widths
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/4501Shape
    • H01L2224/45012Cross-sectional shape
    • H01L2224/45015Cross-sectional shape being circular
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147Copper (Cu) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/48139Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4901Structure
    • H01L2224/4903Connectors having different sizes, e.g. different diameters
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/4917Crossed wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01019Potassium [K]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/30107Inductance
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49146Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

一种功率模块包括一第一散热单元、一第一功率器件、一导热绝缘材料层、一第二功率器件、一引线框架以及一封料。第一散热单元具有一第一区及一第二区。第一功率器件设置在第一区。导热绝缘材料层设置在第二区。第二功率器件通过导热绝缘材料层设置在散热单元。引线框架与第一功率器件及第二功率器件的至少一个电性连接。封料是包覆第一功率器件、导热绝缘材料层、第二功率器件及引线框架的一部分。第一散热单元与第一功率器件及第二功率器件的至少一个电性连接。由于第一功率器件非通过导热绝缘材料层设置在第一散热单元,故可降低成本。

Description

功率模块及其制造方法
技术领域
本发明关于一种功率模块,特别关于一种应用在电源变换器的功率模块。 
背景技术
高效率和高功率密度一直是业界对电源变换器的要求。高效率意味着减少能耗,利于节能减排保护环境,并减少使用成本。高功率密度则意味着体积小、重量轻,减少运输成本和空间需求,从而减少建设成本。因此,电源领域对高效率、高功率密度的追求将永不停息。 
电源变换器由于用途不同,其种类较多。由转换电能类型来分,其可分为:非隔离型AC/DC电源变换器,例如,由一个用在功率因数校正(下称PFC电路)的AC/DC转换电路组成;非隔离型DC/DC电源变换器;隔离型DC/DC变换器;隔离型AC/DC电源变换器,例如,由一个PFC电路加一个或者多个DC/DC变换器而成;DC/AC、AC/AC等等。由于需要转换的电能性质和转换的级数不同,各种变换器的容易达成的功率密度和效率也不尽相同。以隔离型AC/DC电源变换器为例,目前业界普遍的功率密度是10W/inch3,效率是90%左右。非隔离型AC/DC电源变换器、隔离型DC/DC变换器和DC/AC的效率和功率密度则会更高些。 
电源变换器的高效率意味着低能耗。如效率90%时,其转换能耗约是整个电源变换器总输入能量的10%。而效率91%的电源变换器,其转换能耗则降低为总输入能量的9%。也就是说,效率每提升一个点,其能耗就较90%效率的电源变换器降低10%,极为可观。事实上,电源变换器效率提升的努力常常以0.5%甚至0.1%的量级进行。 
电源变换器的能耗主要由通态损耗和开关损耗特别是有源器件的开关损耗组成。开关损耗受工作频率的影响较大。电源变换器,特别是开关电源变换器,是降低音频噪音,其工作频率通常在20kHz以上。其实际工作频率的选择受无源器件特别是磁组件的影响较大。若磁组件体积小,为了可靠工作,通常需要高频率来降低其工作磁通密度从而带来高开关损耗;或者减小磁性组件中线组的线径并增加匝数,从而增加通态损耗,均带来高损耗。反之,若磁组件体积大,则可以在保证可靠工作的前提下降低工作频率从而降低开关损耗;也可以增加磁性组件中线组的线径或者减小匝数,从而降低通态损耗,以降低总损耗,得到高效率。 
因此,不难理解,提升电源内部的空间利用率,是得到高功率密度或者高效率的关键因素之一。空间利用率越高,留给对电源变换效率很重要的无源器件特别是磁性组件的空间就越大,就还容易使用到大体积的无源组件,从而提升电源效率。也可以通过使用大体积的无源器件来增加电源总功率,从而提升电源变换器的功率密度。所以,高的电源空间利用率,更易于在特定功率密度 下达成高效率或者在特定效率下达成高功率密度,也有机会高功率密度和高效率兼顾。 
半导体器件是决定电源变换器效率的重要因素之一。但使用半导体器件,往往不可避免的需要使用对电变换效率无益的额外材料,如:保护半导体的封装材料、帮助散热的散热器、固定半导体器件的夹具等等。这些材料在电源变换器内部的比例越大,电源的内部空间利用率就越差。而目前优秀的产品,已经很好地利用了电源内部空间。也正因为此,功率半导体器件占用的空间体积,占电源总体积的比重也越来越大,也越来越被重视。 
目前业界有很多先进技术被提出,如优化散热器,简化安装等等来减少散热器及其安装造成的空间占用。例如通过新的绝缘垫片技术,舍弃螺丝、夹具等,来减小体积,以改善电源设计。 
为进一步提升电源性能,需要继续提高空间利用率。半导体器件本身的封装空间利用率成为瓶颈。而集成功率模块(Integrated Power Module,IPM),将多个半导体器件集成在一个器件封装里,为提升封装内的空间利用率提供了可能。集成模块因为应用的不同,集成内容也不尽相同:有将单个功率半导体器件与其控制器或者驱动集成在一起的;有仅将多个功率半导体器件集成在一起的;有将多个半导体器件与其相应控制器或者驱动集成在一起的。集成内容不同,导致考虑点和难易程度不尽相同。为有所区别,下文中提及的功率模块中,至少包括2个功率器件,强调多个功率器件的集成。 
功率模块通常集成功率器件在某些场合更会集成一些控制、驱动元器件。常用功率器件有MOSFET,IGBT,POWER Diode等,而控制,驱动组件常包括一些三极管,IC,被动组件等。由于将多个器件变成一个器件,功率模块具备使用方便、平均无故障时间长等等优势,在很多场合被应用。由于功率模块将多个功率器件集中在一起,热量多且多点分布,其热管理因此变得很关键。众多现有技术,很多是在散热能力上做优化。 
现有技术一,如图1所示,为一典型的功率模块30内部截面图。该已有技术将元器件32、34和引线框架(lead frame)35组装。以部分功率器件的芯片32、34为例,其正面电极可以通过引线键合(wire bonding),铜片钎焊(copper strap bonding)等方式和引线框架实现电气连接;其背面可以通过钎焊,银胶,烧结,环氧胶等方式实现和lead-frame之间的电和/或机械连接。元器件和引线框架组装好以后,将需要保护的区域使用封料(molding compound)36包覆,以便起到机械,防尘,防潮,绝缘保护的功用。此结构具有价格低的优势。 
该现有技术,其散热面由封料绝缘,该散热面同时担负机械保护的角色,所以,厚度也会较大,通常大于0.5mm。通常而言,molding compound的热导率在1W/m.K左右。从芯片表面向case的传导热阻的计算式为, 
Figure BSA00000195784200021
对于10mm乘以10mm见方的面积,厚度在0.5mm,封料的热导率假设是1W/m.K时,热阻就高达5K/W。由此可见,通常而言,此类封装的散热性能较差,即,以功率半导体器件为例,从芯片的junction至case的热阻(Rjc)较大。而且,由于封料较低的导热系数,其横向热扩散的能力也较低,因此往往会出现热集中点(热点),危害器件的可靠性以及使用寿命。 
所以,现有技术一的散热能力较差,不适合散热要求高的场合。为了优化功率模块的性能,有更多已有技术被提出。 
现有技术二,如图2所示,在现有技术一的基础上,在molding的一侧,增加一散热单元31,由于此散热单元的热导率较高,例如铜的热导率高于300W/m.K,因此,这样可以使得模块的均温性能有所增加,在一定程度上缓解热点问题,以此增加模块的热管理能力。但由于该散热单元通常也被要求电绝缘,其与导线框架35间往往被填充封料36。由于molding工艺的限制,该封料层的厚度一般大于0.2mm,通常需要在0.3mm以上,按照现有技术一中的计算方法,其10mmX10mm面积对应的热阻在3K/W左右。即,此结构的整体散热性能虽有较大改善,但依然较差。 
现有技术三,如图3所示:在覆铜陶瓷基板(Direct Bonded Copper,DBC)31a上形成电路图形,此DBC板作为元器件的安装载板,将元器件32、34与DBC板组装,针对部分半导体芯片需要使用引线键合(wire bonding)工艺完成半导体芯片32、34正面电极和DBC基板/引线框架35的电信号连接。此结构的本质是在现有技术二的基础上,采用热导系数较高的陶瓷介质层,来替代封料层。由于常用的三氧化二铝陶瓷的导热系数在24W/m.K左右,这相对于封料的1W/m.K有很大的改进。对于10mm乘以10mm见方的面积的DBC板(陶瓷厚度0.38mm,两侧铜厚均是0.3mm)其热阻是0.17K/W,相对现有技术一中所举例的5K/W有较大提升,减少90%以上。 
但由于所有元器件32、34均需安装至DBC板,因此所需的DBC载板的面积比较大,而DBC的价格比较昂贵,因此成本相对较高。更由于DBC的生产工艺是高温烧结,是高能耗产品,大面积DBC板的使用也不符合当前绿色环保的科技进步潮流。而且三氧化二铝,的导热系数(~24W/m.K左右),虽然较封料(通常低于1W/m.K),有很大改善,但是,和金属相比(例如,铜300W/m.K左右)依然相去甚远,导致横向热扩散能力不够好,所以其热均匀性往往不佳。因此,散热性能仍然有进一步提升的空间。 
现有技术四,如图4所示,此结构在现有技术三的基础上有所改进,在DBC板组装元器件31a的另外一侧再组装一个散热单元(散热器)31b,这可以使得模块的均温性能有所提升。但是,由于大面积DBC板的应用,由此可能存在的由DBC,散热单元31b,封料36之间由于热膨胀系数(coefficient of thermal expansion,CTE)失配(mismatch)而引起的翘曲变形(warpage)会比较大,并可能导致可靠性的降低。如果DBC尺寸过大,且DBC和散热单元31b采用通用的焊料(Solder)的方式进行时,还有可能发生焊料层气泡过多等缺陷。而且,成本高的问题,依然没有解决。 
现有技术五,如图5所示,在现有技术四上集成了控制器件或者驱动器件。由于控制器件和驱动器件自身功耗往往不高,而又对温度较敏感,所以通常被设计成与温度较高的材料热绝缘。该现有技术就是将控制器件38或者驱动器件部分作为一个单元(通过PCB板集成或者IC),通过热绝缘体(PCB、Molding料或者专用填充料等等热绝缘体,通常导热系数小于1W/m.K)与散热单元31a连接。绝缘体的生成方式可以是粘结、填充或者在表面上镀膜等等。这样一来,控制器件或者驱动器件等自身功耗小且对热敏感的器件,就可以在封装体中独善其身,而减小被功率器件的高温影响,使得其可以集成到功率模块中,并被可靠使用。 
如前所述,目前的功率模块由于考虑通用性的影响,通常将外壳设计成绝缘的,以简化散热器的安装和选择。即便如现有技术四一样,外壳是电良导体(如铜),其往往也被设计成电绝缘。因此,模块内的金属材料,例如铜,往往仅仅被用作导电(lead frame,DBC铜层)或者散热(铜热沉)的单一功用,少有将铜层在导电同时,兼作和环境直接换热的案例。因此,材料的潜能并没有被完整挖掘,从而降低了空间利用率。 
而且,为了简化用户安装散热器,功率模块往往允许用螺丝或者夹具将其固定到散热器上。所以功率模块通常被设计成允许承受较大的机械应力。为了可靠使用,功率模块通常设计成较厚的封料以允许承受较大应力,这样就增加了厚度,也增加了材料成本,并大大降低空间利用率。而且,功率模块也通常要求自己有较高的表面平整度,以减小散热器安装时的应力,从而导致更大的设计成本和模具成本。 
以上可知,目前,功率模块已有技术依然有着各类问题:如散热性能不佳,材料浪费,可靠性设计困难,电性能未能充分发挥,过于强调设计的通用性而导致过度设计(over design),经济性能不高等这样或那样的问题。特别是其空间利用率不足,限制了其在高功率密度或者高效率场合的应用推广。 
因此,现有技术中的功率模块方案,其性能尚不能很好满足高功率密度或者高效率电源的需求。 
针对每一种半导体封装,其初期投入很高。比如Molding的模具成本,产线架设成本等等。所以,要得到价格合理的半导体封装,往往需要很大的产品量来支撑,以消化初期投入,并降低生产成本。所以,目前的功率模块,往往用在一些应用标准化的场合。如图6所示的IGBT三相桥模块。它被广泛应用在逆变器、变频器等等场合,因为这些场合的电路很标准化,需求很一致,量也就很大。所以,半导体厂家可以自行给出标准化封装,以供客户选择使用。 
在电源变换器场合,也有功率模块被成功使用,如图7所示的双相整流桥。由于绝大部分AC/DC电源变换器,需要输入整流桥,所以,功率模块的需要量很大。且整流电路很标准化,半导体厂家可以给出标准化封装,以供客户选择使用。 
但是,电源变换器其它部分的功率半导体器件,虽然也有众多厂家尝试给出功率模块,但很少被推广使用。除了如前所述,现有技术的性能有不足之外, 另一个很重要的原因是电源变换器的电路结构复杂,很难标准化。若只针对一种电路设计给出功率模块,其量较少,成本代价较高,也就限制了应用。 
因此,为进一步提升电源变换器的功率密度或者变换效率,需要空间利用率高的、成本合理的功率模块解决方案。目前的已有技术尚不能很好满足。 
发明内容
有鉴于上述课题,本发明提出了一种适合电源变换器的功率模块,用以提升功率密度或效率的解决方案,并给出了支持该解决方案的功率模块实施方案。该方案适合在功率密度大于15w/inch3、或者最高效率高于91%的电源变换器,尤其适合功率密度大于20w/inch3,或者最高效率高于93%的电源变换器场合。 
本发明可采用以下技术方案来实现的。 
本发明的一种功率模块包括一第一散热单元、一第一功率器件、一导热绝缘材料层、一第二功率器件、一引线框架以及一封料。第一散热单元具有一第一区及一第二区。第一功率器件设置在第一区。导热绝缘材料层设置在第二区并具有一绝缘层。第二功率器件通过导热绝缘材料层设置在散热单元。引线框架与第一功率器件及第二功率器件的至少一个电性连接。封料是包覆第一功率器件、导热绝缘材料层、第二功率器件及引线框架的一部分。第一散热单元与第一功率器件及第二功率器件的至少一个电性连接。 
在上述情形中,功率模块还包括一键接材料层,该第一功率器件通过该键接材料层连接该第一散热单元,该键接材料层材料是导热导电材料。 
在上述情形中,该第一散热单元与该引线框架一体成型。在上述情形中,该第一散热单元完全设置在封料内、或部分位在封料外、或完全位在封料外。 
在上述情形中,该第一散热单元是与一穿出该封料的引脚连接、或是该第一散热单元穿出该封料并形成一引脚。 
在上述情形中,该第一散热单元是与一电压静地点电性连接。 
在上述情形中,该第一散热单元是分割是多个部分。 
在上述情形中,该导热绝缘材料层是具有一线路层,该引线框架延伸而连结在该线路层。 
在上述情形中,该引线框架延而伸连结在该第一功率器件及该第二功率器件的至少一个。 
在上述情形中,功率模块还包括一第二散热单元,设置在该第二功率器件与该导热绝缘材料层之间。 
在上述情形中,功率模块还包括一第三散热单元,设置在该第一区或者由该第一单元延展而成。 
在上述情形中,该第三散热单元是穿出该封料。 
在上述情形中,该第三散热单元是穿出该封料并具有一弯折。 
在上述情形中,功率模块还包括一第四散热单元,与该第三散热单元连结,并与该封料具有一空隙。 
在上述情形中,该导热绝缘材料层是金属基板或金属化陶瓷基板。 
在上述情形中,功率模块还具有一排引脚,其穿出该封料,并作为讯号传送或散热。 
在上述情形中,功率模块还包括一控制器件,设置在该第一区。 
在上述情形中,功率模块还包括一绝热层,设置在该控制器件与该第一散热单元之间。 
在上述情形中,功率模块还包括一高频电容器,集成在该功率模块内。 
在上述情形中,功率模块还包括一温度传感器,集成在该功率模块内。 
在上述情形中,功率模块各该功率器件具有至少二电极,这些功率器件的至少一个具有至少三电极。 
在上述情形中,功率模块还包括至少一个功率器件,该功率模块包括这些功率器件的至少二具有至少三电极。 
在上述情形中,功率模块该封料的导热系数高于1.2W/m.K。 
在上述情形中,功率模块该封料的导热系数高于1.8W/m.K。 
此外,依据本发明的一种功率模块的制造方法,包括一装配步骤,将第一散热单元、一导热绝缘材料层及一引线框架按照设定的装配关系,使用连接接口材料,组装至一起,其中导热绝缘材料层覆盖第一散热单元的第一区域;一植晶及正面电极引出步骤,将一第一功率器件通过连接接口材料设置在该第一散热单元的第二区域上,并将一第二功率器件通过连接接口材料设置在该导热绝缘材料层上,该引线框架,与该第一功率器件及该第二功率器件的至少一个电性连接,该第一散热单元与该第一功率器件及该第二功率器件的至少一个电性连接;一包封步骤,通过一封料包覆该第一功率器件、该导热绝缘材料层、该第二功率器件及该引线框架的一部分。 
在上述情形中,在该装配步骤中,是在该散热单元上组装该导热绝缘材料层的位置以及和该引线框架连接的位置施加连接材料,并将该导热绝缘材料层上需要和该引线框架组装的位置施加连接材料。 
在上述情形中,连接材料是锡膏、焊料片、导电胶或低温烧结纳米银浆。 
在上述情形中,芯片正面电极引出工艺是打线或粘结/焊接金属片。 
借由上述技术方案,本发明的功率模块至少具有下列优点: 
承上所述,本发明的功率模块集成了复数功率器件,故可大幅提升功率密度或效率。另外,由于本发明的第一功率器件非通过导热绝缘材料层设置于散热单元,而该导热绝缘材料层通常可由导热基板实现,故可降低导热基板的成本。此外,通过本发明所揭露的,用以提升电源变换器功率密度或者效率的封装方法和结构,可以获得与现有技术相比,更佳的热性能,电性能,经济性能,EMC性能与更高的可靠性。其内部空间利用率很高,使用方便,非常有利于提高变 换器功率密度或者效率。而本发明给出的具体功率模块具体实施,也非常可行有效。本发明非常适合用以提升电源变换器的整体性能和性价比。 
附图说明
图1至图5是公知的功率模块的不同态样的示意图; 
图6显示一种IGBT三相桥模块; 
图7显示一种双相整流桥; 
图8是本发明优选实施例的一种功率模块的示意图; 
图9及图16显示本发明优选实施例的一种功率模块应用的全桥电路的不同态样;以及
图10至图15以及图17至图26是本发明优选实施例的功率模块不同态样的示意图。 
主要组件符号说明: 
10、30:功率模块 
11、11a、11b、11c、31、31b:散热单元 
111:第一区 
112:第二区 
12:第一功率器件 
13:导热绝缘材料层 
131:导热层 
132:绝缘层 
133:线路层 
13a:铜基板 
14:第二功率器件 
15、35:引线框架 
16、36:封料 
17:键接材料层 
18、38:控制器件 
31a:覆铜陶瓷基板 
32、34:元器件 
A1:前表面 
A2:后表面 
C:电容器 
D:厚度 
IL:绝热层 
P2、P1:引脚 
S1~S4:开关器件 
具体实施方式
以下将参照相关图式,说明依本发明较佳实施例的一种功率模块,其中相同的组件将以相同的参照符号加以说明。 
请参照图8所示,本发明较佳实施例的一种功率模块10可例如应用于电源变换器(power converter)或是其它需要功率变换的装置上。其中,电源变换器可为交流/直流(AC/DC)或直流/交流(DC/AC)变换器或隔离型DC/DC变换器。若应用于电源变换器上,功率模块10则可应用于电源变换器的功率因子校正部分(power factor correction,PFC)、DC/DC一次侧部分(以下称D2D_Pri)或DC/DC二次侧部分(以下称D2D_Sec)。 
功率模块10系为一封装体,包括一第一散热单元(heat sink)11、一第一功率器件(power chip)12、一导热绝缘材料层13、一第二功率器件14、一引线框架(lead frame)15以及一封料(molding material)16。第一散热单元11设置于封装体的一底侧,并具有一第一区111及一第二区112。第一功率器件12设置于第一区111,导热绝缘材料层13设置于第二区112。第二功率器件14设置于导热绝缘材料层13并与引线框架15电性连接。第一散热单元11系与第一功率器件12及第二功率器件14的至少一个电性连接。封料16系包覆第一功率器件12、导热绝缘材料层13、第二功率器件14及引线框架15的至少一部分,并构成为封装体的主要外观。 
第一散热单元11可以是一独立部件或与引线框架15一体成型,并可为电和热的良导体,例如铜。于此,散热单元11系作为第一功率器件12的载板。第一散热单元11可完全设置于封料16内、或部分位于封料16外、或完全位于封料16外。 
第一功率器件例如为MOSFET的器件,对于一个MOSFET的器件而言,其通常有两个相对平行的面:上表面和下表面。上表面上往往会设置两个电极,source和gate,而下表面电极为drain,下表面利用一键接材料层17可直接与散热单元11组装,键接材料层17可包括钎焊的焊料、导电银胶、或烧结金属材料等。 
第一散热单元11自身的传导热阻通常也非常低,因此,可以获得非常低的器件结点至第一散热单元11外壳的热阻(Rjc),且,由于第一散热单元11的 热容较大,因此,功率器件的抗热冲击的性能也很优良。总而言之,即直接组装至第一散热单元11的第一功率器件12的热性能非常优良。且由于第一散热单元11的存在,功率模块10的热会较均匀,更有利于热管理。当然,此处仅以功率器件为例进行描述。 
由于本实施例的封装类型为电源内部使用,为达成更高空间利用率和提升功率模块10性能,该模块表面无需与内部电路全部电绝缘。以降低绝缘成本和绝缘造成的空间浪费,散热能力衰减等不良。所以在一些具体场合,可以直接利用第一散热单元11作为导电信道,由于第一散热单元11通常为铜、铝等电的优良导体,且厚度相对较厚,其导电性能极佳。因此,可以获得更佳的电气性能,减小发热量,从而进一步改善封装体的热性能。更进一步,第一散热单元11可以直接作为引脚(Pin)使用,或者与至少一个引脚相连,即,引脚可以是和第一散热单元11为一体成型的,或者引脚和第一散热单元11通过导线接合(wire bonding)、焊接、钎焊、导电胶粘接等方式实现良好的电连接,以更充分利用该表面的电良导体。这样大大减小了器件到第一散热单元11的热阻,也使第一散热单元11这个电良导体同时被发掘热和电的能力。从而提升空间利用率,以利于提升电源变换器功率密度或变换效率。 
由于D2D_Pri、D2D_Sec等场合中,全桥电路极为常用。所以,本实施例的功率模块10可被用在全桥电路中。图9为全桥电路示意图,要满足该应用,功率模块10至少要能够排布下8个功能引脚,即Vin、GND、VA、VB、G1、G2、G3、G4。 
为进一步提升功率模块10性能,充分发掘潜力,功率模块10当具备双面散热能力。在本实施例中,功率模块的两个最大的主表面,一前表面(封料16)A1和一后表面(散热单元11及封料16)A2,均能用来散热。这样就可以大大增加有效散热能力,还容易在低损耗场合下自行散热而无需额外散热器,大大提升电源的内部空间利用率。为了实现更好的散热特性,封料的厚度越薄越好。 
为减少使用时的机械应力,以使模块更容易设计得薄,该功率模块也可以不必预设螺丝安装孔。以进一步提升空间利用率。若需安装额外散热器,可选择无螺丝的解决方案,如直接粘结等。 
这样一来,本实施例的功率模块10将大大提升该类型封装的量,也很符合目前和未来电源变换器的需求,并能提升电源变换器的空间利用率,从而提升电源的功率密度或者效率。 
另外,请续参照图8所示,第二功率器件14是通过一导热绝缘材料层13设置于第一散热单元11上,而非直接置于散热单元11。导热绝缘材料层13可具有一绝缘层132,比如用陶瓷片绝缘。导热绝缘材料层13比如为金属基板或金属化陶瓷基板,例如覆铜陶瓷基板(direct bonded copper,DBC)、金属化陶瓷片上组装厚铜电路层、覆铝陶瓷基板(direct bonded aluminum,DBA)、铝基板、铜基板,或其它形式的高导热基板。于此导热绝缘材料层13以DBC基板为例,导热绝缘材料层13可包括一导热层131、一绝缘层132及一线路层133,其中导热层131及线路层133可为铜,绝缘层132可为陶瓷。 
以常用的DBC板为例,相对于现有技术,由于本发明仅有一部分元器件(第二功率器件14),安装于导热绝缘材料层13上,因为搭载在其上的元器件数量减少,DBC板面积也可以相应减小,如此可以降低封装的材料成本,提高封装的经济性能。且,由于DBC面积的减小,由于DBC和散热单元11,封料16之间热胀系数(coefficient of thermal expansion,CTE)不一致而导致的挠曲(warpage)现象也会有所缓解。这是因为由于不同材料CTE之间的适配而引起的挠曲通常随着尺寸的增加而加剧。如此,可以降低封装体内的应力,从而进一步提高封装体的可靠性。所以,由于部分器件(第一功率器件12)已经直接与散热单元11相连,相对于现有技术,本发明的功率模块需要绝缘的材料明显减少,不尽降低了成本,更提升了热管理能力,还更有利于减少各材料CTE不匹配造成的可靠性设计难度。 
在实际应用中,有一些对散热要求非常苛刻的场合,还可以选用导热系数更高的(不低于1W/m.K,尤以大于1.2W/m.K乃至大于1.8W/m.K为佳)封料16,如此,可以增加封料一侧的散热能力,从而实现更优良的双面散热,进一步提升整个封装体的散热能力。 
图10为该封装类型的另一种扩展应用,可以将散热单元表面进行绝缘处理,使第一散热单元11完全由封料16包覆,使其任一表面不外露、或是通过一绝缘体使散热单元11与外界隔离,以便使用在希望绝缘的场合。 
为使功率模块的封装类型可以扩展到更多场合,其可以被设计成双排Pin。如图11所示。当内部电路过于复杂,以至于需要更多引脚,可以在前面提及的特征上,再加一排引脚P2。若此类封装类型被应用在单排引脚P1就足够的场合,则图中的上排引脚P2可以被设计成散热用途。 
众所周知,电源内部,电压跳变点越多,造成的电磁辐射往往就越强,从而给电源电磁兼容带来难度。本发明的散热单元11,由于具备电特性,而其面 积又相对较大,所以对电磁辐射带来隐患。但如果优化设计该散热单元11的电特性,反而有机会将其设计成电磁辐射的屏蔽层,更有利于电磁相容。例如,可以将散热单元11连接到电压静地点,即:相对来讲,该电位相对与大地,比较安静,少噪音。如图9中的Vin和GND,相对与其它电压点,就是比较平静的。将散热单元11设计成Vin或者GND,更有利于电磁兼容的。但实际操作中,为了便于实现,需要功率器件与散热单元11连接的那个面只有一个电极,在本实施例中为第一功率器件12。比如MOSFET,其漏极(Drain)与源极(Source)间承受的电压往往高于门极(Gate)与源极(Source)间的电压,所以,其器件的源极和门极往往共享一面,而漏极往往独占一面。这样一来,将漏极作为静地点的功率器件(第一功率器件12),直接与散热单元11连接,既可以更好地进行电磁兼容,又方便制程。 
如图12,可以将背面的散热单元11拓宽/长,甚至折弯,使其部分超过封料16包覆的部分,以扩大表面积。超出封料16包覆的散热单元11的两面均可以实现和环境的热交换,因此,可以进一步加强功率模块10的散热性能。 
如图13,在某些场合下,封装体内部不仅仅需要搭载一些功率半导体器件,还需要集成一些控制功能。而控制线路通常比较复杂,因此需要使用布线密度还高的基板,如PCB板或者IC。在此态样中,可以将搭载控制线路的控制器件18,例如高密度布线板或者控制IC也封装至封装体内。 
如图14,控制器件18可以是导热系数较低,但是布线密度较高的高密度基板。以便可以集成更多的控制功能。控制器件18通常耐温等级较功率器件的耐温等级相比较低,因此,在控制器件18和散热单元11之间放置一个绝热层(热导率通常低于0.5W/m.K)工L。如此,可以降低控制器件18,以及其上所搭载器件的温度。 
如图15,上面所述散热单元11,不限于一整块,其上可以根据需要做进一步的分割,以形成一些电路图形,即散热单元11也可以具有多个电极。如此可以进一步增加功率模块设计的灵活性。 
功率模块10由于将多个器件集成在一起,相比分立器件,其电流流通回路被大大减少,从而降低了回路电感,即减少了损耗,又降低了电压噪音。但仍可以继续被优化。如图16,以所提及全桥电路为例,增加集成一高频电容器C至功率模块10内部,以进一步减少回路,降低回路电感量。 
通常电源变换器为了安全可靠,会实时监测功率半导体的温度状态,若温度过高或者升温过快,则说明电路有危险,可以提前采取预防动作,如关闭电 源等。分立器件的温度检测,只能在其外部增加温度传感器,所以,无法及时反映内部温度状态,且温度传感器的安装也较复杂。所以,功率模块中,还可以集成温度传感器,既提升了温度监测效果,又简化了使用。 
如图17所示,此态样的功率模块更包括一第二散热单元(heat sink)11a,其设置于第二功率器件14与导热绝缘材料层13之间。由于功率器件在工作过程中,例如会经历超过正常工作电流数倍以上的瞬时冲击,故,通过散热单元11a,可以在不增加导热绝缘材料层13(DBC)面积的情况下,改善搭载至DBC板上需要承受热冲击的组件的抗热冲击能力。另外,引线框架15系延伸与导热绝缘材料层13的线路层133连接。 
如图18所示,为了进一步改善导热绝缘材料层13(以DBC板为例)上发热量较大的组件(例如第二功率器件14)的抗热冲击的性能,以及进一步改善DBC上线路的承载电流的能力,降低电流传导阻抗,更可以将引线框架15的面积增加,通过一导电材料键合至DBC的线路层上。利用此结构开发的一款功率模块的实物照片见图19(未经封料包覆)。其中DBC基板通过钎焊的方式焊接至散热单元11上,而引线框架15同样通过钎焊的方式和DBC基板的线路层实现电气与机械连接。图19所示的功率模块10所使用的DBC基板,其线路层厚度为0.3mm,而引线框架15的厚度为0.5mm,因此,采用此结构的传导电阻和直接将芯片键合在DBC线路层上相比降低60%以上,如此可以有效降低模块产热量,从而提高模块的电性能,改善模块的散热性能。 
如图20所示,在功率模块10内除了使用导热能力较好的DBC基板以外,也可以使用类似铜基板13a等导热能力较好的基板。一般铜基板的结构为,在一较厚的铜衬底上,生成绝缘层和薄铜线路层。而且绝缘层和薄铜线路层的层数不以一层为限,可以是多层。在某些场合下可以实现更高的布线密度。 
一般而言,第一功率器件与第二功率器件皆由导线(wire bonding)来传输讯号,由于导线往往是用铝导线(Al wire)来完成,内阻很大。用金导线(Auwire),则成本太高。虽然最近工艺有铜导线(Cu wire)出现,但仍旧内阻很大。如图21所示,为进一步降低封装内阻造成的损耗,本发明可以用wirelessbond工艺,如铜片取代wire bond来实现电流传递,大大降低了封装内阻,且成本也不会太高。本态样是通过引线框架15延伸连结于第一功率器件12及第二功率器件14的至少一个而取代导线。 
图22所示为一进一步改善热传递能力的方案。由于本发明提及的功率模块,往往是有些器件(例如第一功率器件12)直接与散热单元11相连,而有些器件 (例如第二功率器件14)与散热单元11之间则有绝缘组件(例如具有绝缘层的导热绝缘材料层13),从而导致整个模块中封料16的厚度不均,也就是说,局部封料16与器件的距离会比较厚,使封料16的温度不均匀,从而影响了封料16表面的散热能力。图22中,在封料16较厚的地方增加热良导体的一第三散热单元11b,其系设置于第一散热单元11的第一区,从均匀化封料16至器件的厚度,而改善散热能力。 
另外,如图25所示,第三散热单元11b系穿出封料16,并具有一弯折。第三散热单元11b穿出封料16而可作为引脚Pin、或是单纯散热、或是部分作为引脚部分用来散热。第三散热单元11b通过弯折可减少功率模块10直立时的尺寸。 
实际应用中,若需进一步扩大散热能力,可以通过图26的方式达成。即在功率模块10的第三散热单元11b上再安装一第四散热单元11c。第四散热单元11c可通过焊接、粘结等方式与第三散热单元11b连结。由于安装简单第四散热单元11c的形状和位置可以不受限定。但实际效果上,以保留功率模块10自有表面散热能力为佳。即,如图26,在第四散热单元11c与功率模块10前表面A1之间保留一空隙,使得风流可以该空隙中流动,从而使功率模块前表面和第四散热单元11c下表面(靠近前表面A1的表面)均能发挥一定散热功能。为使该空隙中的风流能够达到相当的程度,该空隙厚度可大于1mm,尤以大于2mm为佳。 
为了更好地解释本发明的意义,进一步借助全桥电路来进行说明,如前所述,图9为全桥电路的拓扑图,图23和图24A至24D分别为其功率模块内部结构和三维示意图。其中,图24A为功率模块10的正面示意图,图24B为功率模块10的背面示意图,图24C为功率模块10脱去封料16的正面示意图,图24D为功率模块10脱去封料16的背面示意图。 
虽然上述实施例系以一第一功率器件12及一第二功率器件14为例作说明,但并非具限制性,且其中第一功率器件12所代表的意义为其设置于散热单元11上,而第二功率器件14所代表的意义为其通过一导热绝缘材料层13设置于散热单元11上。以下系以二个第一功率器件S1及S2以及二个第二功率器件S3及S4作说明。 
如图9所示,全桥电路包括4个开关器件S1~S4,这里以MOSFET为例。这四个开关器件组成两组导电桥臂:S1和S4组成一组,S2和S3组成一组桥臂;桥臂上管开关器件S1和S2的Drain端共同连接在电压高电位点Vin(在D2D应 用时,电气端Vin为直流输入端,是电压波形为一个稳定的直流或者带有很小纹波的直流),桥臂下管开关器件S3和S4的Source端共同连接在电压的低电位点GND;而单一桥臂上管的Source和下管的Drain相连接,如S1和S4桥臂连接于VA,S2和S3的桥臂连接于VB,其工作的基本原理是桥臂的上下管互补导通,如S1开通,S4关断;S1关断,S4开通,在开关状态转换过程存在短暂时间都关断的过程。这样,D2D的应用场合下,输入端Vin-GND之间为直流,而桥臂中间连接点VA,VB的电压则是开关次的跳变,幅值为0与Vin。 
目前大功率MOSFET最典型的电极引出方式为,芯片的背面为“Drain”,正面分布两个电极,“Source”和“Gate”,其中“Gate”的尺寸较小,例如1mm*1mm。芯片背面的“Drain”通常预先进行可钎焊处理,而正面的“Source”和“Gate”往往为铝金属化电极,可以通过铝/金wire bonding的方式实现和外围电路的连接。由于开关器件S1和S2的“Drain”连接于共同的直流电位点Vin,因此,可以将其直接钎焊至散热单元11上,而Vin和外界电连接的pin也可以直接钎焊至散热单元11上,从而利用该导电极佳的散热单元11导电,降低电损耗,减少封装体的热量产生。如此,可以获得最佳的热,电性能。而现有的功率模块,如前述习知的做法为,将所有四颗MOSFET安装至DBC板上,随后,所有MOSFET和引线框架的电连接均靠wire bonding的方式来实现。如上文所讨论的一样,现有技术的种种缺陷(散热差,电性能差,价格高,可靠性差等等)相比之下一目了然。 
本发明在此处的应用更具降低EMI的效果,前面对全桥电路的基本工作原理分析看。散热单元11连接于直流输入端Vin,为很好的静态电位点,而桥臂中间连接点VA,VB则为电压跳变点,大片的散热单元11可以有效阻断跳变信号的传递。如此,可以有效减小跳变点对外围电路的干扰,减小测试的EMI。 
如前所述,为了具备更好的EMC特性和散热性能,将全桥模块中的开关器件S3、S4置于绝缘层(即导热绝缘材料层具有的绝缘层)上,将开关器件S1、S2直接置于散热单元11上;为了方便生产,并减少生产工差造成的空间浪费,开关器件S3、S4置于相连的绝缘层上;为减少回路电感和方便使用,将S2置于S3外侧,将S1置于S4外侧。也就是说,对于图9所示的全桥电路来讲,模块内部器件按S2-S3-S4-S1或者S1-S4-S3-S2的顺序排布,性能更为优秀。 
以下说明本实施例的功率模块的制造流程,于此,导热绝缘材料层系以覆铜陶瓷基板为例,另外,此功率模块除了搭载功率器件(半导体芯片)外还集成了一些被动组件,如电阻和电容,且在引线框架其中一些引脚上还搭载了一 个温度测量电阻,以用作模块过温保护之用。具体的制作流程如下:先在散热单元11上组装导热绝缘材料层13的位置以及和引线框架15连接的位置涂上锡膏,同样将导热绝缘材料层13上需要和引线框架15组装的位置涂上锡膏,随后将散热单元11、导热绝缘材料层13和引线框架15按照设定的装配关系置于一治具中(Assembly);然后过回流焊炉(Reflow)使其焊接在一起,由此这三个部件形成一个整体,在随后植晶制程中可以利用引线框架15进行传输与定位;清洗(Flux Cleaning)后,进行植晶安装所需的半导体器件(如MOS及Diode),此处需要着重强调的是部分功率器件放置在散热单元11上(如第一功率器件12),另外一部分功率芯片放置在导热绝缘材料层13上(如第二功率器件14),植晶时所用的连接界面材料也是锡膏;在使用单一功能的植晶机时,由于其不具备抓取表面黏着(SMT)器件的能力,因此,一些电阻、电容等器件还需要进行SMT的操作,即:点锡膏(Solder Dispense)后,放置其它元器件(SMT);由于所用的功率器件的芯片尺寸较大,采用锡膏(solder paste)进行reflow时有焊接层的气孔率较高而带来工艺性、可靠性不佳的疑虑,此处采用真空回焊(Vacuum Reflow)使组件和散热单元11、导热绝缘材料层13、引线框架15、芯片、SMT器件焊接在一起;清洗(Flux Cleaning)后,进行打线接合(Wire bond)作业;包封(Molding或者其它金属/陶瓷封装形式)后即完成主要流程。 
于一些在植晶制程时无需使用引线框架15进行定位的应用下,有机会进一步简化工艺流程。首先将散热单元11、导热绝缘材料层13、引线框架15上需要的位置施加锡膏;随后将所需的组件(功率芯片以及被动SMT组件)分别放置于需要的位置上,这步骤可以通过泛用较强的机台(如集成植晶和表面黏着技术功能的机台)上而一站式实现,也可以在多个机台上实现,使用的连接界面材料可以为锡膏;随后将放置有组件的散热单元11、导热绝缘材料层13、引线框架15按照设定的装配关系放置于一治具中,完成assembly;随后真空reflow;后续的工艺和上述的工艺流程相同。如此,可以减少reflow的次数以及相应的清洗等流程,由于reflow次数的减少对于提高模块的可靠性也有一定的好处。 
当然也可以使用焊料片,导电胶,低温烧结纳米银浆,等材料代替锡膏作为模块组装所需的电性/机械连接的界面材料。在某些场合下甚至可以在同一模块组装过程中不同的装配位置使用超过一种连接接口材料。使用这些连接材料时,组装工艺以及流程也需要做对应的调整。 
芯片正面电极引出时也可以使用除打线外的其它方式,例如使用粘结/焊接一金属(铜)片,实现正面电极和外部线路的互联。 
综上,通过本发明所揭露的,用以提升电源变换器功率密度或者效率的封装方法和结构,可以获得与现有技术相比,更佳的热性能,电性能,经济性能,EMC性能与更高的可靠性。其内部空间利用率很高,使用方便,非常有利于提高变换器功率密度或者效率。而本发明给出的具体功率模块具体实施,也非常可行有效。本发明非常适合用以提升电源变换器的整体性能和性价比。 
以上所述仅为举例性,而非为限制性者。任何未脱离本发明的精神与范畴,而对其进行的等效修改或变更,均应包括于后附的申请专利范围中。 

Claims (27)

1.一种功率模块,其特征在于,包括:
一第一散热单元,具有一第一区及一第二区;
一第一功率器件,设置在该第一区;
一导热绝缘材料层,设置在该第二区,其包括一导热层、一绝缘层及一线路层;
一第二功率器件,通过该导热绝缘材料层设置在该第一散热单元,该第一功率器件与该第二功率器件分别具有至少两个电极,该第二功率器件是垂直型功率器件,该第二功率器件的一电极是直接与该线路层连接;
一引线框架,分别与该第一功率器件及该第二功率器件各自电极中的至少一个电极电性连接,以形成至少两个引脚;以及
一封料,是包覆该第一功率器件、该导热绝缘材料层、该第二功率器件及该引线框架的一部分,
其中,该第一散热单元与该第一功率器件电性连接,该第一散热单元与该第一功率器件的连接处形成一共接点,该共接点是一电压静地点。
2.根据权利要求1所述的功率模块,其特征在于,还包括:
一键接材料层,该第一功率器件通过该键接材料层连接该第一散热单元,该键接材料层材料是导热导电材料。
3.根据权利要求2所述的功率模块,其特征在于,其中该第一散热单元与该引线框架一体成型。
4.根据权利要求2所述的功率模块,其特征在于,其中该第一散热单元完全设置在封料内、或部分位在封料外、或完全位在封料外。
5.根据权利要求1所述的功率模块,其特征在于,其中该引脚是穿出该封料。
6.根据权利要求2所述的功率模块,其特征在于,其中该第一散热单元是分割为多个部分。
7.根据权利要求1所述的功率模块,其特征在于,其中该引线框架延伸而连结在该线路层。
8.根据权利要求2所述的功率模块,其特征在于,其中该引线框架延伸而连结在该第一功率器件及该第二功率器件的至少一个。
9.根据权利要求2所述的功率模块,其特征在于,还包括:
一第二散热单元,设置在该第二功率器件与该导热绝缘材料层之间。
10.根据权利要求2所述的功率模块,其特征在于,还包括:
一第三散热单元,设置在该第一区或者由该第一散热单元延展而成。
11.根据权利要求10所述的功率模块,其特征在于,其中该第三散热单元是穿出该封料。
12.根据权利要求10所述的功率模块,其特征在于,其中该第三散热单元是穿出该封料并具有一弯折。
13.根据权利要求11所述的功率模块,其特征在于,还包括:
一第四散热单元,与该第三散热单元连结,并与该封料具有一空隙。
14.根据权利要求2所述的功率模块,其特征在于,其中该导热绝缘材料层是金属化陶瓷基板。
15.根据权利要求2所述的功率模块,其特征在于,还具有一排引脚,其穿出该封料,并用于讯号传送或散热。
16.根据权利要求2所述的功率模块,其特征在于,还包括:
一控制器件,设置在该第一区。
17.根据权利要求16所述的功率模块,其特征在于,还包括:
一绝热层,设置在该控制器件与该第一散热单元之间。
18.根据权利要求2所述的功率模块,还包括:
一高频电容器,集成在该功率模块内。
19.根据权利要求2所述的功率模块,其特征在于,还包括:
一温度传感器,集成在该功率模块内。
20.根据权利要求2所述的功率模块,其特征在于,其中该第一功率器件和该第二功率器件的至少一个具有至少三个电极。
21.根据权利要求20所述的功率模块,其特征在于,还包括:
至少一个功率器件,该第一功率器件、该第二功率器件及该至少一个功率器件的至少二个具有至少三个电极。
22.根据权利要求2所述的功率模块,其特征在于,其中该封料的导热系数高于1.2W/m.K。
23.根据权利要求2所述的功率模块,其特征在于,其中该封料的导热系数高于1.8W/m.K。
24.一种功率模块的制造方法,其特征在于,包括:
一装配步骤,将第一散热单元、一导热绝缘材料层及一引线框架按照设定的装配关系,使用连接接口材料,组装至一起,其中导热绝缘材料层覆盖第一散热单元的第一区域;
一植晶及正面电极引出步骤,将一第一功率器件通过连接接口材料设置在该第一散热单元的第二区域上,并将一第二功率器件通过连接接口材料设置在该导热绝缘材料层上,该引线框架,分别与该第一功率器件及该第二功率器件各自电极中的至少一个电极电性连接,该第一散热单元与该第一功率器件电性连接,该第一散热单元与该第一功率器件的连接处形成一共接点,该共接点是一电压静地点;
一包封步骤,通过一封料包覆该第一功率器件、该导热绝缘材料层、该第二功率器件及该引线框架的一部分,
其中,该导热绝缘材料层包括一导热层、一绝缘层及一线路层,该第一功率器件与该第二功率器件分别具有至少两个电极,该第二功率器件是垂直型功率器件,该第二功率器件的一电极是直接与该线路层连接。
25.根据权利要求24所述的功率模块的制造方法,其特征在于,其中在该装配步骤中,是在该散热单元上组装该导热绝缘材料层的位置以及和该引线框架连接的位置施加连接材料,并将该导热绝缘材料层上需要和该引线框架组装的位置施加连接材料。
26.根据权利要求24所述的功率模块的制造方法,其特征在于,其中连接材料是锡膏、焊料片、导电胶或低温烧结纳米银浆。
27.根据权利要求24所述的功率模块的制造方法,其特征在于,其中芯片正面电极引出工艺是打线或粘结/焊接金属片。
CN201010230160.7A 2010-07-15 2010-07-15 功率模块及其制造方法 Active CN102339818B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201010230160.7A CN102339818B (zh) 2010-07-15 2010-07-15 功率模块及其制造方法
US13/049,322 US8472196B2 (en) 2010-07-15 2011-03-16 Power module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201010230160.7A CN102339818B (zh) 2010-07-15 2010-07-15 功率模块及其制造方法

Publications (2)

Publication Number Publication Date
CN102339818A CN102339818A (zh) 2012-02-01
CN102339818B true CN102339818B (zh) 2014-04-30

Family

ID=45466833

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201010230160.7A Active CN102339818B (zh) 2010-07-15 2010-07-15 功率模块及其制造方法

Country Status (2)

Country Link
US (1) US8472196B2 (zh)
CN (1) CN102339818B (zh)

Families Citing this family (62)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9030003B2 (en) * 2011-04-05 2015-05-12 Panasonic Intellectual Property Management Co., Ltd. Encapsulated semiconductor device and method for manufacturing the same
JP5798412B2 (ja) * 2011-08-25 2015-10-21 日産自動車株式会社 半導体モジュール
ITMI20112300A1 (it) 2011-12-19 2013-06-20 St Microelectronics Srl Realizzazione di dispositivi elettronici di tipo dsc tramite inserto distanziatore
WO2013118478A1 (ja) * 2012-02-09 2013-08-15 富士電機株式会社 半導体装置
WO2013140703A1 (ja) * 2012-03-22 2013-09-26 富士電機株式会社 電力変換装置
US8941208B2 (en) 2012-07-30 2015-01-27 General Electric Company Reliable surface mount integrated power module
JP5863599B2 (ja) * 2012-08-21 2016-02-16 三菱電機株式会社 パワーモジュール
US8829692B2 (en) * 2012-09-04 2014-09-09 Rolls-Royce Corporation Multilayer packaged semiconductor device and method of packaging
JP6099453B2 (ja) * 2012-11-28 2017-03-22 Dowaメタルテック株式会社 電子部品搭載基板およびその製造方法
CN103619031A (zh) * 2012-12-18 2014-03-05 徐培杰 无线网络自适应功控设置算法
JP6075128B2 (ja) * 2013-03-11 2017-02-08 株式会社ジェイテクト 駆動回路装置
US8987876B2 (en) 2013-03-14 2015-03-24 General Electric Company Power overlay structure and method of making same
CN104052244B (zh) * 2013-03-14 2019-12-13 珠海格力电器股份有限公司 功率模块
US10269688B2 (en) 2013-03-14 2019-04-23 General Electric Company Power overlay structure and method of making same
US9093564B2 (en) * 2013-03-20 2015-07-28 International Business Machines Corporation Integrated passive devices for FinFET technologies
CN103325701A (zh) * 2013-06-05 2013-09-25 吉林华微斯帕克电气有限公司 功率模块pcb板安装方法、安装结构及功率模块
CN103346136B (zh) * 2013-06-05 2016-01-27 吉林华微斯帕克电气有限公司 功率模块及其封装方法
CN104347582A (zh) * 2013-07-31 2015-02-11 浙江大学苏州工业技术研究院 一种提高器件纵向耐压能力的半导体装置封装结构
US20150075849A1 (en) * 2013-09-17 2015-03-19 Jia Lin Yap Semiconductor device and lead frame with interposer
WO2015045648A1 (ja) * 2013-09-30 2015-04-02 富士電機株式会社 半導体装置、半導体装置の組み立て方法、半導体装置用部品及び単位モジュール
US9312231B2 (en) * 2013-10-31 2016-04-12 Freescale Semiconductor, Inc. Method and apparatus for high temperature semiconductor device packages and structures using a low temperature process
CN104716128B (zh) * 2013-12-16 2019-11-22 台达电子企业管理(上海)有限公司 功率模块、电源变换器以及功率模块的制造方法
CN108988836B (zh) * 2013-12-16 2023-02-28 台达电子企业管理(上海)有限公司 控制方法及功率电路的封装结构
US20150342069A1 (en) * 2014-05-20 2015-11-26 Freescale Semiconductor, Inc. Housing for electronic devices
DE102014211562A1 (de) * 2014-06-17 2015-12-17 Robert Bosch Gmbh Halbleiteranordnung mit einer Wärmesenke
JP6483498B2 (ja) 2014-07-07 2019-03-13 ローム株式会社 電子装置およびその実装構造
DE102014117943B4 (de) * 2014-12-05 2022-12-08 Infineon Technologies Austria Ag Vorrichtung mit einer Leiterplatte und einem Metallwerkstück
CH710644B1 (de) * 2015-01-22 2018-10-15 Melexis Tech Sa Verfahren zur Herstellung von Stromsensoren.
CN104779174B (zh) * 2015-03-23 2018-05-01 广东美的制冷设备有限公司 功率模块的制作方法
CN104767396B (zh) * 2015-03-23 2017-11-14 广东美的制冷设备有限公司 智能功率模块及其制造方法
US9867932B2 (en) 2015-10-30 2018-01-16 International Business Machines Corporation Drug delivery device having a cavity sealed by a pressurized membrane
DE102016000264B4 (de) * 2016-01-08 2022-01-05 Infineon Technologies Ag Halbleiterchipgehäuse, das sich lateral erstreckende Anschlüsse umfasst, und Verfahren zur Herstellung desselben
TWI619212B (zh) * 2016-03-17 2018-03-21 瑞昱半導體股份有限公司 用於半導體裝置之接合線式散熱結構
JP6724449B2 (ja) * 2016-03-18 2020-07-15 富士電機株式会社 半導体装置および半導体装置の製造方法
CN105870096A (zh) * 2016-04-01 2016-08-17 无锡麟力科技有限公司 一种基于单基岛sot23引线框架的多芯片封装结构
CN105932005A (zh) * 2016-04-01 2016-09-07 无锡麟力科技有限公司 一种基于通用esop8引线框架的多芯片封装结构
US10291065B2 (en) * 2016-04-04 2019-05-14 Computime, Ltd. Robust and high current smart-plug
CN107295755A (zh) * 2016-04-13 2017-10-24 讯芯电子科技(中山)有限公司 覆铜陶瓷基板的制造方法
CN106024651A (zh) * 2016-07-29 2016-10-12 广东美的制冷设备有限公司 一种智能功率模块及其制造方法
CN106098652A (zh) * 2016-08-19 2016-11-09 广东美的制冷设备有限公司 一种智能功率模块及其制造方法
CN106298698A (zh) * 2016-08-31 2017-01-04 广东美的制冷设备有限公司 一种智能功率模块及其制造方法
CN106067450A (zh) * 2016-07-29 2016-11-02 广东美的制冷设备有限公司 一种智能功率模块及其制造方法
US10404186B2 (en) 2016-10-27 2019-09-03 General Electric Company Power module systems and methods having reduced common mode capacitive currents and reduced electromagnetic interference
JP6665759B2 (ja) * 2016-11-10 2020-03-13 三菱電機株式会社 高周波回路
FR3060847B1 (fr) * 2016-12-21 2020-12-04 Valeo Systemes De Controle Moteur Module electronique de puissance comprenant une face d'echange thermique
CN108257923A (zh) * 2016-12-29 2018-07-06 比亚迪股份有限公司 一种散热基板及其制备方法和应用以及电子元器件
CN108257922A (zh) * 2016-12-29 2018-07-06 比亚迪股份有限公司 一种散热基板及其制备方法和应用以及电子元器件
CN107808858A (zh) * 2017-11-08 2018-03-16 深圳芯能半导体技术有限公司 功率器件及其功率组件
CN108321134A (zh) * 2018-04-09 2018-07-24 黄山宝霓二维新材科技有限公司 高功率密度塑封式ipm模块的封装结构及加工工艺
CN108387803A (zh) * 2018-04-26 2018-08-10 艾乐德电子(南京)有限公司 一种电子负载测试装置
CN109920785A (zh) * 2019-03-13 2019-06-21 黄山学院 双面散热ipm混合模块的封装结构及加工工艺
CN110676237A (zh) * 2019-09-15 2020-01-10 天水华天电子集团股份有限公司 基于微小级别ssop封装的散热智能功率半导体模块及其制备方法与应用
CN110620094A (zh) * 2019-10-12 2019-12-27 芜湖启迪半导体有限公司 一种功率半导体器件的封装结构及其封装工艺
CN113053833A (zh) * 2019-12-26 2021-06-29 财团法人工业技术研究院 一种半导体装置及其制作方法
TWI764256B (zh) * 2020-08-28 2022-05-11 朋程科技股份有限公司 智慧功率模組封裝結構
JP2022063589A (ja) * 2020-10-12 2022-04-22 株式会社マキタ 作業機
DE102021102924A1 (de) * 2021-02-09 2022-08-11 Avl Software And Functions Gmbh Leistungsmodul mit reduzierter intrinsischer Induktivität
DE102021105264B4 (de) * 2021-03-04 2024-05-29 Infineon Technologies Ag Leistungselektronikmodul und Verfahren zur Herstellung eines Leistungselektronikmoduls
CN113066727A (zh) * 2021-03-19 2021-07-02 深圳市汇顶科技股份有限公司 芯片组件的制作方法、芯片组件及电子设备
CN113421863B (zh) * 2021-05-07 2023-05-05 华为数字能源技术有限公司 功率半导体封装器件及功率变换器
CN114449739A (zh) * 2022-01-27 2022-05-06 华为数字能源技术有限公司 封装模组及其制备方法、电子设备
CN116364695B (zh) * 2023-01-31 2024-05-14 海信家电集团股份有限公司 功率模块及其电子设备

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5057906A (en) * 1989-05-22 1991-10-15 Kabushiki Kaisha Toshiba Plastic molded type semiconductor device
US6257215B1 (en) * 1999-03-18 2001-07-10 Hitachi, Ltd. Resin-sealed electronic apparatus for use in internal combustion engines
US6313520B1 (en) * 2000-03-07 2001-11-06 Mitsubishi Denki Kabushiki Kaisha Resin-sealed power semiconductor device including substrate with all electronic components for control circuit mounted thereon
CN101496163A (zh) * 2005-08-26 2009-07-29 库尔选项公司 用于微电子元件的电路小片级封装的热导性热塑性塑料

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1222152B (it) * 1987-07-28 1990-09-05 Sgs Microelettronica Spa Dispositivo a piu' piastrine di materiale in contenitore di metallo e resina
US5049973A (en) * 1990-06-26 1991-09-17 Harris Semiconductor Patents, Inc. Heat sink and multi mount pad lead frame package and method for electrically isolating semiconductor die(s)
JP2708320B2 (ja) * 1992-04-17 1998-02-04 三菱電機株式会社 マルチチップ型半導体装置及びその製造方法
US5353498A (en) * 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
JP3429921B2 (ja) * 1995-10-26 2003-07-28 三菱電機株式会社 半導体装置
JPH09208668A (ja) * 1996-02-06 1997-08-12 Toshiba Chem Corp エポキシ樹脂組成物および半導体封止装置
JP3241279B2 (ja) * 1996-11-14 2001-12-25 株式会社日立製作所 保護機能付きスイッチ回路
US6137165A (en) * 1999-06-25 2000-10-24 International Rectifier Corp. Hybrid package including a power MOSFET die and a control and protection circuit die with a smaller sense MOSFET
KR100335481B1 (ko) * 1999-09-13 2002-05-04 김덕중 멀티 칩 패키지 구조의 전력소자
JP3511136B2 (ja) * 2000-09-25 2004-03-29 日立化成工業株式会社 封止用エポキシ樹脂成形材料及び半導体装置
DE10122363B4 (de) * 2001-05-09 2007-11-29 Infineon Technologies Ag Halbleitermodul
DE10149774A1 (de) * 2001-10-09 2003-04-24 Bosch Gmbh Robert Verfahren zum Verpacken von elektronischen Baugruppen und Mehrfachchipverpackung
US6946740B2 (en) * 2002-07-15 2005-09-20 International Rectifier Corporation High power MCM package
JP2005146229A (ja) * 2003-11-20 2005-06-09 Matsushita Electric Works Ltd 封止用エポキシ樹脂組成物及びそれを用いた半導体装置
US7868465B2 (en) * 2007-06-04 2011-01-11 Infineon Technologies Ag Semiconductor device with a metallic carrier and two semiconductor chips applied to the carrier
KR101505551B1 (ko) * 2007-11-30 2015-03-25 페어차일드코리아반도체 주식회사 온도 감지소자가 장착된 반도체 파워 모듈 패키지 및 그제조방법
US8207607B2 (en) * 2007-12-14 2012-06-26 Denso Corporation Semiconductor device with resin mold
KR101448850B1 (ko) * 2008-02-04 2014-10-14 페어차일드코리아반도체 주식회사 반도체 패키지 및 그 제조방법들
US7847375B2 (en) * 2008-08-05 2010-12-07 Infineon Technologies Ag Electronic device and method of manufacturing same
KR101555300B1 (ko) * 2008-12-05 2015-09-24 페어차일드코리아반도체 주식회사 외부 본딩 영역을 구비하는 반도체 파워 모듈 패키지

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5057906A (en) * 1989-05-22 1991-10-15 Kabushiki Kaisha Toshiba Plastic molded type semiconductor device
US6257215B1 (en) * 1999-03-18 2001-07-10 Hitachi, Ltd. Resin-sealed electronic apparatus for use in internal combustion engines
US6313520B1 (en) * 2000-03-07 2001-11-06 Mitsubishi Denki Kabushiki Kaisha Resin-sealed power semiconductor device including substrate with all electronic components for control circuit mounted thereon
CN101496163A (zh) * 2005-08-26 2009-07-29 库尔选项公司 用于微电子元件的电路小片级封装的热导性热塑性塑料

Also Published As

Publication number Publication date
US20120014069A1 (en) 2012-01-19
US8472196B2 (en) 2013-06-25
CN102339818A (zh) 2012-02-01

Similar Documents

Publication Publication Date Title
CN102339818B (zh) 功率模块及其制造方法
CN102340233B (zh) 功率模块
CN107170714B (zh) 一种低寄生电感功率模块及双面散热低寄生电感功率模块
CN104716128B (zh) 功率模块、电源变换器以及功率模块的制造方法
CN107170720A (zh) 一种叠层封装双面散热功率模块
CN100435333C (zh) 电力半导体装置
CN102446880B (zh) 包括插件的半导体模块和用于生产包括插件的半导体模块的方法
CN107195623A (zh) 一种双面散热高可靠功率模块
TWI455286B (zh) 功率模組及功率模組之製造方法
CN110506330A (zh) 功率电子模块以及包含该模块的电功率变换器
CN103140103B (zh) 智能功率模块的封装结构
TWI446462B (zh) 功率模組
CN106684076B (zh) 封装结构及其制造方法
CN207165543U (zh) 一种低寄生电感双面散热功率模块
CN106298724B (zh) 塑封型功率模块
CN107146775A (zh) 一种低寄生电感双面散热功率模块
CN207165564U (zh) 一种双面散热高可靠功率模块
CN112701094A (zh) 一种功率器件封装结构及电力电子设备
CN110060991B (zh) 智能功率模块及空调器
CN207038508U (zh) 一种叠层封装双面散热功率模块
CN218123406U (zh) 功率器件及功率设备
CN115064512A (zh) 一种双面散热高频大功率模组及其制作方法
CN210379038U (zh) 用于布置芯片的引线框架、封装体以及电源模块
CN202948921U (zh) 非绝缘型功率模块
CN102723420B (zh) 一种支架与led灯

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant