WO2018137280A1 - 芯片封装器件及封装方法 - Google Patents

芯片封装器件及封装方法 Download PDF

Info

Publication number
WO2018137280A1
WO2018137280A1 PCT/CN2017/077439 CN2017077439W WO2018137280A1 WO 2018137280 A1 WO2018137280 A1 WO 2018137280A1 CN 2017077439 W CN2017077439 W CN 2017077439W WO 2018137280 A1 WO2018137280 A1 WO 2018137280A1
Authority
WO
WIPO (PCT)
Prior art keywords
chip
layer
chips
substrate
packaging method
Prior art date
Application number
PCT/CN2017/077439
Other languages
English (en)
French (fr)
Inventor
张万宁
于德泽
Original Assignee
新加坡有限公司
张万宁
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 新加坡有限公司, 张万宁 filed Critical 新加坡有限公司
Priority to US16/480,622 priority Critical patent/US10937767B2/en
Publication of WO2018137280A1 publication Critical patent/WO2018137280A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4871—Bases, plates or heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3142—Sealing arrangements between parts, e.g. adhesion promotors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492—Bases or plates or solder therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5381—Crossover interconnections, e.g. bridge stepovers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H01L2224/214—Connecting portions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24101—Connecting bonding areas at the same height
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821—Forming a build-up interconnect
    • H01L2224/82101—Forming a build-up interconnect by additive methods, e.g. direct writing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H01L2224/83815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8384—Sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/95001—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]

Definitions

  • the present invention relates to the technical field of chip packaging, and in particular, to a chip package device and a packaging method.
  • Insulated Gate Bipolar Transistor is a composite full-voltage-driven power semiconductor device composed of BJT (bipolar transistor) and MOS (insulated gate field effect transistor), which is high in MOS.
  • BJT bipolar transistor
  • MOS insulated gate field effect transistor
  • GTR giant transistor
  • the GTR saturation voltage is reduced, the current carrying density is large, but the driving current is large, the MOS driving power is small, the switching speed is fast, but the conduction voltage drop is large, and the current carrying density is small.
  • IGBT combines the advantages of the above two devices, the driving power is small and the saturation voltage is reduced. It is very suitable for converter systems with DC voltages of 600v and above, such as AC motors, inverters, switching power supplies, lighting circuits, traction drives, etc.
  • the package structure includes: an aluminum silicon carbide heat dissipation plate 1 , and a first solder layer sequentially disposed on the aluminum silicon carbide heat dissipation plate 1 .
  • the diode chips 8 and the IGBT 9 are separated from each other on the layer 6.
  • the diode chip 8, the IGBT 9 and the third copper layer 7 are connected by a wire 10.
  • the wire 10 is generally a gold wire, an aluminum wire or a copper wire.
  • the disadvantage of the wire connection is that the wire is long, the resistance is large, and the electrical energy is converted into unnecessary heat energy.
  • the metal wire of the power device In order to ensure low resistivity and to enhance heat dissipation, the metal wire of the power device must use a thick wire of 0.1 mm or more, and an ordinary one of only 0.25 mm. In this way, the interconnection distance between the chip and the substrate is large, and the interconnection between the chips is larger than that of the ordinary chip, so that the area of the terminal product is relatively large.
  • the technical solution of the present invention is a chip packaging method, which includes the following steps:
  • Step S01 providing a carrier board, the carrier board is provided with a first bonding layer;
  • Step S02 placing a plurality of chips on the first bonding layer at intervals;
  • Step S03 forming a plastic sealing layer on the carrier plate by a plastic sealing process, the plastic sealing layer filling a gap between the plurality of chips to form a plastic sealing chip;
  • Step S04 removing the carrier board and the first bonding layer
  • Step S05 forming an insulating layer on the plastic chip, forming an opening on the insulating layer, forming a metal conductor layer and an interconnection circuit between the chips in the opening;
  • Step S06 cutting the plastic chip to form a plurality of modules.
  • Step S07 providing a substrate, the substrate is formed with a plurality of metal pad structures, and the metal pad structure is in one-to-one correspondence with the chips in the module;
  • Step S08 forming a second bonding layer on the metal pad structure
  • Step S09 bonding the module to one side of the insulating layer to the substrate.
  • step S09 the material of the second bonding layer is solder; in step S09, the module is placed on the substrate by a chip mounter, and the module is moved away from the insulating layer by a reflow furnace. The side is bonded to the substrate.
  • the material of the second bonding layer is a sintered material; in step S09, the module is placed on the substrate by a mounter, and the module is kept away from the One side of the edge layer is bonded to the substrate.
  • the material of the second bonding layer is a conductive paste; in step S09, the module is placed on the substrate by a mounter, and the module is kept away from the insulating layer by baking. One side is bonded to the substrate.
  • the substrate is made of metal and has a conductive function or a heat dissipation function.
  • the carrier board is circular, square or rectangular.
  • the distance between adjacent chips is greater than or equal to 50 um.
  • the plastic sealing process is a pressure molding process or an injection molding process, and the plastic sealing layer is made of epoxy resin.
  • the thickness of the plastic sealing layer is equal to the thickness of the chip.
  • the thickness of the plastic sealing layer is smaller than the thickness of the chip, and the surface of the plastic sealing layer is 2 um to 10 um lower than the surface of the chip on a side close to the substrate.
  • a circuit is disposed on a front surface of the chip, and an electrode is disposed on a back surface of the chip, and a back surface of the chip is placed on the first bonding layer.
  • step S05 the steps of forming the metal conductor layer and the interconnection circuit between the chips include:
  • the metal seed layer that is not plated is removed.
  • the present invention further provides a chip package device, which is packaged by the chip package method described above, and the chip package device includes:
  • the chip package device and the packaging method provided by the invention have the following beneficial effects:
  • a plurality of chips are placed on a carrier plate provided with a first bonding layer, and then a plastic sealing layer is formed on the carrier plate by a plastic sealing process, the plastic sealing layer filling a plurality of the chips
  • the gap forms a plastic-sealed chip, thereby reducing the distance between the chips, and finally reducing the area of the terminal product, which is advantageous for miniaturization of the terminal product;
  • the present invention deposits a metal seed layer by sputtering in an opening of an insulating layer, and forms a metal conductor layer and an interconnection circuit between the chips by electroplating the metal seed layer, and the inter-metal interconnection resistance is higher than that of the prior art.
  • the connected resistance is small, thereby reducing energy loss and improving the efficiency of the semiconductor device.
  • FIG. 1 is a schematic diagram of a package structure of an IGBT module in the prior art.
  • FIG. 2 is a flowchart of a chip packaging method according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a chip according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of each step of a chip packaging method according to an embodiment of the present invention.
  • the present invention provides a chip packaging method and a chip package device formed by the package method, the chip packaging method comprising the steps of: providing a carrier board, the carrier board is provided with a first bonding layer; Forming a chip on the first bonding layer; forming a plastic sealing layer on the carrier plate by a plastic sealing process, the plastic sealing layer filling a gap between the plurality of chips to form a plastic chip; a carrier layer and a first bonding layer; forming an insulating layer on the plastic chip, forming an opening in the insulating layer, depositing a metal in the opening to form a metal conductor layer, and an interconnection circuit between the chips Cutting the packaged chip to form a plurality of modules.
  • the present invention deposits a plurality of chips on a carrier plate provided with a first bonding layer, and then forms a plastic sealing layer on the carrier plate by a plastic sealing process, the plastic sealing layer filling between the plurality of chips
  • the gap forms a plastic package chip, thereby reducing the distance between the chips, and finally reducing the area of the terminal product, which is advantageous for miniaturization of the terminal product.
  • FIG. 2 is a flowchart of a chip packaging method according to an embodiment of the present invention. As shown in FIG. 2, the present invention provides a chip packaging method, including the following steps:
  • Step S01 providing a carrier board, the carrier board is provided with a first bonding layer;
  • Step S02 placing a plurality of chips on the first bonding layer at intervals;
  • Step S03 forming a plastic sealing layer on the carrier plate by a plastic sealing process, the plastic sealing layer filling a gap between the plurality of chips to form a plastic sealing chip;
  • Step S04 removing the carrier board and the first bonding layer
  • Step S05 forming an insulating layer on the plastic chip, forming an opening on the insulating layer, depositing a metal in the opening to form a metal conductor layer and an interconnection circuit between the chips;
  • Step S06 cutting the packaged chip to form a plurality of modules
  • Step S07 providing a substrate on which a plurality of metal pad structures are formed, the metal The pad structure has a one-to-one correspondence with the chips in the module;
  • Step S08 forming a second bonding layer on the metal pad structure
  • Step S09 bonding the module to one side of the insulating layer to the substrate.
  • FIG. 4 to FIG. 12 are schematic diagrams showing the steps of the steps of the chip packaging method according to an embodiment of the present invention. Referring to FIG. 2 and FIG. 4 to FIG. 12, the chip packaging method proposed by the present invention is described in detail:
  • step S01 a carrier board 201 is provided, and the carrier board 201 is provided with a first bonding layer 202, as shown in FIG.
  • the carrier board 201 is circular, square or rectangular.
  • the first bonding layer 202 has a property of lowering its adhesion under high temperature or light conditions.
  • step S02 a plurality of chips 100 are placed on the first bonding layer 202 at intervals, as shown in FIG.
  • the distance between adjacent chips 100 is greater than or equal to 50 um, for example, the distance between adjacent chips 100 is 50 um, 60 um or 70 um.
  • FIG. 3 is a chip provided by an embodiment of the present invention.
  • the chip 100 includes a semiconductor sink 150, an insulating layer 140 is disposed on a front surface of the semiconductor substrate 150, and a recess is formed in the insulating layer 140.
  • the metal is filled with a gate 120 and an emitter 130 of the chip 100 as an input end and an output end of the chip, and a collector 110 is disposed on the back surface of the semiconductor substrate 150.
  • the back surface of the semiconductor substrate 150 is placed on the first bonding layer.
  • the front surface and the back surface of the semiconductor substrate 150 are opposite.
  • the side away from the first bonding layer 201 is the semiconductor substrate 150 .
  • the front side is a back surface of the semiconductor substrate 150 near one side of the first bonding layer 201.
  • step S03 a plastic sealing layer 203 is formed on the carrier plate 201 by a plastic sealing process, and the plastic sealing layer 203 fills a gap between the plurality of the chips 100 to form a plastic sealing chip 200. 6 is shown.
  • the molding process is a pressure molding process or an injection molding process
  • the material of the plastic sealing layer 203 is epoxy resin.
  • the epoxy resin and the chip are integrally molded by a pressure molding process or an injection molding process to form a plastic package chip.
  • the epoxy resin forms a plastic sealing layer 203, and the plastic sealing layer 203 fills a gap between the plurality of chips, that is, the plastic sealing layer 203 surrounds the periphery of the chip 100, and the plastic sealing layer 203 and the chip
  • the upper surface of 100 is flush.
  • the plastic chip can be designed to be circular, square or rectangular according to the shape of the carrier plate 101.
  • the thickness of the plastic sealing layer 203 is equal to the thickness of the chip 100, or the thickness of the plastic sealing layer 203 may also be smaller than the thickness of the chip 100. For example, the thickness of the plastic sealing layer 203 is greater than the thickness of the chip 100.
  • the size of the collector 110 on the back side of the chip 100 is 2 um to 10 um higher than that of the plastic encapsulation layer 203.
  • the epoxy resin comprises a low thermal expansion coefficient polymer material having a volume concentration of 7 ppm to 9 ppm, for example, a low thermal expansion coefficient polymer material having a volume concentration of 7 ppm, 8 ppm or 9 ppm.
  • the low thermal expansion coefficient polymer material refers to a polymer material having a thermal expansion coefficient of less than 4 ⁇ 10 / ° C.
  • step S04 the carrier board 201 and the first bonding layer 202 are removed to form a plastic package chip 300, as shown in FIG.
  • step S05 an insulating layer 301 is formed on the plastic package chip 300, an opening is formed in the insulating layer 301, and a metal is formed in the opening to form a metal conductor layer 302 and an interconnection circuit 303 between the chips. As shown in Figure 8.
  • a first insulating layer 301 is coated on the molding chip 300, and the insulating material in the insulating layer 301 is a ultraviolet photolithography material commonly used in integrated circuit packaging.
  • a developing process forms an opening at a position corresponding to a gate and an emitter of the chip 100. The opening extends to the upper surface of the chip 100.
  • a metal seed layer is deposited on the first insulating layer 301 using a sputtering method to a thickness of 0.2 um to 0.5 um for the purpose of plating a metal to form a wire.
  • a photoresist is coated on the metal seed layer, exposed and developed, the position of the opening is exposed, the exposed metal seed layer is electroplated, and then the photoresist is removed and removed by acid etching.
  • the metal seed layer that is not plated forms a metal conductor layer 302 and an interconnection circuit 303 between the chips.
  • a second insulating layer 304 is coated on the surface of the device formed as described above, and a hole is formed at a specific position to form an opening 305 of the insulating layer as an interface with an external circuit.
  • step S06 the plastic chip is cut to form a plurality of modules 400, as shown in FIG.
  • the module 400 can be a single chip or a multi-chip integration. In this embodiment, two chips are taken as an example for description.
  • a substrate 500 is provided.
  • the substrate 500 is formed with a plurality of metal pad structures, and the metal pad structure is in one-to-one correspondence with the chips in the module, as shown in FIG.
  • the substrate 500 is made of metal and has a conductive function or a heat dissipation function.
  • the position of the metal pad structure (not shown) on the substrate 500 corresponds one-to-one with the chips in the module. That is to say, if two chips are included in the module, two metal pad structures are also disposed on the substrate, and the distance between the metal pad structures is equal to the distance between the chips.
  • a second bonding layer 501 is formed on the metal pad structure as shown in FIG.
  • the material of the second bonding layer 501 is solder, or a low-temperature sintered material, or a conductive paste, or other materials known to those skilled in the art.
  • step S09 the side of the module 400 away from the insulating layer is bonded to the substrate 500 to form a structure as shown in FIG.
  • the module 400 is placed on the substrate 500 by a mounter.
  • the side of the module 400 away from the insulating layer is placed on the side of the substrate 500 on which the second adhesive layer 501 is disposed. on.
  • the second bond The material of the layer 501 is solder
  • the sintering furnace the material of the second bonding layer 501 is a sintered material
  • baked the material of the second bonding layer 501 is a conductive adhesive
  • the present invention forms a plastic sealing layer 203 on the carrier board 201 by placing a plurality of chips 100 on the carrier board 201 provided with the first bonding layer 202, and the plastic sealing layer 203 is filled with a plurality of layers.
  • the gap between the chips 100 forms the plastic package chip 200, so that the distance between the chips 100 can be reduced, and the area of the terminal product is finally reduced, which is advantageous for miniaturization of the terminal product.
  • the present invention forms a metal seed layer by sputtering in the opening of the insulating layer, and forms a metal conductor layer 302 and an interconnection circuit 303 between the chips by electroplating the metal seed layer, and the inter-metal interconnection resistance is higher than that in the prior art.
  • the wire connection has a small resistance, thereby reducing energy loss and improving the efficiency of the semiconductor device.
  • the present invention also provides a chip package device, which is packaged by the chip package method described above.
  • the chip package device includes: a substrate 500, a plurality of spaced apart second bonding layers 501 formed on the substrate 500; and a plurality of chips 100 respectively located on the second bonding layer On the layer 501, the chip 100 is in one-to-one correspondence with the second bonding layer 501; a plastic sealing layer 203 is disposed on the substrate 500 and the second bonding layer 501 and surrounds the chip 100; a plastic sealing layer 203 and an insulating layer 301 on the chip 100; an opening in the insulating layer 301, the opening extending to the chip 100; a metal conductor layer 302 formed in the opening and Interconnect circuit 303 between the chips. Also included is a second insulating layer 304 over the insulating layer 301 and the interconnecting circuit 303, and an insulating layer opening 305.
  • the chip package device provided by the invention can minimize the distance between the chips 100 by 50 um, which greatly reduces the distance between the chips compared with the prior art 500 um, thereby finally reducing the area of the terminal product. Conducive to the miniaturization of terminal products. Moreover, in the chip package device provided by the present invention, the metal interconnection is used instead of the wire connection in the prior art, and the resistance of the connection is largely reduced, and the inter-metal interconnection resistance is only 30% to 50 of the line connection resistance. %,From The energy loss is reduced, and the efficiency of the semiconductor device is improved.
  • the chip package device and the packaging method provided by the present invention are formed by placing a plurality of chips on a carrier plate provided with a first adhesive layer, and then forming a plastic seal layer on the carrier plate by a plastic sealing process.
  • the plastic sealing layer fills a gap between the plurality of chips to form a plastic chip, thereby reducing the distance between the chips, and finally reducing the area of the terminal product, thereby facilitating miniaturization of the terminal product;
  • a metal seed layer is sputter deposited in the opening of the insulating layer, and a metal conductor layer is formed by electroplating the metal seed layer and an interconnection circuit between the chips, and the inter-metal interconnection resistance is smaller than that of the prior art. Thereby reducing the energy loss and improving the efficiency of the semiconductor device.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

一种芯片封装器件及封装方法，所述芯片封装方法包括：提供一承载板（201），所述承载板（201）上设置有第一粘接层（202）；将多个芯片（100）间隔放置于所述第一粘接层（202）上；采用塑封工艺在所述承载板（201）上形成塑封层（203），所述塑封层（203）填满多个所述芯片（100）之间的间隙，形成塑封芯片（200）；移除所述承载板（201）与第一粘接层（202）形成塑封芯片（300）；在所述塑封芯片（300）上形成绝缘层（301），在所述绝缘层（301）上形成开孔，在所述开孔内形成金属导体层（302）以及芯片之间的互连电路（303）；对所述塑封芯片（300）进行切割，形成多个模块（400）；采用所述的芯片封装方法，能够减小芯片之间的距离，最终减小终端产品的面积，有利于实现终端产品的小型化。

Description

芯片封装器件及封装方法 技术领域
本发明涉及芯片封装的技术领域，特别涉及一种芯片封装器件及封装方法。
背景技术
绝缘栅双极晶体管(Insulated Gate Bipolar Transistor,IGBT)是由BJT(双极型三极管)和MOS(绝缘栅型场效应管)组成的复合全控型电压驱动式功率半导体器件，兼具MOS的高输入阻抗和GTR(巨型晶体管)的低导通压降两方面的优点。GTR饱和压降低，载流密度大，但驱动电流较大，MOS驱动功率很小，开关速度快，但导通压降大，载流密度小。IGBT综合了以上两种器件的优点，驱动功率小而饱和压降低，非常适合应用于直流电压为600v及以上的变流系统如交流电机、变频器、开关电源、照明电路、牵引传动等领域。
图1为现有技术中IGBT模块的封装结构示意图，如图1所示，所述封装结构包括：铝碳化硅散热板1，依次位于所述铝碳化硅散热板1之上的第一焊料层2、第一铜层3、陶瓷层4以及第二铜层5，位于所述第二铜层5上彼此隔开的第二焊料层6与第三铜层7，以及位于所述第二焊料层6上的彼此隔开的二极管芯片8与IGBT 9。所述二极管芯片8、IGBT 9以及第三铜层7通过导线10相连接。
所述导线10一般为金线、铝线或铜线，线连接的缺点是导线长，电阻大，电能转换成不必要的热能。功率器件的金属线为保证低电阻率，和加强散热，必须使用粗线，在0.1毫米以上，普通的只有0.25毫米。这样就使芯片与衬底的互联距离很大，芯片之间的互联也要比普通芯片大，使得终端产品面积比较大。
因此，提供一种缩小芯片之间距离的封装，减小终端产品面积是本领域技术人员亟需解决的一个技术问题。
发明内容
本发明的目的在于提供一种芯片封装器件及封装方法，减小芯片之间的距离，最终减小终端产品的面积。
本发明的技术方案是一种芯片封装方法，包括以下步骤：
步骤S01：提供一承载板，所述承载板上设置有第一粘接层；
步骤S02：将多个芯片间隔放置于所述第一粘接层上；
步骤S03：采用塑封工艺在所述承载板上形成塑封层，所述塑封层填满多个所述芯片之间的间隙，形成塑封芯片；
步骤S04：移除所述承载板与第一粘接层；
步骤S05：在所述塑封芯片上形成绝缘层，在所述绝缘层上形成开孔，在所述开孔内形成金属导体层以及芯片之间的互连电路；
步骤S06：对所述塑封芯片进行切割，形成多个模块。
进一步的，还包括：
步骤S07：提供一基板，所述基板上形成有多个金属垫结构，所述金属垫结构与所述模块内的芯片一一对应；
步骤S08：在所述金属垫结构上形成第二粘接层；
步骤S09：将所述模块远离所述绝缘层的一侧粘接至所述基板。
进一步的，所述第二粘接层的材料为焊锡；在步骤S09中，将所述模块用贴片机放置于所述基板上，通过回流炉，使所述模块远离所述绝缘层的一侧粘接至所述基板。
进一步的，所述第二粘接层的材料为烧结材料；在步骤S09中，将所述模块用贴片机放置于所述基板上，通过烧结炉，使所述模块远离所述绝 缘层的一侧粘接至所述基板。
进一步的，所述第二粘接层的材料为导电胶；在步骤S09中，将所述模块用贴片机放置于所述基板上，通过烘烤，使所述模块远离所述绝缘层的一侧粘接至所述基板。
进一步的，所述基板的材质为金属，具备导电功能或散热功能。
进一步的，所述承载板为圆形、正方形或长方形。
进一步的，在所述第一粘接层上，相邻芯片之间的距离大于等于50um。
进一步的，步骤S03中，所述塑封工艺为压力塑封工艺或注塑工艺，所述塑封层的材质为环氧树脂。
进一步的，所述塑封层的厚度等于所述芯片的厚度。
进一步的，所述塑封层的厚度小于所述芯片的厚度，在靠近所述基板的一侧所述塑封层的表面比所述芯片的表面低2um～10um。
进一步的，所述芯片的正面设置有电路，在所述芯片的背面设置有电极，所述芯片的背面放置于所述第一粘接层上。
进一步的，在步骤S05中，形成金属导体层以及芯片之间的互连电路的步骤包括：
采用溅射法在所述绝缘层上沉积金属种子层；
对所述开孔内的金属种子层进行电镀；
去除未被电镀的金属种子层。
相应的，本发明还提供一种芯片封装器件，采用上述的芯片封装方法进行封装，所述芯片封装器件包括：
基板，形成于所述基板上的多个间隔排列的第二粘接层；
多个芯片，分别位于所述第二粘结层上，所述芯片与所述第二粘结层一一对应；
位于所述基板上且包围所述芯片四周的塑封层；
位于所述塑封层以及所述芯片上的绝缘层；
位于所述绝缘层内的开孔，所述开孔延伸至所述芯片；
在所述开孔内形成的金属导体层以及芯片之间的互连电路。
与现有技术相比，本发明提供的芯片封装器件及封装方法具有以下有益效果：
1、通过将多个芯片间隔放置于设置有第一粘结层的承载板上，然后采用塑封工艺在所述承载板上形成塑封层，所述塑封层填满多个所述芯片之间的间隙，形成塑封芯片，由此减小芯片之间的距离，最终减小终端产品的面积，有利于实现终端产品的小型化；
2、本发明通过在绝缘层的开孔内溅射沉积金属种子层，并通过对金属种子层进行电镀形成金属导体层以及芯片之间的互联电路，金属间互联电阻比现有技术中的线连接的电阻小，从而降低了能量的损耗，提高了半导体器件的效率。
附图说明
图1为现有技术中IGBT模块的封装结构示意图。
图2为本发明一实施例所提供的芯片封装方法的流程图。
图3为本发明一实施例所提供的芯片的结构示意图。
图4～图12为本发明一实施例所提供的芯片封装方法的各步骤结构示意图。
具体实施方式
为使本发明的内容更加清楚易懂，以下结合说明书附图，对本发明的内容做进一步说明。当然本发明并不局限于该具体实施例，本领域的技术人员所熟知的一般替换也涵盖在本发明的保护范围内。
其次，本发明利用示意图进行了详细的表述，在详述本发明实例时，为了便于说明，示意图不依照一般比例局部放大，不应对此作为本发明的限定。
本发明本发明提供一种芯片封装方法及由该封装方法形成的芯片封装器件，所述芯片封装方法包括以下步骤：提供一承载板，所述承载板上设置有第一粘接层；将多个芯片间隔放置于所述第一粘接层上；采用塑封工艺在所述承载板上形成塑封层，所述塑封层填满多个所述芯片之间的间隙，形成塑封芯片；移除所述承载板与第一粘接层；在所述塑封芯片上形成绝缘层，在所述绝缘层上形成开孔，在所述开孔内沉积金属形成金属导体层以及芯片之间的互连电路；对所述封装芯片进行切割，形成多个模块。
本发明通过将多个芯片间隔放置于设置有第一粘结层的承载板上，然后采用塑封工艺在所述承载板上形成塑封层，所述塑封层填满多个所述芯片之间的间隙，形成塑封芯片，由此减小芯片之间的距离，最终减小终端产品的面积，有利于实现终端产品的小型化。
图2为本发明一实施例所提供的芯片封装方法的流程图，如图2所示，本发明提出一种芯片封装方法，包括以下步骤：
步骤S01：提供一承载板，所述承载板上设置有第一粘接层；
步骤S02：将多个芯片间隔放置于所述第一粘接层上；
步骤S03：采用塑封工艺在所述承载板上形成塑封层，所述塑封层填满多个所述芯片之间的间隙，形成塑封芯片；
步骤S04：移除所述承载板与第一粘接层；
步骤S05：在所述塑封芯片上形成绝缘层，在所述绝缘层上形成开孔，在所述开孔内沉积金属形成金属导体层以及芯片之间的互连电路；
步骤S06：对所述封装芯片进行切割，形成多个模块；
步骤S07：提供一基板，所述基板上形成有多个金属垫结构，所述金属 垫结构与所述模块内的芯片一一对应；
步骤S08：在所述金属垫结构上形成第二粘接层；
步骤S09：将所述模块远离所述绝缘层的一侧粘接至所述基板。
图4～图12为本发明一实施例所提供的芯片封装方法的各步骤结构示意图，请参考图2所示，并结合图4～图12，详细说明本发明提出的芯片封装方法：
在步骤S01中，提供一承载板201，所述承载板201上设置有第一粘接层202，如图4所示。
在本实施例中，所述承载板201为圆形、正方形或长方形。所述第一粘结层202具有在高温或光照条件下其粘结性降低的性能。
在步骤S02中，将多个芯片100间隔放置于所述第一粘接层202上，如图5所示。相邻所述芯片100之间的距离大于等于50um，例如相邻所述芯片100之间的距离为50um、60um或70um。
所述芯片的正面设置有电路，所述芯片的背面设置有电极，所述芯片的背面放置于所述第一粘接层上，具体的，图3为本发明一实施例所提供的芯片的结构示意图，如图3所示，所述芯片100包括半导体沉底150，在所述半导体衬底150正面设置有绝缘层140，在所述绝缘层140内形成有凹槽，在所述凹槽内填充有金属，形成所述芯片100的栅极120与发射极130，作为芯片的输入端与输出端，在所述半导体衬底150的背面设置有集电极110。所述半导体衬底150的背面放置于所述第一粘接层上。可以理解的是，所述半导体衬底150的正面与背面是相对而言的，在本实施例中，以图5为例，以远离所述第一粘接层201的一面为半导体衬底150的正面，以靠近所述第一粘接层201的一面为半导体衬底150的背面。
在步骤S03中，采用塑封工艺在所述承载板201上形成塑封层203，所述塑封层203填满多个所述芯片100之间的间隙，形成塑封芯片200，如图 6所示。
所述塑封工艺为压力塑封工艺或注塑工艺，所述塑封层203的材质为环氧树脂。使用环氧树脂，利用压力塑封工艺或注塑工艺将环氧树脂与芯片铸成一体，形成塑封芯片。所述环氧树脂形成塑封层203，所述塑封层203填满多个所述芯片之间的间隙，即所述塑封层203包围所述芯片100的四周，所述塑封层203与所述芯片100的上表面平齐。塑封芯片可以根据承载板101的形状，设计成圆形、正方形或长方形。所述塑封层203的厚度等于所述芯片100的厚度，或者，所述塑封层203的厚度也可以小于所述芯片100的厚度，例如，所述塑封层203的厚度比所述芯片100的厚度小2um～10um，使得所述芯片100背面的集电极110比所述塑封层203高出2um～10um。所述环氧树脂包含低热膨胀系数高分子材料，所述低热膨胀系数高分子材料的体积浓度为7ppm～9ppm，例如所述低热膨胀系数高分子材料的体积浓度为7ppm、8ppm或9ppm。所述低热膨胀系数高分子材料是指热膨胀系数小于4×10/℃的高分子材料。
在步骤S04中，移除所述承载板201与第一粘接层202，形成塑封芯片300，如图7所示。
对所述塑封芯片200进行加热，使所述第一粘结层202的粘结性降低，然后使用真空吸盘将所述塑封芯片200中的所述承载板201以及第一粘结层202移除，形成塑封芯片300。
在步骤S05中，在所述塑封芯片300上形成绝缘层301，在所述绝缘层301上形成开孔，在所述开孔内沉积金属形成金属导体层302以及芯片之间的互连电路303，如图8所示。
具体的，首先，在所述塑封芯片300上涂布第一层绝缘层301，绝缘层301中的绝缘材料为集成电路封装常用的紫外光照相制版材料。经过曝光，显影工艺，在对应于所述芯片100的栅极与发射极的位置处形成开孔，所 述开孔延伸至所述芯片100的上表面。
然后，使用溅射法，在所述第一层绝缘层301上沉积金属种子层，厚度为0.2um～0.5um，目的是电镀金属，形成导线。
然后，在所述金属种子层上涂布光刻胶，进行曝光与显影，暴露出开孔的位置，对暴露出的所述金属种子层进行电镀，然后去除光刻胶，用酸刻蚀去除未被电镀的金属种子层，形成金属导体层302以及芯片之间的互连电路303。
还包括，在上述形成的器件表面涂布第二层绝缘层304，在特定位置开孔，形成绝缘层开孔305，作为与外部电路的接口。
在步骤S06中，对所述塑封芯片进行切割，形成多个模块400，如图9所示。所述模块400可以为单一芯片，也可以是多芯片的集成。在本实施例以两个芯片为例进行说明。
在步骤S07中，提供一基板500，所述基板500上形成有多个金属垫结构，所述金属垫结构与所述模块内的芯片一一对应，如图10所示。所述基板500的材质为金属，具备导电功能或散热功能。所述金属垫结构(图中未示出)在所述基板500上的位置与所述模块内的芯片一一对应。也就是说，如果模块内包含两个芯片，则所述基板上也设置有两个金属垫结构，所述金属垫结构之间的距离与所述芯片之间的距离相等。
在步骤S08中，在所述金属垫结构上形成第二粘接层501，如图11所示。所述第二粘接层501的材料为焊锡，或者低温烧结材料，或者导电胶，或本领域技术人员已知的其他材料。
在步骤S09中，将所述模块400远离所述绝缘层的一侧粘接至所述基板500，形成如图12所示的结构。首先，将所述模块400用贴片机放置于所述基板500上，所述模块400上远离所述绝缘层的一侧放置于所述基板500上设置有第二粘结层501的一侧上。然后，通过回流炉(所述第二粘接 层501的材料为焊锡)或者烧结炉(所述第二粘接层501的材料为烧结材料)或者烘烤(所述第二粘接层501的材料为导电胶)，使所述模块400粘结于所述基板500上，形成芯片封装器件。
本发明通过将多个芯片100间隔放置于设置有第一粘结层202的承载板201上，然后采用塑封工艺在所述承载板201上形成塑封层203，所述塑封层203填满多个所述芯片100之间的间隙，形成塑封芯片200，从而能够减小芯片100之间的距离，最终减小终端产品的面积，有利于实现终端产品的小型化。并且，本发明通过在绝缘层的开孔内溅射沉积金属种子层，并通过对金属种子层进行电镀形成金属导体层302以及芯片之间的互联电路303，金属间互联电阻比现有技术中的线连接的电阻小，从而降低了能量的损耗，提高了半导体器件的效率。
相应的，本发明还提供一种芯片封装器件，采用上述的芯片封装方法进行封装。请参考图12所示，所述芯片封装器件包括：基板500，形成于所述基板500上的多个间隔排列的第二粘接层501；多个芯片100，分别位于所述第二粘结层501上，所述芯片100与所述第二粘结层501一一对应；位于所述基板500及所述第二粘接层501上且包围所述芯片100四周的塑封层203；位于所述塑封层203以及所述芯片100上的绝缘层301；位于所述绝缘层301内的开孔，所述开孔延伸至所述芯片100；在所述开孔内形成的金属导体层302以及芯片之间的互连电路303。还包括：位于所述绝缘层301及互联电路303之上的第二层绝缘层304，以及绝缘层开孔305。
本发明提供的芯片封装器件，芯片100之间的距离最小可以达到50um，与现有技术中的500um相比，大大减小了芯片之间的距离，从而最终减小了终端产品的面积，有利于实现终端产品的小型化。并且，在本发明提供的芯片封装器件中，采用金属互联代替了现有技术中的线连接，在很大程度上降低的连线的电阻，金属间互联电阻只有线连接电阻的30％～50％，从 而降低了能量的损耗，提高了半导体器件的效率。
综上所述，本发明提供的芯片封装器件及封装方法，通过将多个芯片间隔放置于设置有第一粘结层的承载板上，然后采用塑封工艺在所述承载板上形成塑封层，所述塑封层填满多个所述芯片之间的间隙，形成塑封芯片，由此减小芯片之间的距离，最终减小终端产品的面积，有利于实现终端产品的小型化；本发明通过在绝缘层的开孔内溅射沉积金属种子层，并通过对金属种子层进行电镀形成金属导体层以及芯片之间的互联电路，金属间互联电阻比现有技术中的线连接的电阻小，从而降低了能量的损耗，提高了半导体器件的效率。
上述描述仅是对本发明较佳实施例的描述，并非对本发明范围的任何限定，本发明领域的普通技术人员根据上述揭示内容做的任何变更、修饰，均属于权利要求书的保护范围。

Claims (14)

  1. 一种芯片封装方法，其特征在于，包括以下步骤：
    步骤S01：提供一承载板，所述承载板上设置有第一粘接层；
    步骤S02：将多个芯片间隔放置于所述第一粘接层上；
    步骤S03：采用塑封工艺在所述承载板上形成塑封层，所述塑封层填满多个所述芯片之间的间隙，形成塑封芯片；
    步骤S04：移除所述承载板与第一粘接层；
    步骤S05：在所述塑封芯片上形成绝缘层，在所述绝缘层上形成开孔，在所述开孔内形成金属导体层以及芯片之间的互连电路；
    步骤S06：对所述塑封芯片进行切割，形成多个模块。
  2. 如权利要求1所述的芯片封装方法，其特征在于，还包括：
    步骤S07：提供一基板，所述基板上形成有多个金属垫结构，所述金属垫结构与所述模块内的芯片一一对应；
    步骤S08：在所述金属垫结构上形成第二粘接层；
    步骤S09：将所述模块远离所述绝缘层的一侧粘接至所述基板。
  3. 如权利要求2所述的芯片封装方法，其特征在于，所述第二粘接层的材料为焊锡；在步骤S09中，将所述模块用贴片机放置于所述基板上，通过回流炉，使所述模块远离所述绝缘层的一侧粘接至所述基板。
  4. 如权利要求2所述的芯片封装方法，其特征在于，所述第二粘接层的材料为烧结材料；在步骤S09中，将所述模块用贴片机放置于所述基板上，通过烧结炉，使所述模块远离所述绝缘层的一侧粘接至所述基板。
  5. 如权利要求2所述的芯片封装方法，其特征在于，所述第二粘接层的材料为导电胶；在步骤S09中，将所述模块用贴片机放置于所述基板上，通过烘烤，使所述模块远离所述绝缘层的一侧粘接至所述基板。
  6. 如权利要求2所述的芯片封装方法，其特征在于，所述基板的材质为金属，具备导电功能或散热功能。
  7. 如权利要求1所述的芯片封装方法，其特征在于，所述承载板为圆形、正方形或长方形。
  8. 如权利要求1所述的芯片封装方法，其特征在于，在所述第一粘接层上，相邻芯片之间的距离大于等于50um。
  9. 如权利要求1所述的芯片封装方法，其特征在于，步骤S03中，所述塑封工艺为压力塑封工艺或注塑工艺，所述塑封层的材质为环氧树脂。
  10. 如权利要求8所述的芯片封装方法，其特征在于，所述塑封层的厚度等于所述芯片的厚度。
  11. 如权利要求8所述的芯片封装方法，其特征在于，所述塑封层的厚度小于所述芯片的厚度，在靠近所述基板的一侧所述塑封层表面比所述芯片的表面低2um～10um。
  12. 如权利要求1所述的芯片封装方法，其特征在于，所述芯片的正面设置有电路，在所述芯片的背面设置有电极，所述芯片的背面放置于所述第一粘接层上。
  13. 如权利要求12所述的芯片封装方法，其特征在于，在步骤S05中，形成金属导体层以及芯片之间的互连电路的步骤包括：
    采用溅射法在所述绝缘层上沉积金属种子层；
    对所述开孔内的金属种子层进行电镀；
    去除未被电镀的金属种子层。
  14. 一种芯片封装器件，其特征在于，采用如权利要求1～13中任一项所述的芯片封装方法进行封装，所述芯片封装器件包括：
    基板，形成于所述基板上的多个间隔排列的第二粘接层；
    多个芯片，分别位于所述第二粘结层上，所述芯片与所述第二粘结层 一一对应；
    位于所述基板上且包围所述芯片四周的塑封层；
    位于所述塑封层以及所述芯片上的绝缘层；
    位于所述绝缘层内的开孔，所述开孔延伸至所述芯片；
    在所述开孔内形成的金属导体层以及芯片之间的互连电路。
PCT/CN2017/077439 2017-01-25 2017-03-21 芯片封装器件及封装方法 WO2018137280A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/480,622 US10937767B2 (en) 2017-01-25 2017-03-21 Chip packaging method and device with packaged chips

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710061017.1A CN108346587A (zh) 2017-01-25 2017-01-25 芯片封装器件及封装方法
CN201710061017.1 2017-01-25

Publications (1)

Publication Number Publication Date
WO2018137280A1 true WO2018137280A1 (zh) 2018-08-02

Family

ID=62962440

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/077439 WO2018137280A1 (zh) 2017-01-25 2017-03-21 芯片封装器件及封装方法

Country Status (3)

Country Link
US (1) US10937767B2 (zh)
CN (1) CN108346587A (zh)
WO (1) WO2018137280A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109524333A (zh) * 2018-12-27 2019-03-26 西安中车永电电气有限公司 一种高压igbt模块封装用释放液注入工装

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113036425B (zh) * 2021-03-01 2023-05-30 青岛歌尔智能传感器有限公司 集成封装及移动终端
CN113611616B (zh) * 2021-07-29 2023-12-26 矽磐微电子(重庆)有限公司 半导体封装方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102956589A (zh) * 2011-08-19 2013-03-06 欣兴电子股份有限公司 半导体封装结构及其制法
CN103745958A (zh) * 2013-12-05 2014-04-23 南通富士通微电子股份有限公司 封装结构
CN103915355A (zh) * 2013-12-05 2014-07-09 南通富士通微电子股份有限公司 封装结构的形成方法
CN105244341A (zh) * 2015-09-01 2016-01-13 华进半导体封装先导技术研发中心有限公司 半导体器件的fowlp封装结构及制作方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1213754A3 (en) * 1994-03-18 2005-05-25 Hitachi Chemical Co., Ltd. Fabrication process of semiconductor package and semiconductor package
KR100343462B1 (ko) * 1999-12-08 2002-07-11 박종섭 열방출이 용이한 칩 사이즈 패키지
CN201623107U (zh) * 2010-01-30 2010-11-03 江苏长电科技股份有限公司 印刷线路板芯片倒装散热块外接散热板封装结构
CN103745936B (zh) * 2014-02-08 2016-08-17 华进半导体封装先导技术研发中心有限公司 扇出型方片级封装的制作方法
CN105514071B (zh) * 2016-01-22 2019-01-25 中芯长电半导体（江阴）有限公司 一种扇出型芯片的封装方法及封装结构
US11003884B2 (en) * 2016-06-16 2021-05-11 Qualcomm Incorporated Fingerprint sensor device and methods thereof
CN206639791U (zh) * 2017-01-25 2017-11-14 新加坡有限公司 芯片封装器件

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102956589A (zh) * 2011-08-19 2013-03-06 欣兴电子股份有限公司 半导体封装结构及其制法
CN103745958A (zh) * 2013-12-05 2014-04-23 南通富士通微电子股份有限公司 封装结构
CN103915355A (zh) * 2013-12-05 2014-07-09 南通富士通微电子股份有限公司 封装结构的形成方法
CN105244341A (zh) * 2015-09-01 2016-01-13 华进半导体封装先导技术研发中心有限公司 半导体器件的fowlp封装结构及制作方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109524333A (zh) * 2018-12-27 2019-03-26 西安中车永电电气有限公司 一种高压igbt模块封装用释放液注入工装
CN109524333B (zh) * 2018-12-27 2024-03-26 西安中车永电电气有限公司 一种高压igbt模块封装用释放液注入工装

Also Published As

Publication number Publication date
US20190385986A1 (en) 2019-12-19
CN108346587A (zh) 2018-07-31
US10937767B2 (en) 2021-03-02

Similar Documents

Publication Publication Date Title
JP7254840B2 (ja) ワイヤボンドを有するパワーオーバーレイ構造体およびその製造方法
US7759163B2 (en) Semiconductor module
US8637341B2 (en) Semiconductor module
US7799614B2 (en) Method of fabricating a power electronic device
TWI485817B (zh) 微電子封裝及其散熱方法
TWI590395B (zh) 多功率晶片的功率封裝模組及功率晶片單元的製造方法
US10312194B2 (en) Stacked electronics package and method of manufacturing thereof
US9984897B2 (en) Method for manufacturing a chip arrangement including a ceramic layer
CN104425470A (zh) 半导体模块及其通过扩展嵌入技术的制造方法
US10051742B2 (en) Power module and manufacturing method thereof
US10700035B2 (en) Stacked electronics package and method of manufacturing thereof
US20130229777A1 (en) Chip arrangements and methods for forming a chip arrangement
WO2018137280A1 (zh) 芯片封装器件及封装方法
US9117786B2 (en) Chip module, an insulation material and a method for fabricating a chip module
US20180247924A1 (en) Electronics package having a multi-thickness conductor layer and method of manufacturing thereof
CN106298724B (zh) 塑封型功率模块
CN114005812A (zh) 一种扇出型封装结构及其构造方法
US7632712B2 (en) Method of fabricating a power semiconductor module
US20190148332A1 (en) Reinforcement for electrical connectors
CN106876350B (zh) 功率模块及其制造方法
CN206639791U (zh) 芯片封装器件
WO2017157486A1 (en) Semiconductor device
EP3223306A1 (en) Semiconductor package

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17893775

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 31/10/2019)

122 Ep: pct application non-entry in european phase

Ref document number: 17893775

Country of ref document: EP

Kind code of ref document: A1