CN206639791U - 芯片封装器件 - Google Patents
芯片封装器件 Download PDFInfo
- Publication number
- CN206639791U CN206639791U CN201720104099.9U CN201720104099U CN206639791U CN 206639791 U CN206639791 U CN 206639791U CN 201720104099 U CN201720104099 U CN 201720104099U CN 206639791 U CN206639791 U CN 206639791U
- Authority
- CN
- China
- Prior art keywords
- chip
- substrate
- plastic packaging
- perforate
- packaging layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004033 plastic Substances 0.000 claims abstract description 56
- 238000004806 packaging method and process Methods 0.000 claims abstract description 42
- 229910052751 metal Inorganic materials 0.000 claims abstract description 37
- 239000002184 metal Substances 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 239000000853 adhesive Substances 0.000 claims abstract description 26
- 230000001070 adhesive effect Effects 0.000 claims abstract description 26
- 230000004888 barrier function Effects 0.000 claims abstract description 25
- 239000004020 conductor Substances 0.000 claims abstract description 11
- 239000007795 chemical reaction product Substances 0.000 abstract description 13
- 238000000034 method Methods 0.000 description 17
- 239000000463 material Substances 0.000 description 14
- 239000004065 semiconductor Substances 0.000 description 11
- 230000008569 process Effects 0.000 description 8
- 239000003822 epoxy resin Substances 0.000 description 5
- 229920000647 polyepoxide Polymers 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000002861 polymer material Substances 0.000 description 4
- 238000007747 plating Methods 0.000 description 3
- 239000000047 product Substances 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000003984 copper intrauterine device Substances 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 238000005245 sintering Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 244000247747 Coptis groenlandica Species 0.000 description 1
- 235000002991 Coptis groenlandica Nutrition 0.000 description 1
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- KMWBBMXGHHLDKL-UHFFFAOYSA-N [AlH3].[Si] Chemical compound [AlH3].[Si] KMWBBMXGHHLDKL-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229920002521 macromolecule Polymers 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- VIKNJXKGJWUCNN-XGXHKTLJSA-N norethisterone Chemical compound O=C1CC[C@@H]2[C@H]3CC[C@](C)([C@](CC4)(O)C#C)[C@@H]4[C@@H]3CCC2=C1 VIKNJXKGJWUCNN-XGXHKTLJSA-N 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
- 238000004062 sedimentation Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
- H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
本实用新型提供了一种芯片封装器件,包括:基板,形成于所述基板上的多个间隔排列的第二粘接层;多个芯片,分别位于所述第二粘结层上,所述芯片与所述第二粘结层一一对应;位于所述基板上且包围所述芯片四周的塑封层;位于所述塑封层以及所述芯片上的绝缘层;位于所述绝缘层内的开孔,所述开孔延伸至所述芯片;在所述开孔内形成的金属导体层以及芯片之间的互连电路;采用本实用新型所述的芯片封装器件,能够减小芯片之间的距离,最终减小终端产品的面积,有利于实现终端产品的小型化。
Description
技术领域
本实用新型涉及芯片封装的技术领域,特别涉及一种芯片封装器件。
背景技术
绝缘栅双极晶体管(Insulated Gate Bipolar Transistor,IGBT)是由BJT(双极型三极管)和MOS(绝缘栅型场效应管)组成的复合全控型电压驱动式功率半导体器件,兼具MOS的高输入阻抗和GTR(巨型晶体管)的低导通压降两方面的优点。GTR饱和压降低,载流密度大,但驱动电流较大,MOS驱动功率很小,开关速度快,但导通压降大,载流密度小。IGBT综合了以上两种器件的优点,驱动功率小而饱和压降低,非常适合应用于直流电压为600v及以上的变流系统如交流电机、变频器、开关电源、照明电路、牵引传动等领域。
图1为现有技术中IGBT模块的封装结构示意图,如图1所示,所述封装结构包括:铝碳化硅散热板1,依次位于所述铝碳化硅散热板1之上的第一焊料层2、第一铜层3、陶瓷层4以及第二铜层5,位于所述第二铜层5上彼此隔开的第二焊料层6与第三铜层7,以及位于所述第二焊料层6上的彼此隔开的二极管芯片8与IGBT 9。所述二极管芯片8、IGBT 9以及第三铜层7通过导线10相连接。
所述导线10一般为金线、铝线或铜线,线连接的缺点是导线长,电阻大,电能转换成不必要的热能。功率器件的金属线为保证低电阻率,和加强散热,必须使用粗线,在0.1毫米以上,普通的只有0.25毫米。这样就使芯片与衬底的互联距离很大,芯片之间的互联也要比普通芯片大,使得终端产品面积比较大。
因此,提供一种缩小芯片之间距离的封装,减小终端产品面积是本领域技术人员亟需解决的一个技术问题。
实用新型内容
本实用新型的目的在于提供一种芯片封装器件,减小芯片之间的距离,最终减小终端产品的面积。
本实用新型的技术方案是一种芯片封装器件,包括:
基板,形成于所述基板上的多个间隔排列的第二粘接层;
多个芯片,分别位于所述第二粘结层上,所述芯片与所述第二粘结层一一对应;
位于所述基板上且包围所述芯片四周的塑封层;
位于所述塑封层以及所述芯片上的绝缘层;
位于所述绝缘层内的开孔,所述开孔延伸至所述芯片;
在所述开孔内形成的金属导体层以及芯片之间的互连电路。
进一步的,相邻所述芯片之间的距离大于等于50um。
进一步的,所述塑封层的厚度等于所述芯片的厚度。
进一步的,所述塑封层的厚度小于所述芯片的厚度,在靠近所述基板的一侧所述塑封层表面比所述芯片的表面低2um~10um。
进一步的,所述芯片的正面设置有电路,在所述芯片的背面设置有电极,所述芯片的正面设置于所述第二粘接层上。
与现有技术相比,本实用新型提供的芯片封装器件,在基板上设置有多个间隔排列的第二粘接层,芯片设置于所述第二粘接层上,在芯片的四周设置有塑封层,在所述塑封层以及所述芯片上设置有绝缘层,在绝缘层内设置有延伸至所述芯片的开孔,在开孔内形成有金属导体层以及芯片之间的互连电路,由此实现多个芯片之间的互连;本实用新型所提供的芯片封装器件能够减小芯片之间的距离,最终减小终端产品的面积,有利于实现终端产品的小型化。
附图说明
图1为现有技术中IGBT模块的封装结构示意图。
图2为本实用新型一实施例所提供的芯片封装方法的流程图。
图3为本实用新型一实施例所提供的芯片的结构示意图。
图4~图12为本实用新型一实施例所提供的芯片封装方法的各步骤结构示意图。
具体实施方式
为使本实用新型的内容更加清楚易懂,以下结合说明书附图,对本实用新型的内容做进一步说明。当然本实用新型并不局限于该具体实施例,本领域的技术人员所熟知的一般替换也涵盖在本实用新型的保护范围内。
其次,本实用新型利用示意图进行了详细的表述,在详述本实用新型实例时,为了便于说明,示意图不依照一般比例局部放大,不应对此作为本实用新型的限定。
本实用新型提供的芯片封装器件,在基板上设置有多个间隔排列的第二粘接层,芯片设置于所述第二粘接层上,在芯片的四周设置有塑封层,在所述塑封层以及所述芯片上设置有绝缘层,在绝缘层内设置有延伸至所述芯片的开孔,在开孔内形成有金属导体层以及芯片之间的互连电路,由此实现多个芯片之间的互连;本实用新型所提供的芯片封装器件能够减小芯片之间的距离,最终减小终端产品的面积,有利于实现终端产品的小型化。
图2为本实用新型一实施例所提供的芯片封装方法的流程图,如图2所示,本实用新型提出一种芯片封装方法,包括以下步骤:
步骤S01:提供一承载板,所述承载板上设置有第一粘接层;
步骤S02:将多个芯片间隔放置于所述第一粘接层上;
步骤S03:采用塑封工艺在所述承载板上形成塑封层,所述塑封层填满多个所述芯片之间的间隙,形成塑封芯片;
步骤S04:移除所述承载板与第一粘接层;
步骤S05:在所述塑封芯片上形成绝缘层,在所述绝缘层上形成开孔,在所述开孔内沉积金属形成金属导体层以及芯片之间的互连电路;
步骤S06:对所述封装芯片进行切割,形成多个模块;
步骤S07:提供一基板,所述基板上形成有多个金属垫结构,所述金属垫结构与所述模块内的芯片一一对应;
步骤S08:在所述金属垫结构上形成第二粘接层;
步骤S09:将所述模块远离所述绝缘层的一侧粘接至所述基板。
图4~图12为本实用新型一实施例所提供的芯片封装方法的各步骤结构示意图,请参考图2所示,并结合图4~图12,详细说明本实用新型提出的芯片封装方法:
在步骤S01中,提供一承载板201,所述承载板201上设置有第一粘接层202,如图4所示。
在本实施例中,所述承载板201为圆形、正方形或长方形。所述第一粘结层202具有在高温或光照条件下其粘结性降低的性能。
在步骤S02中,将多个芯片100间隔放置于所述第一粘接层202上,如图5所示。相邻所述芯片100之间的距离大于等于50um,例如相邻所述芯片100之间的距离为50um、60um或70um。
所述芯片的正面设置有电路,所述芯片的背面设置有电极,所述芯片的背面放置于所述第一粘接层上,具体的,图3为本实用新型一实施例所提供的芯片的结构示意图,如图3所示,所述芯片100包括半导体沉底150,在所述半导体衬底150正面设置有绝缘层140,在所述绝缘层140内形成有凹槽,在所述凹槽内填充有金属,形成所述芯片100的栅极120与发射极130,作为芯片的输入端与输出端,在所述半导体衬底150的背面设置有集电极110。所述半导体衬底150的背面放置于所述第一粘接层上。可以理解的是,所述半导体衬底150的正面与背面是相对而言的,在本实施例中,以图5为例,以远离所述第一粘接层201的一面为半导体衬底150的正面,以靠近所述第一粘接层201的一面为半导体衬底150的背面。
在步骤S03中,采用塑封工艺在所述承载板201上形成塑封层203,所述塑封层203填满多个所述芯片100之间的间隙,形成塑封芯片200,如图6所示。
所述塑封工艺为压力塑封工艺或注塑工艺,所述塑封层203的材质为环氧树脂。使用环氧树脂,利用压力塑封工艺或注塑工艺将环氧树脂与芯片铸成一体,形成塑封芯片。所述环氧树脂形成塑封层203,所述塑封层203填满多个所述芯片之间的间隙,即所述塑封层203包围所述芯片100的四周,所述塑封层203与所述芯片100的上表面平齐。塑封芯片可以根据承载板101的形状,设计成圆形、正方形或长方形。所述塑封层203的厚度等于所述芯片100的厚度,或者,所述塑封层203的厚度也可以小于所述芯片100的厚度,例如,所述塑封层203的厚度比所述芯片100的厚度小2um~10um,使得所述芯片100背面的集电极110比所述塑封层203高出2um~10um。所述环氧树脂包含低热膨胀系数高分子材料,所述低热膨胀系数高分子材料的体积浓度为7ppm~9ppm,例如所述低热膨胀系数高分子材料的体积浓度为7ppm、8ppm或9ppm。所述低热膨胀系数高分子材料是指热膨胀系数小于4×10/℃的高分子材料。
在步骤S04中,移除所述承载板201与第一粘接层202,形成塑封芯片300,如图7所示。
对所述塑封芯片200进行加热,使所述第一粘结层202的粘结性降低,然后使用真空吸盘将所述塑封芯片200中的所述承载板201以及第一粘结层202移除,形成塑封芯片300。
在步骤S05中,在所述塑封芯片300上形成绝缘层301,在所述绝缘层301上形成开孔,在所述开孔内沉积金属形成金属导体层302以及芯片之间的互连电路303,如图8所示。
具体的,首先,在所述塑封芯片300上涂布第一层绝缘层301,绝缘层301中的绝缘材料为集成电路封装常用的紫外光照相制版材料。经过曝光,显影工艺,在对应于所述芯片100的栅极与发射极的位置处形成开孔,所述开孔延伸至所述芯片100的上表面。
然后,使用溅射法,在所述第一层绝缘层301上沉积金属种子层,厚度为0.2um~0.5um,目的是电镀金属,形成导线。
然后,在所述金属种子层上涂布光刻胶,进行曝光与显影,暴露出开孔的位置,对暴露出的所述金属种子层进行电镀,然后去除光刻胶,用酸刻蚀去除未被电镀的金属种子层,形成金属导体层302以及芯片之间的互连电路303。
还包括,在上述形成的器件表面涂布第二层绝缘层304,在特定位置开孔,形成绝缘层开孔305,作为与外部电路的接口。
在步骤S06中,对所述塑封芯片进行切割,形成多个模块400,如图9所示。所述模块400可以为单一芯片,也可以是多芯片的集成。在本实施例以两个芯片为例进行说明。
在步骤S07中,提供一基板500,所述基板500上形成有多个金属垫结构,所述金属垫结构与所述模块内的芯片一一对应,如图10所示。所述基板500的材质为金属,具备导电功能或散热功能。所述金属垫结构(图中未示出)在所述基板500上的位置与所述模块内的芯片一一对应。也就是说,如果模块内包含两个芯片,则所述基板上也设置有两个金属垫结构,所述金属垫结构之间的距离与所述芯片之间的距离相等。
在步骤S08中,在所述金属垫结构上形成第二粘接层501,如图11所示。所述第二粘接层501的材料为焊锡,或者低温烧结材料,或者导电胶,或本领域技术人员已知的其他材料。
在步骤S09中,将所述模块400远离所述绝缘层的一侧粘接至所述基板500,形成如图12所示的结构。首先,将所述模块400用贴片机放置于所述基板500上,所述模块400上远离所述绝缘层的一侧放置于所述基板500上设置有第二粘结层501的一侧上。然后,通过回流炉(所述第二粘接层501的材料为焊锡)或者烧结炉(所述第二粘接层501的材料为烧结材料)或者烘烤(所述第二粘接层501的材料为导电胶),使所述模块400粘结于所述基板500上,形成芯片封装器件。
本实用新型通过将多个芯片100间隔放置于设置有第一粘结层202的承载板201上,然后采用塑封工艺在所述承载板201上形成塑封层203,所述塑封层203填满多个所述芯片100之间的间隙,形成塑封芯片200,从而能够减小芯片100之间的距离,最终减小终端产品的面积,有利于实现终端产品的小型化。并且,本实用新型通过在绝缘层的开孔内溅射沉积金属种子层,并通过对金属种子层进行电镀形成金属导体层302以及芯片之间的互联电路303,金属间互联电阻比现有技术中的线连接的电阻小,从而降低了能量的损耗,提高了半导体器件的效率。
相应的,本实用新型还提供一种芯片封装器件,采用上述的芯片封装方法进行封装。请参考图12所示,所述芯片封装器件包括:基板500,形成于所述基板500上的多个间隔排列的第二粘接层501;多个芯片100,分别位于所述第二粘结层501上,所述芯片100与所述第二粘结层501一一对应;位于所述基板500及所述第二粘接层501上且包围所述芯片100四周的塑封层203;位于所述塑封层203以及所述芯片100上的绝缘层301;位于所述绝缘层301内的开孔,所述开孔延伸至所述芯片100;在所述开孔内形成的金属导体层302以及芯片之间的互连电路303。还包括:位于所述绝缘层301及互联电路303之上的第二层绝缘层304,以及绝缘层开孔305。
本实用新型提供的芯片封装器件,芯片100之间的距离最小可以达到50um,与现有技术中的500um相比,大大减小了芯片之间的距离,从而最终减小了终端产品的面积,有利于实现终端产品的小型化。并且,在本实用新型提供的芯片封装器件中,采用金属互联代替了现有技术中的线连接,在很大程度上降低的连线的电阻,金属间互联电阻只有线连接电阻的30%~50%,从而降低了能量的损耗,提高了半导体器件的效率。
综上所述,本实用新型提供的芯片封装器件,通过将多个芯片间隔放置于设置有第一粘结层的承载板上,然后采用塑封工艺在所述承载板上形成塑封层,所述塑封层填满多个所述芯片之间的间隙,形成塑封芯片,由此减小芯片之间的距离,最终减小终端产品的面积,有利于实现终端产品的小型化;本实用新型通过在绝缘层的开孔内溅射沉积金属种子层,并通过对金属种子层进行电镀形成金属导体层以及芯片之间的互联电路,金属间互联电阻比现有技术中的线连接的电阻小,从而降低了能量的损耗,提高了半导体器件的效率。
上述描述仅是对本实用新型较佳实施例的描述,并非对本实用新型范围的任何限定,本实用新型领域的普通技术人员根据上述揭示内容做的任何变更、修饰,均属于权利要求书的保护范围。
Claims (5)
1.一种芯片封装器件,其特征在于,包括:
基板,形成于所述基板上的多个间隔排列的第二粘接层;
多个芯片,分别位于所述第二粘结层上,所述芯片与所述第二粘结层一一对应;
位于所述基板上且包围所述芯片四周的塑封层;
位于所述塑封层以及所述芯片上的绝缘层;
位于所述绝缘层内的开孔,所述开孔延伸至所述芯片;
在所述开孔内形成的金属导体层以及芯片之间的互连电路。
2.如权利要求1所述的芯片封装器件,其特征在于,相邻所述芯片之间的距离大于等于50um。
3.如权利要求1所述的芯片封装器件,其特征在于,所述塑封层的厚度等于所述芯片的厚度。
4.如权利要求1所述的芯片封装器件,其特征在于,所述塑封层的厚度小于所述芯片的厚度,在靠近所述基板的一侧所述塑封层表面比所述芯片的表面低2um~10um。
5.如权利要求1所述的芯片封装器件,其特征在于,所述芯片的正面设置有电路,在所述芯片的背面设置有电极,所述芯片的正面设置于所述第二粘接层上。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201720104099.9U CN206639791U (zh) | 2017-01-25 | 2017-01-25 | 芯片封装器件 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201720104099.9U CN206639791U (zh) | 2017-01-25 | 2017-01-25 | 芯片封装器件 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN206639791U true CN206639791U (zh) | 2017-11-14 |
Family
ID=60250944
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201720104099.9U Active CN206639791U (zh) | 2017-01-25 | 2017-01-25 | 芯片封装器件 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN206639791U (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108346587A (zh) * | 2017-01-25 | 2018-07-31 | 新加坡有限公司 | 芯片封装器件及封装方法 |
-
2017
- 2017-01-25 CN CN201720104099.9U patent/CN206639791U/zh active Active
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108346587A (zh) * | 2017-01-25 | 2018-07-31 | 新加坡有限公司 | 芯片封装器件及封装方法 |
US10937767B2 (en) | 2017-01-25 | 2021-03-02 | Inno-Pach Technology Pte Ltd | Chip packaging method and device with packaged chips |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CA2762470C (en) | Method for fabricating a semiconductor device package | |
KR101204187B1 (ko) | 소성 접합을 이용한 파워 모듈 및 그 제조 방법 | |
US20220375833A1 (en) | Substrate structures and methods of manufacture | |
CN108109986A (zh) | 一种功率半导体集成式封装用陶瓷模块及其制备方法 | |
CN108133915A (zh) | 功率器件内置且双面散热的功率模组及其制备方法 | |
CN106486458B (zh) | 多功率芯片的功率封装模块及功率芯片单元的制造方法 | |
US20130062743A1 (en) | Power module package and method for manufacturing the same | |
CN1702880A (zh) | 半导体发光二极管(led)通孔倒扣焊芯片及生产工艺 | |
US9117786B2 (en) | Chip module, an insulation material and a method for fabricating a chip module | |
CN107393882A (zh) | 基于三层dbc基板的碳化硅器件封装结构及制造方法 | |
CN202736904U (zh) | 一种覆铜硅基板 | |
CN106298724B (zh) | 塑封型功率模块 | |
CN108346587A (zh) | 芯片封装器件及封装方法 | |
CN206639791U (zh) | 芯片封装器件 | |
CN207165564U (zh) | 一种双面散热高可靠功率模块 | |
CN208240668U (zh) | 一种功率半导体集成式封装用陶瓷模块 | |
TW201019500A (en) | A ceramic packaging substrate for the high power LED | |
KR20200142951A (ko) | 반도체 패키지 | |
CN115312505A (zh) | 一种功率器件的无引线封装结构及封装方法 | |
TW201205882A (en) | Manufacturing method for LED light emitting device | |
KR101074550B1 (ko) | 파워 모듈 및 그의 제조 방법 | |
US11887961B2 (en) | Semiconductor device, semiconductor arrangement and method for producing the same | |
CN112310029A (zh) | 衬板和基体集成的功率半导体器件及其制造方法 | |
CN219998213U (zh) | 功率半导体模块 | |
CN220796724U (zh) | 一种双面半桥功率模块 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
GR01 | Patent grant | ||
GR01 | Patent grant | ||
TR01 | Transfer of patent right |
Effective date of registration: 20231120 Address after: 10th 65th Street, Hongmao Bridge, Singapore 04-20 Patentee after: Sunlight Technology Singapore Ltd. Address before: Singapore woodlands Street 11, No. 11, 10 floor, No. 8 Patentee before: INNO-PACH TECHNOLOGY Pte. Ltd. |
|
TR01 | Transfer of patent right |