CN115312505A - 一种功率器件的无引线封装结构及封装方法 - Google Patents

一种功率器件的无引线封装结构及封装方法 Download PDF

Info

Publication number
CN115312505A
CN115312505A CN202210847452.8A CN202210847452A CN115312505A CN 115312505 A CN115312505 A CN 115312505A CN 202210847452 A CN202210847452 A CN 202210847452A CN 115312505 A CN115312505 A CN 115312505A
Authority
CN
China
Prior art keywords
chip
lining plate
metal component
power device
leadless
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202210847452.8A
Other languages
English (en)
Inventor
杜隆纯
戴小平
刘洪伟
曾亮
刘亮
黄蕾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hunan Guoxin Semiconductor Technology Co ltd
Original Assignee
Hunan Guoxin Semiconductor Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hunan Guoxin Semiconductor Technology Co ltd filed Critical Hunan Guoxin Semiconductor Technology Co ltd
Priority to CN202210847452.8A priority Critical patent/CN115312505A/zh
Publication of CN115312505A publication Critical patent/CN115312505A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492—Bases or plates or solder therefor
    • H01L23/4924—Bases or plates or solder therefor characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/031—Manufacture and pre-treatment of the bonding area preform
    • H01L2224/0312—Applying permanent coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73221—Strap and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832—Applying energy for connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83447—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8384—Sintering

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Die Bonding (AREA)

Abstract

本发明公开了一种功率器件的无引线封装结构及封装方法，封装结构包括芯片、金属构件和衬板，所述芯片的背面连接在所述衬板上，所述金属构件的一端与芯片的正面之间通过烧结工艺连接，所述金属构件的另一端与衬板或外部端子之间通过烧结工艺连接。本发明采用金属构件来代替铝线键合，实现半导体芯片正面到衬板或者外部端子之间的电性连接，达到无引线连接效果，能显著提高芯片的通流能力，极大的发挥碳化硅芯片的优势。

Description

一种功率器件的无引线封装结构及封装方法
技术领域
本发明主要涉及功率半导体封装工艺技术领域，具体涉及一种功率器件的无引线封装结构及封装方法。
背景技术
随着功率器件的广泛运用以及迅速发展，其设计与制造趋于高频开关速率、高功率密度、高结温等要求发展，尤其是碳化硅材料的出现，相对于传统的硅基半导体芯片，碳化硅半导体芯片有着高结温(最高有望超过600℃)，低导通电阻，高临界击穿场强，高开关频率等性能优势。然而目前由于封装技术受限，碳化硅半导体芯片大多数仍然采用传统的硅基功率半导体器件的封装形式，传统的硅基功率器件封装形式未能完全发挥碳化硅半导体芯片的优势。
传统功率器件封装工艺中芯片正面采用的是引线互连技术，通常采用铝线键合。由于铝线电阻率高、屈服强度低等材料本身的局限性，这种连接方式成为功率器件可靠性的短板；另外芯片尤其是碳化硅芯片正面的可连接面积有限，能键合的铝线根数受限，导致芯片的电流通量受限，未能完全发挥碳化硅芯片的优势，因此需要探索一种全新的连接方式。
发明内容
本发明要解决的技术问题就在于：针对现有技术存在的问题，本发明提供一种通过金属构件代替铝键合、显著提高芯片通流能力的功率器件的无引线封装结构及封装方法。
为解决上述技术问题，本发明提出的技术方案为：
一种功率器件的无引线封装结构，包括芯片、金属构件和衬板，所述芯片的背面连接在所述衬板上，所述金属构件的一端与芯片的正面之间通过烧结工艺连接，所述金属构件的另一端与衬板或外部端子之间通过烧结工艺连接。
作为上述技术方案的进一步改进：
所述金属构件为铜或者CuMo30合金制成。
所述金属构件呈П型，其中П型金属构件底面的一端与芯片的正面连接，П型金属构件底面的另一端与衬板连接。
所述金属构件的一端与芯片的正面之间通过银烧结工艺连接，所述金属构件的另一端与衬板之间通过银烧结工艺连接。
所述金属构件的一端和另一端的连接面上设置有NiPdAu层，所述NiPdAu层上设有一层银膏。
所述芯片为碳化硅芯片。
本发明还公开了一种如上所述的功率器件的无引线封装结构的封装方法，包括步骤：
在金属构件的两个连接面镀NiPdAu层，然后在NiPdAu层上均匀预敷一层银膏；
将芯片的背面与衬板连接；
将金属构件的两个连接面分别贴在芯片正面与衬板上，在预设温度和预设压力的作用下，将芯片正面与金属构件连接面，以及衬板与金属构件连接面之间进行烧结，形成一层银烧结层，完成金属构件与芯片正面，以及金属构件与衬板之间的连接。
作为上述技术方案的进一步改进：
将芯片的背面与衬板连接的具体过程为：在加热加压的情况下将芯片背面沾银膜，贴于衬板上，然后在一定压力与温度的条件下进行烧结，实现芯片背面与衬板之间的连接。
在芯片的门极和源极信号需要外延时，通过引线将芯片的门极和源极分别与衬板连接。
所述引线为铝线。
与现有技术相比，本发明的优点在于：
本发明采用金属构件来代替铝线键合，实现半导体芯片正面到衬板或者外部端子之间的电性连接，达到无引线连接效果，能显著提高芯片的通流能力，极大的发挥碳化硅芯片的优势；另外金属构件的结构强度、电阻率和导热性等都远高于铝线，能避免产生铝线的工艺缺陷和可靠性问题。
本发明的半导体芯片与金属构件之间的连接，以及金属构件与衬板或者外部端子之间的连接均采用银烧结的方式，银烧结材料具有更高的热导率、电导率、机械强度和接近纯银的熔点，能显著提高功率器件的可靠性，是当前最具应用前景的互连技术。
附图说明
图1为本发明中的金属构件在实施例的主视结构图。
图2为本发明中金属构件的连接面在实施例的结构图。
图3为本发明中的金属构件在实施例的立体结构图。
图4为本发明的封装结构在实施例的主视结构图。
图5为本发明的封装结构在实施例的立体结构图。
图6为本发明的单面散热模块在实施例的立体结构图。
图7为本发明的芯片在实施例的主视结构图。
图例说明：1、衬板；2、芯片；201、门极；202、源极；203、漏极；3、金属构件；301、NiPdAu层；302、银膏；4、铝线。
具体实施方式
以下结合说明书附图和具体实施例对本发明作进一步描述。
如图4和图5所示，本发明实施例提供了一种功率器件的无引线封装结构，包括芯片2(如碳化硅芯片)、金属构件3和衬板1，芯片2的背面连接在衬板1上，金属构件3的一端与芯片2的正面之间通过烧结工艺(如银烧结)连接，金属构件3的另一端与衬板1或外部端子之间通过烧结工艺(如银烧结)连接。
本发明的无引线封装结构，采用金属构件3来代替铝线键合，实现半导体芯片2正面到衬板1或者外部端子之间的电性连接，达到无引线连接效果，能显著提高芯片2的通流能力，极大的发挥碳化硅芯片2的优势；另外金属构件3的结构强度、电阻率和导热性等都远高于铝线，能避免产生铝线的工艺缺陷和可靠性问题。
本发明的半导体芯片2与金属构件3之间的连接，以及金属构件3与衬板1或者外部端子之间的连接均采用银烧结的方式，由于银烧结材料具有更高的热导率、电导率、机械强度和接近纯银的熔点，能显著提高功率器件的可靠性，是当前最具应用前景的互连技术。
考虑通流能力、CTE与芯片2和衬板1的匹配原则，以及工艺过程的要求等，这种金属构件3的材料可以是纯铜或者CuMo30合金，金属构件3的连接面需提前电镀或化学镀NiPdAu层301，然后均匀预敷一层银膏302，此银膏302为可烧结材料，包含微纳米级别银颗粒；再使用烧结设备使芯片2正面与金属构件3，以及金属构件3与衬板1或者外部端子之间形成一层导电导热的银烧结层。其中金属构件3呈П型，如图1～3所示，П型金属构件3底面的两端形成连接面，分别与芯片2正面和衬板1(或外部端子)连接。
本发明实施例还公开了一种如上所述的功率器件的无引线封装结构的封装方法，包括步骤：
在金属构件3的两个连接面镀一层NiPdAu，然后均匀预敷一层银膏302；
将芯片2的背面与衬板1连接；
将金属构件3的两个连接面分别贴在芯片2正面与衬板1上，在预设温度和预设压力的作用下，将芯片2正面与金属构件3连接面，以及衬板1与金属构件3连接面之间进行烧结，形成一层银烧结层，完成金属构件3与芯片2正面，以及金属构件3与衬板1之间的连接。
本发明的封装方法操作简便且易于实现。
在一具体实施例中，将芯片2的背面与衬板1连接的具体过程为：在加热加压的情况下将芯片2背面沾银膜，贴于衬板1上，然后在一定压力与温度的条件下进行烧结，实现芯片2背面与衬板1之间的连接。
下面结合一完整的具体实施例来对本发明作进一步详细说明：
以单面散热模块为实施例进行说明，如图6所示，模块的上下桥分别有三个SiCMOS芯片2，其中采用CuMo30合金为金属构件3的材料；芯片2上的门极201、源极202和漏极203的分布如图7所示。
第一阶段实现芯片2背面漏极203与衬板1之间的连接，在加热加压的情况下使用贴片设备将六个芯片2的背面沾银膜，贴于衬板1上，然后使用烧结设备在一定压力与温度的条件下实现六个芯片2背面与衬板1之间的连接；当然，也可以通过其它方式实现芯片2背面与衬板1之间的连接；
第二阶段实现金属构件3与芯片2正面源极202，以及金属构件3与衬板1之间的连接，贴片头加热吸取金属构件3，在一定压力作用下放置在指定位置，使金属构件3的一端连接在芯片2正面源极202区域，一端连接在衬板1上，然后使用烧结设备在一定压力与温度的条件下使金属构件3的两个连接面形成一层烧结层，实现金属构件3与芯片2正面源极202，以及金属构件3与衬板1之间的连接。考虑到MOS芯片2需要将门极201与源极202信号外延，使用键合设备用铝线4将芯片2的门极201和源极202与衬板1连接。
如本公开和权利要求书中所示，除非上下文明确提示例外情形，“一”、“一个”、“一种”和/或“该”等词并非特指单数，也可包括复数。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
以上仅是本发明的优选实施方式，本发明的保护范围并不仅局限于上述实施例，凡属于本发明思路下的技术方案均属于本发明的保护范围。应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理前提下的若干改进和润饰，应视为本发明的保护范围。

Claims (10)

1.一种功率器件的无引线封装结构，其特征在于，包括芯片(2)、金属构件(3)和衬板(1)，所述芯片(2)的背面连接在所述衬板(1)上，所述金属构件(3)的一端与芯片(2)的正面之间通过烧结工艺连接，所述金属构件(3)的另一端与衬板(1)或外部端子之间通过烧结工艺连接。
2.根据权利要求1所述的功率器件的无引线封装结构，其特征在于，所述金属构件(3)为铜或者CuMo30合金制成。
3.根据权利要求1或2所述的功率器件的无引线封装结构，其特征在于，所述金属构件(3)呈П型，其中П型金属构件(3)底面的一端与芯片(2)的正面连接，П型金属构件(3)底面的另一端与衬板(1)连接。
4.根据权利要求1或2所述的功率器件的无引线封装结构，其特征在于，所述金属构件(3)的一端与芯片(2)的正面之间通过银烧结工艺连接，所述金属构件(3)的另一端与衬板(1)之间通过银烧结工艺连接。
5.根据权利要求4所述的功率器件的无引线封装结构，其特征在于，所述金属构件(3)的一端和另一端的连接面上设置有NiPdAu层(301)，所述NiPdAu层(301)上设有一层银膏(302)。
6.根据权利要求1或2所述的功率器件的无引线封装结构，其特征在于，所述芯片(2)为碳化硅芯片。
7.一种如权利要求1～6中任意一项所述的功率器件的无引线封装结构的封装方法，其特征在于，包括步骤：
在金属构件(3)的两个连接面镀NiPdAu层(301)，然后在NiPdAu层(301)上均匀预敷一层银膏(302)；
将芯片(2)的背面与衬板(1)连接；
将金属构件(3)的两个连接面分别贴在芯片(2)正面与衬板(1)上，在预设温度和预设压力的作用下，将芯片(2)正面与金属构件(3)连接面，以及衬板(1)与金属构件(3)连接面之间进行烧结，形成一层银烧结层，完成金属构件(3)与芯片(2)正面，以及金属构件(3)与衬板(1)之间的连接。
8.根据权利要求7所述的封装方法，其特征在于，将芯片(2)的背面与衬板(1)连接的具体过程为：在加热加压的情况下将芯片(2)背面沾银膜，贴于衬板(1)上，然后在一定压力与温度的条件下进行烧结，实现芯片(2)背面与衬板(1)之间的连接。
9.根据权利要求7或8所述的封装方法，其特征在于，在芯片(2)的门极(201)和源极(202)信号需要外延时，通过引线将芯片(2)的门极(201)和源极(202)分别与衬板(1)连接。
10.根据权利要求9所述的封装方法，其特征在于，所述引线为铝线(4)。
CN202210847452.8A 2022-07-19 2022-07-19 一种功率器件的无引线封装结构及封装方法 Pending CN115312505A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210847452.8A CN115312505A (zh) 2022-07-19 2022-07-19 一种功率器件的无引线封装结构及封装方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210847452.8A CN115312505A (zh) 2022-07-19 2022-07-19 一种功率器件的无引线封装结构及封装方法

Publications (1)

Publication Number Publication Date
CN115312505A true CN115312505A (zh) 2022-11-08

Family

ID=83856704

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210847452.8A Pending CN115312505A (zh) 2022-07-19 2022-07-19 一种功率器件的无引线封装结构及封装方法

Country Status (1)

Country Link
CN (1) CN115312505A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115722749A (zh) * 2022-11-16 2023-03-03 深圳市森国科科技股份有限公司 一种局部感应加热扩散焊接方法及功率模块封装方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115722749A (zh) * 2022-11-16 2023-03-03 深圳市森国科科技股份有限公司 一种局部感应加热扩散焊接方法及功率模块封装方法

Similar Documents

Publication Publication Date Title
CN110854103B (zh) 一种嵌入式双面互连功率模块封装结构和制作方法
JPH08500469A (ja) 多重チップ・モジュールを組み込んだ金属電子パッケージ
CN107887368A (zh) 采用低温烧结纳米银的双面互连硅基igbt模块的方法
CN104392942A (zh) 无压低温烧结纳米银焊膏封装大功率igbt器件的方法
CN109168320B (zh) 半导体装置
CN107393882A (zh) 基于三层dbc基板的碳化硅器件封装结构及制造方法
CN115312505A (zh) 一种功率器件的无引线封装结构及封装方法
CN104867888A (zh) 一种高散热性SiC的功率模块
WO2018137280A1 (zh) 芯片封装器件及封装方法
CN102244189A (zh) 一种陶瓷基板集成封装的led
JP2012138470A (ja) 半導体素子、半導体装置および半導体装置の製造方法
CN201435388Y (zh) 一种用于mosfet封装的引线框架
CN216849941U (zh) 一种新型可反向导通氮化镓功率器件
CN212587507U (zh) 采用多芯片堆叠结构的功率分立器件
CN216054669U (zh) 一种便于散热的氮化镓功率器件
CN112086372B (zh) 一种用于高结温功率模块芯片正面连接的封装材料结构层及其制作方法
CN217788385U (zh) 大功率器件的高散热封装结构
JP2003224234A (ja) 半導体装置
CN206639791U (zh) 芯片封装器件
TWI244181B (en) Semiconductor chip packaging structure and manufacturing method of the same
CN206789535U (zh) 一种电力电子器件的扇出型封装结构
CN102034781B (zh) 在引线框架和晶圆上印刷粘接材料的半导体封装及其制造方法
JP7418178B2 (ja) 半導体装置、及び、その製造方法
CN217881492U (zh) 一种双基岛封装器件
CN220796724U (zh) 一种双面半桥功率模块

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination