CN107887368A - 采用低温烧结纳米银的双面互连硅基igbt模块的方法 - Google Patents

采用低温烧结纳米银的双面互连硅基igbt模块的方法 Download PDF

Info

Publication number
CN107887368A
CN107887368A CN201710952767.8A CN201710952767A CN107887368A CN 107887368 A CN107887368 A CN 107887368A CN 201710952767 A CN201710952767 A CN 201710952767A CN 107887368 A CN107887368 A CN 107887368A
Authority
CN
China
Prior art keywords
silicon substrate
dbc substrates
silicon
chip
substrate igbt
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201710952767.8A
Other languages
English (en)
Inventor
梅云辉
刘�文
付善灿
陆国权
李欣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tianjin University
Original Assignee
Tianjin University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tianjin University filed Critical Tianjin University
Priority to CN201710952767.8A priority Critical patent/CN107887368A/zh
Priority to PCT/CN2017/112769 priority patent/WO2019071743A1/zh
Publication of CN107887368A publication Critical patent/CN107887368A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/325—Material
    • H01L2224/32501—Material at the bonding interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/335—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8384—Sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Die Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

本发明涉及一种采用低温烧结纳米银的双面互连硅基IGBT模块及制备方法，由功率端子、上DBC基板、下DBC基板、纳米银焊膏、硅基IGBT芯片、缓冲层、粗铝丝、焊片、硅基二极管芯片、硅凝胶和模制树脂组成；分别将硅基IGBT芯片的下表面、硅基二极管芯片的下表面以及缓冲层的下表面与下DBC基板通过纳米银连接，同时在上DBC基板也进行同样的连接，芯片和缓冲层与DBC基板的连接强度可达30MPa以上；下DBC基板的硅基IGBT芯片和硅基二极管芯片以及缓冲层的上表面分别同时与上DBC基板的缓冲层以及硅基IGBT芯片和硅基二极管芯片的上表面通过SnAgCu焊片或SnAg焊片进行连接，得到双面互连硅基IGBT模块。

Description

采用低温烧结纳米银的双面互连硅基IGBT模块的方法
技术领域
本发明涉及功率半导体封装以及功率模块领域，特别涉及一种采用低温烧结纳米银封装双面互连硅基IGBT模块。
背景技术
随着电力电子技术的发展，大功率转换系统装置(比如硅基IGBT模块)已经吸引了越来越多的关注。与此同时，出于节能和低成本的需求也迫切的要求大功率硅基IGBT模块更加轻型化和小型化。但是，这种需求给大功率硅基IGBT模块的发展带来了巨大的挑战，因为轻型化和小型化会导致模块电流密度的增加，这会导致模块内部会产生较高的热量，从而引起结温的升高。如果产生的热量不能及时排出，较高的结温会影响硅基IGBT模块整体的热机械性能和可靠性。所以，大功率硅基IGBT模块的散热是研究者和厂家不得不面对的一个问题。
除了提高的硅基IGBT模块外部散热器的散热效率外，优化大功率硅基IGBT模块内部的封装结构是解决散热问题的另外一个有效方法。传统的硅基IGBT模块采用单面封装的结构，模块的内部产生的热量仅仅可以从硅基IGBT芯片集电极排出。一些研究者尝试去掉硅基IGBT芯片发射极的引线，采用双面封装的结构来提高硅基IGBT模块的散热效率。这种封装结构可以使得模块内部产生的热量从芯片集电极和发射极两个方向排出。同时，这种封装结构去掉了引线键合可以有效的降低硅基IGBT模块的寄生电感。
但是，传统双面硅基IGBT模块的芯片连接材料采用的是焊料合金，它们的熔点一般低于300℃。这种焊料合金由于熔点低和易产生金属间化合物容易产生蠕变疲劳失效，尤其是在IGBT模块的高温应用环境中。所以，传统的焊料合金成为制约大功率硅基IGBT模块高温应用和功率密度提高的一大瓶颈。相对于焊料合金，纳米银焊膏具有烧结温度低(275℃)、熔点高(960℃)和热导率高(240W·m-1·K-1)等优点，从而可以更有效的提高大功率硅基IGBT模块的工作环境温度及使用寿命。但是，采用低温烧结纳米银的双面模块还没有被报道过，主要是因为多个大面积芯片与衬板烧结的连接强度不高(低于30 MPa)，尤其是采用裸铜DBC基板。由于芯片与裸铜DBC基板连接需要无氧环境，从而导致烧结连接过程中纳米银焊膏的有机物挥发不出来，进而导致较低的连接强度。
发明内容
为了解决上述问题，本发明专利的目的是提供一种新型工艺的采用低温烧结的纳米银焊膏的双面互连硅基IGBT模块。通过在甲酸环境中施加5-10MPa的压力实现芯片与DBC基板的连接强度高于30MPa。芯片和缓冲层与DBC基板的连接均采用纳米银焊膏。通过先进行功率端子焊接，再进行低温烧结连接纳米银焊膏的工艺顺序，避免了由于超声震动而引起纳米银烧结连接层脱落的问题。
本发明专利的技术方案如下：
一种采用低温烧结纳米银的双面互连硅基IGBT模块：由功率端子1、上DBC基板2、下DBC基板3、纳米银焊膏4、硅基IGBT芯片5、缓冲层6、粗铝丝7、焊片8、硅基二极管芯片9、硅凝胶和模制树脂组成；分别将硅基IGBT芯片的下表面、硅基二极管芯片的下表面以及缓冲层的下表面与下DBC基板连接，同时在上DBC基板也进行同样的连接；下DBC基板的硅基IGBT芯片和硅基二极管芯片以及缓冲层的上表面分别同时与上DBC基板的缓冲层以及硅基IGBT芯片和硅基二极管芯片的上表面连接。
一种采用低温烧结纳米银的双面互连硅基IGBT模块的方法，包括步骤如下：
(1)硅基IGBT芯片和所述硅基二极管芯片的上表面采用磁控溅射的方法镀一层银膜。
(2)双面互连硅基IGBT模块，先采用钢网印刷的方式在下DBC基板均匀涂覆纳米银焊膏，然后将所述的硅基IGBT芯片、硅基二极管芯片和缓冲层的下表面贴装在焊膏表面。
(3)双面互连硅基IGBT模块，在上DBC基板重复步骤(2)。
(4)将贴装好的上DBC基板和下DBC基板在甲酸环境中进行低温烧结连接，烧结温度为250℃-300℃，保温时间15-45min。
(5)在下DBC基板的硅基IGBT芯片、硅基二极管芯片和缓冲层上表面放置SnAgCu焊片或SnAg焊片，然后将下DBC基板置于定位夹具，将上DBC基板倒置放于下DBC基板，最后把组装完成的双面模块放在真空回流炉中进行焊接。
(6)灌冲硅凝胶对双面模块进行密闭保护，保温温度130℃-200℃，保温时间40-90min，最后将灌胶完成的双面模块进行塑封。
优选每一个硅基IGBT芯片对应一个硅基二极管芯片。
优选4个1200-V/150-A硅基IGBT芯片及对应的1200-V/150-A硅基二极管芯片并联在DBC基板上，从而实现双面互连的1200-V/600-A硅基IGBT模块的封装。
与现有技术相比，本发明有以下优点：
(1)双面互连硅基IGBT模块的功率芯片和缓冲层与DBC基板连接均采用纳米银低温烧结连接。芯片和缓冲层与DBC基板的连接强度可达30MPa以上。
(2)DBC基板采用的是裸铜陶瓷基板，而传统的纳米银低温烧结连接采用的是镀银的覆铜陶瓷基板。因此，采用本方法封装的双面互连硅基IGBT模块的成本更加低廉。
根据上述方案制造的双面互连硅基IGBT模块，由于采用纳米银焊膏作为芯片和缓冲层与DBC基板的连接材料，可有效提高该模块的工作环境温度及使用寿命。该双面模块封装紧凑，功率密度大、可靠性好。
附图说明
图1为本发明双面互连硅基IGBT模块的横截面结构示意图；
图2为本发明采用DBC基板结构示意图；
图3为本发明双面互连硅基IGBT模块的引线键合和端子连接示意图；
图4为本发明双面互连硅基IGBT模块定位夹具示意图；
图5为本发明双面互连硅基IGBT模块组装示意图。
其中：1-功率端子、2-上DBC基板、3-下DBC基板、4-纳米银焊膏、5-硅基IGBT芯片、6-缓冲层、7-粗铝丝、8-焊片、9-硅基二极管芯片
具体实施方式
下面结合附图，对本发明的具体实施方式作详细说明。
采用低温烧结纳米银的双面互连硅基IGBT模块的方法，具体包括如下步骤：
步骤一、采用超声焊接技术实现双面互连硅基IGBT模块端子1与DBC基板电极区的连接。端子与DBC基板电极区的材料均为纯铜。超声焊接功率为1.3-1.6W。
步骤二、DBC基板材料选择为裸铜陶瓷板，该材料具有较高的热导率和热膨胀系数。如图2所示，2为上DBC基板，3为下DBC基板。采用超声波清洗和等离子清洗的方法去除上DBC基板2和下DBC基板3表面的杂质。然后采用钢网在上DBC基板2和下DBC基板3上印刷纳米银焊膏4。接着将上DBC基板2和下DBC基板3放入甲酸环境中进行纳米银焊膏的一次烧结。烧结温度260℃，保温时间为20分钟。
步骤二、取出上DBC基板2和下DBC基板3进行二次钢网印刷纳米银焊膏。然后在上DBC基板2和下DBC基板3分别同时贴上硅基IGBT芯片5、硅基二极管芯片9和对应的缓冲层6。在进行烧结之前，轻轻挤压硅基IGBT芯片5、硅基二极管芯片9和缓冲层6使其与纳米银焊膏4充分的润湿。最后将贴装完成的上DBC基板2和下DBC基板3放入甲酸环境中进行纳米银焊膏的二次烧结。烧结温度和保温时间与步骤一相同。该阶段的烧结过程可以试加5-10MPa的压力，实现芯片和缓冲层与DBC基板的连接强度达30MPa以上。
步骤三、采用粗铝丝7实现大功率硅基IGBT芯片5的门极和DBC基板电极区连接。通过引线键合技术实现粗铝丝7的一端与大功率硅基IGBT芯片5门极连接，另一端与DBC基板电极区连接。由于硅基IGBT芯片5的发射极通过缓冲层与上DBC基板连接，所以铝线键合的高度不能超过缓冲层的高度，烧结及键合完成模块示意图见图3。
步骤五、在下DBC基板3的硅基IGBT芯片5、硅基二极管芯片9和缓冲层6上放置0.2毫米厚的焊片8。将下DBC基板3置于定位夹具中，定位夹具如图4所示，接着将同等大小，反向对称的上DBC基板2倒置并轻轻放置在下DBC基板3的上面，如图5所示，实现双面互连硅基IGBT模块的组装。最后将组装完成的双面模块放置在真空回流炉中进行焊接。
步骤六、填充密闭剂和塑封。密闭剂选用双组分硅凝胶，该硅胶在250℃能长期保持弹性，且具优良的电气性能和化学稳定性。填充完密闭剂，将模块放在真空干燥箱中并在150℃的环境中保温1小时以实现硅胶的固化。最后，采用塑封技术实现双面互连硅基IGBT模块的四周密闭树脂封装。

Claims (4)

1.一种采用低温烧结纳米银的双面互连硅基IGBT模块，由功率端子(1)、上DBC基板(2)、下DBC基板(3)、纳米银焊膏(4)、硅基IGBT芯片(5)、缓冲层(6)、粗铝丝(7)、焊片(8)、硅基二极管芯片(9)、硅凝胶和模制树脂组成；其特征是分别将硅基IGBT芯片的下表面、硅基二极管芯片的下表面以及缓冲层的下表面与下DBC基板通过纳米银连接，同时在上DBC基板也进行同样的连接；下DBC基板的硅基IGBT芯片和硅基二极管芯片以及缓冲层的上表面分别同时与上DBC基板的缓冲层以及硅基IGBT芯片和硅基二极管芯片的上表面通过焊料连接，得到双面互连硅基IGBT模块。
2.权利要求1的采用低温烧结纳米银的双面互连硅基IGBT模块的制备方法，包括步骤如下：
(1)硅基IGBT芯片和硅基二极管芯片的上表面采用磁控溅射的方法镀一层银膜；
(2)双面互连硅基IGBT模块，先采用钢网印刷的方式在下DBC基板均匀涂覆纳米银焊膏，然后将所述的硅基IGBT芯片、硅基二极管芯片和缓冲层的下表面贴装在焊膏表面；
(3)双面互连硅基IGBT模块，在上DBC基板重复步骤(2)；
(4)将贴装好的上DBC基板和下DBC基板在甲酸环境中进行低温烧结连接，烧结温度为250℃-300℃，保温时间15-45min，烧结过程可试加5-10MPa的压力；
(5)在下DBC基板的硅基IGBT芯片、硅基二极管芯片和缓冲层上表面放置SnAgCu焊片或SnAg焊片，然后将下DBC基板置于定位夹具，将上DBC基板倒置放于下DBC基板，最后把组装完成的双面模块放在真空回流炉中进行焊接；
(6)灌冲硅凝胶对双面模块进行密闭保护，保温温度130℃-200℃，保温时间40-90min，最后将灌胶完成的双面模块进行塑封。
3.如权利要求2所述的方法，其特征是每一个硅基IGBT芯片对应一个硅基二极管芯片。
4.如权利要求2所述的方法，其特征是4个1200-V/150-A硅基IGBT芯片及对应的1200-V/150-A硅基二极管芯片并联在DBC基板上，实现双面互连的1200-V/600-A硅基IGBT模块的封装。
CN201710952767.8A 2017-10-13 2017-10-13 采用低温烧结纳米银的双面互连硅基igbt模块的方法 Pending CN107887368A (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201710952767.8A CN107887368A (zh) 2017-10-13 2017-10-13 采用低温烧结纳米银的双面互连硅基igbt模块的方法
PCT/CN2017/112769 WO2019071743A1 (zh) 2017-10-13 2017-11-24 采用低温烧结纳米银的双面互连硅基igbt模块的方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710952767.8A CN107887368A (zh) 2017-10-13 2017-10-13 采用低温烧结纳米银的双面互连硅基igbt模块的方法

Publications (1)

Publication Number Publication Date
CN107887368A true CN107887368A (zh) 2018-04-06

Family

ID=61781588

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710952767.8A Pending CN107887368A (zh) 2017-10-13 2017-10-13 采用低温烧结纳米银的双面互连硅基igbt模块的方法

Country Status (2)

Country Link
CN (1) CN107887368A (zh)
WO (1) WO2019071743A1 (zh)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109786345A (zh) * 2019-03-13 2019-05-21 黄山宝霓二维新材科技有限公司 石墨烯基ipm模块的先进封装结构及加工工艺
CN109887909A (zh) * 2019-03-13 2019-06-14 黄山学院 基于石墨烯的ipm混合模块封装结构及加工工艺
CN109920785A (zh) * 2019-03-13 2019-06-21 黄山学院 双面散热ipm混合模块的封装结构及加工工艺
CN109994373A (zh) * 2019-04-12 2019-07-09 中国电子科技集团公司第三十八研究所 一种微组装裸芯片连接及返修方法
CN110571204A (zh) * 2019-08-28 2019-12-13 天津大学 具有双面散热能力的双向开关功率器件及制作方法
CN111725196A (zh) * 2020-06-30 2020-09-29 中南大学 一种高温原位紫外探测系统
CN111799251A (zh) * 2020-07-09 2020-10-20 华羿微电子股份有限公司 采用多芯片堆叠结构的功率分立器件及其制备方法
CN112259513A (zh) * 2020-10-22 2021-01-22 湖南国芯半导体科技有限公司 一种双面散热功率模块及其封装方法
CN112271141A (zh) * 2020-10-23 2021-01-26 浙江大学 一种双面散热功率半导体模块及制造方法
CN113140472A (zh) * 2020-01-20 2021-07-20 北京新能源汽车股份有限公司 冷却功率模块的制作工艺
WO2023206594A1 (zh) * 2022-04-29 2023-11-02 赵岩 一种压接结构的碳化硅器件及其制造方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115188681B (zh) * 2022-09-09 2023-01-06 深圳平创半导体有限公司 一种微纳米金属焊膏脉冲电烧结方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103594395A (zh) * 2013-10-24 2014-02-19 天津大学 纳米银焊膏粘接大面积芯片的加压辅助烧结模块及方法
CN105070695A (zh) * 2015-08-14 2015-11-18 株洲南车时代电气股份有限公司 双面散热电动汽车功率模块
CN106653627A (zh) * 2016-10-11 2017-05-10 天津大学 一种纳米银焊膏连接裸铜衬底或敷铜基板的烧结方法
CN107170720A (zh) * 2017-06-14 2017-09-15 扬州国扬电子有限公司 一种叠层封装双面散热功率模块

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9041183B2 (en) * 2011-07-19 2015-05-26 Ut-Battelle, Llc Power module packaging with double sided planar interconnection and heat exchangers
KR101289196B1 (ko) * 2011-09-14 2013-07-26 삼성전기주식회사 전력 모듈 패키지 및 그 제조방법
CN106449552A (zh) * 2016-12-01 2017-02-22 江苏宏微科技股份有限公司 双面直接冷却散热结构的功率模块

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103594395A (zh) * 2013-10-24 2014-02-19 天津大学 纳米银焊膏粘接大面积芯片的加压辅助烧结模块及方法
CN105070695A (zh) * 2015-08-14 2015-11-18 株洲南车时代电气股份有限公司 双面散热电动汽车功率模块
CN106653627A (zh) * 2016-10-11 2017-05-10 天津大学 一种纳米银焊膏连接裸铜衬底或敷铜基板的烧结方法
CN107170720A (zh) * 2017-06-14 2017-09-15 扬州国扬电子有限公司 一种叠层封装双面散热功率模块

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
龚云表，石安富: "《高分子密封材料》", 30 November 1983, 上海科学技术出版 *

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109887909A (zh) * 2019-03-13 2019-06-14 黄山学院 基于石墨烯的ipm混合模块封装结构及加工工艺
CN109920785A (zh) * 2019-03-13 2019-06-21 黄山学院 双面散热ipm混合模块的封装结构及加工工艺
CN109887909B (zh) * 2019-03-13 2020-06-23 黄山学院 基于石墨烯的ipm混合模块封装结构及加工工艺
CN109786345A (zh) * 2019-03-13 2019-05-21 黄山宝霓二维新材科技有限公司 石墨烯基ipm模块的先进封装结构及加工工艺
CN109786345B (zh) * 2019-03-13 2024-04-23 黄山谷捷股份有限公司 石墨烯基ipm模块的先进封装结构及加工工艺
CN109994373A (zh) * 2019-04-12 2019-07-09 中国电子科技集团公司第三十八研究所 一种微组装裸芯片连接及返修方法
CN110571204A (zh) * 2019-08-28 2019-12-13 天津大学 具有双面散热能力的双向开关功率器件及制作方法
CN113140472A (zh) * 2020-01-20 2021-07-20 北京新能源汽车股份有限公司 冷却功率模块的制作工艺
CN111725196A (zh) * 2020-06-30 2020-09-29 中南大学 一种高温原位紫外探测系统
CN111725196B (zh) * 2020-06-30 2023-11-28 长沙安牧泉智能科技有限公司 一种高温原位紫外探测系统
CN111799251A (zh) * 2020-07-09 2020-10-20 华羿微电子股份有限公司 采用多芯片堆叠结构的功率分立器件及其制备方法
CN112259513A (zh) * 2020-10-22 2021-01-22 湖南国芯半导体科技有限公司 一种双面散热功率模块及其封装方法
CN112259513B (zh) * 2020-10-22 2023-09-26 湖南国芯半导体科技有限公司 一种双面散热功率模块及其封装方法
CN112271141A (zh) * 2020-10-23 2021-01-26 浙江大学 一种双面散热功率半导体模块及制造方法
WO2023206594A1 (zh) * 2022-04-29 2023-11-02 赵岩 一种压接结构的碳化硅器件及其制造方法

Also Published As

Publication number Publication date
WO2019071743A1 (zh) 2019-04-18

Similar Documents

Publication Publication Date Title
CN107887368A (zh) 采用低温烧结纳米银的双面互连硅基igbt模块的方法
CN110854103B (zh) 一种嵌入式双面互连功率模块封装结构和制作方法
WO2018227655A1 (zh) 一种低寄生电感功率模块及双面散热低寄生电感功率模块
CN107195623B (zh) 一种双面散热高可靠功率模块
CN110838480B (zh) 一种碳化硅mosfet模块的封装结构和制作方法
CN106910691B (zh) 功率变流器中igbt模块的散热结构及封装工艺
CN106340513A (zh) 一种集成控制电路的功率模块
CN107170720A (zh) 一种叠层封装双面散热功率模块
CN107910324A (zh) 一种基于纳米银焊膏双面互连碳化硅mos器件的模块化封装方法
CN113130455B (zh) 一种高热可靠性的多单元功率集成模块及其加工工艺
WO2023246214A1 (zh) 一种功率模组及其制造方法
CN113497014B (zh) 一种多芯片并联的功率模块的封装结构及封装方法
CN102130020A (zh) 一种碳化硅功率器件的封装方法
CN107146775A (zh) 一种低寄生电感双面散热功率模块
CN109273371A (zh) 一种功率半导体器件封装结构及封装方法
CN109786345B (zh) 石墨烯基ipm模块的先进封装结构及加工工艺
CN113838821A (zh) 一种用于SiC平面封装结构的散热件及其制备方法
CN210073809U (zh) 一种压接式igbt内部封装结构
CN216849941U (zh) 一种新型可反向导通氮化镓功率器件
CN110571204A (zh) 具有双面散热能力的双向开关功率器件及制作方法
CN110211885A (zh) 功率芯片预封装、封装方法及其结构、晶圆预封装结构
CN214705909U (zh) 一种3d双面散热封装结构的功率模块
CN115312505A (zh) 一种功率器件的无引线封装结构及封装方法
CN203775045U (zh) 一种智能半导体功率模块
CN103780102B (zh) 一种智能半导体功率模块

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20180406