CN107910324A - 一种基于纳米银焊膏双面互连碳化硅mos器件的模块化封装方法 - Google Patents
一种基于纳米银焊膏双面互连碳化硅mos器件的模块化封装方法 Download PDFInfo
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Abstract
本发明涉及一种基于纳米银焊膏双面互连碳化硅MOS器件的模块及封装方法；由功率端子、上DBC基板、下DBC基板、纳米银焊膏、缓冲层、n对碳化硅FRED芯片和碳化硅MOS芯片、栅极电阻、粗铝丝、硅凝胶和模制树脂组成；分别将碳化硅MOS芯片下表面、碳化硅FRED芯片下表面以及缓冲层的下表面平行并联在下DBC基板；同样上DBC基板进行同样的连接；将碳化硅MOS芯片和碳化硅FRED芯片的上表面与上DBC基板的缓冲层上表面相连，同样的，下DBC基板的缓冲层与上DBC基板的碳化硅MOS芯片和碳化硅FRED芯片相互连接。功率芯片和缓冲层与DBC基板的连接均采用纳米银焊膏，具有烧结温度低、熔点高和热导率高优点。
Description
技术领域
本发明涉及功率电子器件封装技术领域，特别是一种基于纳米银焊膏双面互连碳化硅MOS器件的模块化封装方法。
背景技术
碳化硅功率半导体器件具有击穿电压强度高、能带隙宽、热导率高等优点，这些特性使得碳化硅器件超越硅器件更适合应用在高功率密度、高开关频率等场所。同时，传统的硅器件的极限工作温度仅仅为200℃，而碳化硅基功率器件能够在500℃以上的环境温度下工作。因此，碳化硅功率器件可以应用在许多恶劣的环境中，比如航空航天和飞机等。
但是，碳化硅器件在高频、高电压和大电流工作条件下会产生大量的耗散热量，从而影响器件的可靠性。为了保证半导体器件的可靠性运行，高电流能力和低封装互联阻抗是该器件封装设计的关键问题之一。传统的半导体功率器件采用的单面封装结构散热效率不高，其内部产生的热量仅仅可以从半导体功率芯片的下表面排出。近年来，双面封装结构得到越来越到的关注，因为它能够大幅提高半导体功率器件的散热效率。该封装结构可以使得半导体功率器件内部产生的热量从半导体功率芯片的上表面和下表面两个方向排出。同时，该封装结构去掉了引线键合可以有效的降低半导体功率器件的寄生电感。
但是双面互连碳化硅MOS器件的封装还没有人报道过，主要是因为单个碳化硅MOS芯片的开关速度比较快，从而引起多个(比如8个芯片以上)碳化硅芯片并联会引起电流不均流性的问题。同时由于碳化硅MOS芯片的工作环境温度比较高，采用传统的焊料合金作为芯片连接材料成为制约双面互连碳化硅MOS模块封装应用的另一个因素。
发明内容
为了解决这个问题，本发明的目的是提供一种电流均流性好、耐高温的一种基于纳米银焊膏双面互连碳化硅MOS器件的模块化封装方法。通过在模块中每个碳化硅MOS芯片串联一个栅极电阻降低开关速度的方法，实现多个芯片均流性一致。采用纳米银焊膏作为芯片连接材料解决了双面互连的碳化硅MOS器件的高温应用问题。
本发明专利的技术方案如下：
一种一种基于纳米银焊膏双面互连碳化硅MOS器件的模块化封装方法：由功率端子1、上DBC基板2、下DBC基板3、纳米银焊膏4、缓冲层5、n对碳化硅FRED芯片6和碳化硅MOS芯片7、栅极电阻8、粗铝丝9、硅凝胶和模制树脂组成。分别将所述碳化硅MOS芯片的下表面、碳化硅FRED芯片的下表面以及缓冲层的下表面平行并联在下DBC基板上，上DBC基板进行同样的连接；然后将碳化硅MOS芯片和碳化硅FRED芯片的上表面与上DBC基板的缓冲层上表面相连，同样的，下DBC基板的缓冲层与上DBC基板的碳化硅MOS芯片和碳化硅FRED芯片相互连接。
一种基于纳米银焊膏双面互连碳化硅MOS器件的模块化封装方法，步骤如下：
(1)优选碳化硅MOS芯片和碳化硅FRED芯片的上表面采用磁控溅射的方法镀一层膜。
(2)优选采用钢网印刷的方式在下DBC基板均匀涂覆纳米银焊膏，然后将所述的碳化硅MOS芯片、碳化硅FRED芯片和缓冲层的下表面贴装在焊膏表面。
(3)在上DBC基板重复步骤(2)。
(4)优选将贴装完成的上DBC基板和下DBC基板在甲酸环境中进行低温无压烧结，烧结温度为250℃-300℃，保温时间15-45min。
(5)优选在下DBC基板的碳化硅MOS芯片、碳化硅FRED芯片和缓冲层上表面放置SnAgCu焊片或SnAg焊片，然后将上DBC基板倒置于下DBC基板上，最后将组装完成的双面模块放在真空回流炉中进行焊接。
(6)优选灌冲硅凝胶对双面模块进行密闭保护，保温温度130℃-200℃，保温时间40-90min，最后将灌胶完成的双面模块进行塑封。
优选缓冲层为鉬或鉬铜合金。
优选该功率半导体器件中芯片材料均采用碳化硅。
优选双面互连碳化硅MOS器件中碳化硅MOS芯片、碳化硅FRED芯片和缓冲层与DBC基板连接均采用纳米银低温无压烧结连接。
优选纳米银焊膏的烧结连接在甲酸环境中进行。
优选DBC基板包括氧化铝陶瓷DBC基板、氧化铝陶瓷DBA基板、氮化硅AMB和氮化铝DBC。
与现有技术相比，本发明有以下优点：
(1)该发明专利中首次研发制备全碳化硅半导体功率器件，即MOS芯片和FRED芯片的材料均采用碳化硅。
(2)该发明专利制备的双面互连的碳化硅MOS模块多个芯片的电流均流性基本一致。
(3)该发明专利中功率芯片和缓冲层与DBC基板的连接均采用纳米银焊膏，具有烧结温度低(275℃)、熔点高(960℃)和热导率高(240W·m-1·K-1)等优点。
附图说明
图1为本发明采用DBC基板结构示意图；
图2为本发明双面互连碳化硅MOS器件连接示意图；
图3为本发明双面互连碳化硅MOS器件定位夹具示意图。
图4为本发明双面互连碳化硅MOS器件组装示意图。
其中：1-功率端子、2-下DBC基板、3-上DBC基板、4-纳米银焊膏、5-缓冲层、6-碳化硅FRED芯片、7-碳化硅MOS芯片、8-栅极电阻、9-粗铝丝
具体实施方式
下面结合附图，对本发明的具体实施方式作详细说明。
采用低温烧结纳米银的双面互连碳化硅MOS器件的方法，具体包括如下步骤：
步骤一、采用超声焊接技术实现该双面互连碳化硅MOS器件的功率端子1与上DBC基板和下DBC基板电极区的连接。功率端子与DBC基板电极区的材料均为纯铜。
步骤二、如图1所示，2为下DBC基板，3为上DBC基板。采用超声波清洗和等离子清洗的方法去除下DBC基板2和上DBC基板3表面的杂质。然后采用钢网在下DBC基板2和上DBC基板3上印刷纳米银焊膏4。接着将下DBC基板2和上DBC基板3放入真空烧结炉中进行纳米银焊膏的一次烧结。烧结温度260℃，保温时间为20分钟。
步骤三、取出下DBC基板2和上DBC基板3进行二次钢网印刷纳米银焊膏。然后在下DBC基板2和上DBC基板3分别同时贴上缓冲层5、碳化硅FRED芯片6、碳化硅MOS芯片7。在进行烧结之前，轻轻挤压缓冲层5、碳化硅MOS芯片6和碳化硅FRED芯片7使其与纳米银焊膏4充分的润湿。同时，通过纳米银焊膏4将栅极电阻8粘接在DBC基板上。最后将贴装完成的下DBC基板2和上DBC基板3放入甲酸环境中进行纳米银焊膏的二次烧结连接。
步骤四、采用粗铝丝9实现大功率碳化硅MOS芯片的栅极和DBC基板电极区连接。通过引线键合技术实现粗铝丝9的一端与大功率碳化硅MOS芯片栅极连接，另一端与DBC基板电极区连接。同时，铝线键合的高度不能超过缓冲层的高度，如图2所示。
步骤五、在缓冲层5、碳化硅FRED芯片6、碳化硅MOS芯片7的上表面涂抹上纳米银焊膏。然后将下DBC基板2置于定位夹具中，定位夹具如图3所示，接着将同等大小，反向对称的上DBC基板3倒置并轻轻放置在下DBC基板2的上面，实现双面互连碳化硅MOS器件的组装。最后将组装完成的双面互连碳化硅MOS器件放置在真空回流炉中进行低温无压烧结连接，如图4所示。
步骤六、填充完硅凝胶，将模块放在真空干燥箱中并在150℃的环境中保温1小时以实现硅凝胶的固化。最后，采用塑封技术实现双面互连碳化硅MOS器件的模块的四周密闭树脂封装。
Claims (7)
1.一种基于纳米银焊膏双面互连碳化硅MOS器件的模块；由功率端子1、上DBC基板2、下DBC基板3、纳米银焊膏4、缓冲层5、n对碳化硅FRED芯片6和碳化硅MOS芯片7、栅极电阻8、粗铝丝9、硅凝胶和模制树脂组成；其特征是分别将所述碳化硅MOS芯片的下表面、碳化硅FRED芯片的下表面以及缓冲层的下表面平行并联在下DBC基板；同样上DBC基板进行同样的连接；然后将碳化硅MOS芯片和碳化硅FRED芯片的上表面与上DBC基板的缓冲层上表面相连，同样的，下DBC基板的缓冲层与上DBC基板的碳化硅MOS芯片和碳化硅FRED芯片相互连接。
2.权利要求1的一种基于纳米银焊膏双面互连碳化硅MOS器件的模块封装方法，其特征是包括步骤如下：
(1)碳化硅MOS芯片和碳化硅FRED芯片的上表面采用磁控溅射的方法镀一层膜；
(2)采用钢网印刷的方式在下DBC基板均匀涂覆纳米银焊膏，然后将所述的碳化硅MOS芯片、碳化硅FRED芯片和缓冲层的下表面贴装在焊膏表面；
(3)在上DBC基板重复步骤(2)；
(4)将贴装完成的上DBC基板和下DBC基板在甲酸环境中进行低温无压烧结，烧结温度为250℃-300℃，保温时间15-45min；
(5)在下DBC基板的碳化硅MOS芯片、碳化硅FRED芯片和缓冲层上表面放置SnAgCu焊片或SnAg焊片，然后将上DBC基板倒置于下DBC基板上，最后将组装完成的双面模块放在真空回流炉中进行焊接；
(6)灌冲硅凝胶对双面模块进行密闭保护，保温温度130℃-200℃，保温时间40-90min，最后将灌胶完成的双面模块进行塑封。
3.如权利要求2所述的方法，其特征是缓冲层为鉬或鉬铜合金。
4.如权利要求2所述的方法，其特征是芯片材料采用碳化硅。
5.如权利要求2所述的方法，其特征是双面互连碳化硅MOS器件中碳化硅MOS芯片、碳化硅FRED芯片和缓冲层与DBC基板连接采用纳米银低温无压烧结连接。
6.如权利要求2所述的方法，其特征是纳米银焊膏的烧结连接在甲酸环境中进行。
7.如权利要求2所述的方法，其特征是DBC基板包括氧化铝陶瓷DBC基板、氧化铝陶瓷DBA基板、氮化硅AMB或氮化铝DBC。
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