CN109411464A - 一种基于快速烧结纳米银焊膏无压互连技术的1200v/50a igbt功率模块 - Google Patents

一种基于快速烧结纳米银焊膏无压互连技术的1200v/50a igbt功率模块 Download PDF

Info

Publication number
CN109411464A
CN109411464A CN201811079007.1A CN201811079007A CN109411464A CN 109411464 A CN109411464 A CN 109411464A CN 201811079007 A CN201811079007 A CN 201811079007A CN 109411464 A CN109411464 A CN 109411464A
Authority
CN
China
Prior art keywords
igbt
chip
nano mattisolda
substrate
module
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201811079007.1A
Other languages
English (en)
Inventor
梅云辉
张心印
李欣
陆国权
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tianjin University
Original Assignee
Tianjin University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tianjin University filed Critical Tianjin University
Priority to CN201811079007.1A priority Critical patent/CN109411464A/zh
Publication of CN109411464A publication Critical patent/CN109411464A/zh
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/14Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15Ceramic or glass substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601Structure
    • H01L2224/0603Bonding areas having different sizes, e.g. different heights or widths
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8384Sintering

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

本发明涉及一种基于快速烧结纳米银焊膏无压互连技术的1200V/50A IGBT功率模块;底板材料为镀镍的厚铜块或AlSiC,在所述底板上反向放置两块同样电路样式的陶瓷覆铜DBC基板;基板之间通过连接桥连接;两组IGBT芯片和续流二极管芯片并联支路组与基板互连;采用双层印刷变温预热焊膏的方法,芯片与DBC基板之间通过连续脉冲电流辅助无压烧结纳米银焊膏实现瞬时连接;烧结连接时间不大于15秒;再通过引线键合,真空回流二次焊接,安装管壳,填充密闭剂制备IGBT模块。与同等级的商业IGBT模块相比,本发明的IGBT模块具有良好的电气性能,更低的热阻和更优的散热特性,同时具有优异的抗热循环疲劳老化能力。

Description

一种基于快速烧结纳米银焊膏无压互连技术的1200V/50A IGBT功率模块
技术领域
本发明涉及一种基于快速烧结纳米银焊膏无压互连技术的1200V/50A IGBT功率模块,属于功率电子器件封装技术领域。
背景技术
IGBT模块广泛应用于通信、计算机、消费电子、汽车电子、船舶驱动、航空航天、加工装备、国防军工等传统产业领域以及轨道交通、新能源、智能电网、新能源汽车等战略性新兴产业领域。IGBT以其驱动功率小、输入阻抗高、开关速度快、通态压降小、载流密度大、阻断电压高等特点,成为电力电子行业中的主要功率器件。采用IGBT进行功率变换,能够提高用电效率和质量,具有高效节能和绿色环保的特点,是解决能源短缺问题和降低碳排放的关键支撑技术,被称为功率变流产品的“CPU”、“绿色经济之核”。
以传统的1200V/50A IGBT功率模块为例,模块芯片封装使用焊料合金,经过回流,焊料完全溶解形成粘接。然而由于较低的熔点和工作温度(<300℃),传统焊料合金的使用将降低模块的可靠性,限制功率模块的高温工作能力。
纳米银焊膏具有熔点高(961℃)、导电、导热性能优好、绿色无铅等优点,适用于高温大功率和高密度封装,能提高功率模块高温服役的可靠性,成为IGBT功率模块高温应用的首选互连材料。
目前纳米银焊膏普遍采用热压烧结工艺,但是热压烧结工艺存在一些弊端:所需烧结时间较长(>1小时),工艺条件复杂,效率较低。施压定位夹具装置也不利于封装功率半导体器件自动化生产,施加的压力选取不当有可能对芯片造成永久性破坏。
发明内容
考虑到上述情况,本发明公开一种基于快速烧结纳米银焊膏无压互连技术的1200V/50A IGBT功率模块,烧结连接过程无需额外施加辅助压力,仅在10s-15s即可完成电流辅助无压烧结纳米银焊膏,本发明的IGBT模块与同等级的1200V/50A商业IGBT模块相比,具有良好的电气性能,更低的热阻和更优的散热特性,具有优异的抗热循环疲劳老化能力,可靠性更优。
本发明采用的技术方案如下:
一种基于快速烧结纳米银焊膏无压互连技术的1200V/50A IGBT功率模块;其特征是底板材料为镀镍的厚铜块或AlSiC,在所述底板上反向放置两块同样电路样式的陶瓷覆铜DBC基板;基板之间通过连接桥连接;两组IGBT芯片和续流二极管芯片并联支路组与基板互连;采用双层印刷变温预热焊膏的方法,芯片与DBC基板之间通过连续脉冲电流辅助无压烧结纳米银焊膏实现瞬时连接;烧结连接时间不大于15秒;再通过引线键合,真空回流二次焊接,安装管壳,填充密闭剂制备IGBT模块。
所述的IGBT芯片并联支路组,每块DBC基板上有若干IGBT芯片和续流二极管芯片并联;IGBT芯片与续流二极管芯片数量比为1:1;所述二极管芯片的阳极与其对应的IGBT芯片的发射极电气连接于同一个发射极汇流结构。
所述的双层印刷变温预热焊膏的方法是:第一步,在DBC基板待连接区域利用丝网印刷的方式印制一层30μm~40μm的单层纳米银焊膏,置于100℃~120℃加热装置中预热10min~20min,促使该单层纳米银焊膏中的有机溶剂在100℃~120℃充分挥发;第二步,再次利用丝网印刷的方式,在上述预干燥后的纳米银焊膏层再次印制一层30μm~40μm的纳米银焊膏,随后置于130℃~150℃加热装置中预热10min~20min。
所述的脉冲电流辅助无压快速烧结纳米银焊膏的连接过程,IGBT芯片和二极管芯片紧密贴装在预热完成的焊膏上,电极预压在DBC基板上,施加直流脉冲电流值为0.8kA~1.0kA,脉冲电流的占空比为75%~80%,电流导通时间为10s~15s。
具体说明如下:
本发明的一种基于快速烧结纳米银焊膏无压互连技术的1200V/50A IGBT功率模块,模块底板材料为镀镍的厚铜块或AlSiC;在所述底板上反向放置两块同样电路样式的陶瓷覆铜(DBC)基板;基板之间通过连接桥连接;两组IGBT芯片和续流二极管芯片并联支路组与基板互连;芯片与DBC基板之间通过连续脉冲电流辅助无压烧结纳米银焊膏实现瞬时连接;烧结连接时间不大于15秒;与同等级的商业IGBT模块相比,本发明的IGBT模块具有良好的电气性能,更低的热阻和更优的散热特性,且封装工艺时间大幅缩短;由于烧结银互连层致密度高,使得该发明IGBT模块具有优异的抗热循环疲劳老化能力,可靠性更优。
所述的IGBT芯片并联支路组,每块DBC基板上有若干IGBT芯片和续流二极管芯片并联;IGBT芯片与续流二极管芯片数量比为1:1;所述二极管芯片的阳极与其对应的IGBT芯片的发射极电气连接于同一个发射极汇流结构。
所述的模块模块烧结连接过程无需额外施加辅助压力,仅在10s-15s即可完成电流辅助无压烧结纳米银焊膏,实现IGBT芯片/二极管芯片与DBC基板瞬间连接;采用双层印刷变温预热焊膏的方法,实现焊膏多步预干燥,可避免焊膏中有机溶剂在烧结过程中由于快速挥发或烧蚀产生显著应力,避免芯片互连层中存在大量气道,从而提高互连强度,降低接触电阻和热阻;该方法区别于通过施加显著辅助压力的传统烧结方法,可有效避免半导体芯片中晶体管单元受压预损坏的风险。
所述双层印刷变温预热焊膏的方法,先在DBC基板待连接区域利用丝网印刷的方式印制一层30μm~40μm的单层纳米银焊膏,置于100℃~120℃加热装置中预热10min~20min,促使该单层纳米银焊膏中的有机溶剂会在100℃~120℃充分挥发。随后利用丝网印刷的方式,在上述预干燥后的纳米银焊膏层再次印制一层30μm~40μm的纳米银焊膏,随后置于130℃~150℃加热装置中预热10min~20min;由于第一次印刷的焊膏经过预热有机物已充分挥发,且第二层纳米银焊膏覆盖在第一层纳米银焊膏后,焊膏层厚度也变为原来的两倍,为保证第二层焊膏与第一层焊膏充分润湿,应适度提高预热温度至130℃~150℃;但再次预热温度不能过高,应考虑避免过高温度导致预干燥期间焊膏中纳米银颗粒过度发生非致密性表面扩散行为,降低银颗粒烧结致密化的扩散驱动力,导致焊膏随后烧结温度时也无法获得较高的密度烧结银接头,降低芯片互连连接强度。
所述脉冲电流辅助无压快速烧结纳米银焊膏的瞬时连接方法,IGBT芯片和二极管芯片紧密贴装在预热完成的焊膏上,电极预压在DBC基板上,施加直流脉冲电流值优选为0.8kA~1.0kA,脉冲电流的占空比为75%~80%,电流导通时间优选为10s~15s。
与现有技术相比,本发明有以下优点:
本发明基于快速烧结纳米银焊膏无压互连技术的1200V/50A IGBT功率模块,烧结连接过程无需额外施加辅助压力,仅在10s~15s即可完成电流辅助无压烧结纳米银焊膏,实现IGBT芯片/二极管芯片与DBC基板瞬间连接;采用双层印刷变温预热焊膏的方法,实现焊膏多步预干燥,可避免焊膏中有机溶剂在烧结过程中由于快速挥发或烧蚀产生显著应力,避免芯片互连层中存在大量气道,从而提高互连强度,降低接触电阻和热阻;该方法区别于通过施加显著辅助压力的传统烧结方法,可有效避免半导体芯片中晶体管单元受压预损坏的风险。与同等级的商业IGBT模块相比,本发明的IGBT模块具有良好的电气性能,更低的热阻和更优的散热特性,且封装工艺时间大幅缩短;由于烧结银互连层致密度高,使得该发明IGBT模块具有优异的抗热循环疲劳老化能力,可靠性更优。
附图说明
图1为本发明所用DBC基板。
图2为印有焊膏的基板示意图。
图3为本发明所用电流烧结电极示意图。
图4为未安装壳体的1200V/50A IGBT模块俯视结构示意图。
图5为安装壳体的1200V/50A IGBT模块结构示意图。
其中:1-下铜层、2-陶瓷、3-上铜层、4-纳米银焊膏、5-电极压头、6-IGBT芯片、7-二极管芯片、8-连接桥、9-引线、10-底板、11-管壳、12-电极端子。
具体实施方式
下面结合附图,对本发明的具体实施方式作详细说明。
一种基于快速烧结纳米银焊膏互连技术的1200V/50A IGBT功率模块,具体步骤如下:
步骤一:DBC基板超声清洗预处理。DBC基板如图1所示,首先使用无水酒精超声清洗DBC基板,通过物理震荡的方法去除基板表面可能存在的污染物颗粒,然后用氮气枪吹干DBC基板表面。
步骤二:印刷纳米银焊膏。首先在DBC基板待连接区域利用丝网印刷的方式印制一层30μm~40μm的单层纳米银焊膏,置于100℃~120℃加热装置中预热10min~20min,随后利用丝网印刷的方式,在上述预干燥后的纳米银焊膏层再次印制一层30μm~40μm的纳米银焊膏,随后置于130℃~150℃加热装置中预热10min~20min。印有焊膏的基板如图2所示。
步骤三:电流烧结。用贴片机将IGBT芯片6和二极管芯片7紧密贴装在预热完成的焊膏上,将电极预压在DBC基板上,与工件接触良好,施加0.8kA~1.0kA直流脉冲电流,脉冲电流的占空比为75%~80%,通电时间为10s~15s。如图3所示,当直流脉冲电流从其中一钨电极沿基板表面流至另一钨电极过程中,利用所产生的大量电阻热实现纳米银焊膏的快速烧结。
步骤四:引线键合。利用超声键合设备完成IGBT和续流二极管芯片与DBC基板电极区引线9键合,二极管芯片的阳极与其对应的IGBT芯片的发射极电气连接于同一个发射极汇流结构,完成引线键合的1200V/50A IGBT模块如图4所示。
步骤五:真空回流炉二次焊连接。将焊片放在底板10上,底板上反向放置两块同样电路样式的陶瓷覆铜(DBC)基板;基板之间通过连接桥连接;并用焊片将电极端子12和连接桥8的焊接面处包裹住并放在基板的电极焊接区上,然后将整个模块放进真空回流炉中完成真空回流焊接。
步骤六:安装外壳,涂胶封装。将管壳11安装到底板上并采用高温环氧树脂涂抹封装,在模块中填充抽真空的双组分硅胶密闭剂,放入真空干燥箱中,在120℃下保温1小时将硅胶固化,最后将电极12弯折成型,最终完成壳体安装的1200V/50A IGBT模块如图5所示。
实例1:对基于快速烧结纳米银焊膏互连技术的1200V/50A IGBT功率模块进行绝缘漏电测试,静态I-V特性,动态开关特性测试,与同等级商业模块漏电曲线基本吻合,具有同样良好的电气性能。
实例2:对基于快速烧结纳米银焊膏互连技术的1200V/50A IGBT功率模块进行热阻测试,与同等级商业模块相比,热阻降低12%,具有更好的散热特性,在相同负载的条件下,电流快速烧结纳米银焊膏制备的IGBT模块结温更低。
实例3:对基于快速烧结纳米银焊膏互连技术的1200V/50A IGBT功率模块进行高低温冲击老化和功率循环老化试验,同等级商业模块低经历500cycles老化后,模块失效。电流快速烧结纳米银焊膏制备的IGBT模块经历1000cycles的高低温老化冲击,其热阻并没有显著增加。同等级商业模块的寿命经历63K cycles时失效,电流快速烧结纳米银焊膏制备的IGBT模块的寿命为80K cycles。
本发明基于快速烧结纳米银焊膏无压互连技术的1200V/50A IGBT功率模块,烧结连接过程无需额外施加辅助压力,仅在10s~15s即可完成电流辅助无压烧结纳米银焊膏,与同等级的商业IGBT模块相比,本发明的IGBT模块具有良好的电气性能,更低的热阻和更优的散热特性,且封装工艺时间大幅缩短;由于烧结银互连层致密度高,使得该发明IGBT模块具有优异的抗热循环疲劳老化能力,可靠性更优,具有很高的推广价值。

Claims (4)

1.一种基于快速烧结纳米银焊膏无压互连技术的1200V/50A IGBT功率模块;其特征是底板材料为镀镍的厚铜块或AlSiC,在所述底板上反向放置两块同样电路样式的陶瓷覆铜DBC基板;基板之间通过连接桥连接;两组IGBT芯片和续流二极管芯片并联支路组与基板互连;采用双层印刷变温预热焊膏的方法,芯片与DBC基板之间通过连续脉冲电流辅助无压烧结纳米银焊膏实现瞬时连接;烧结连接时间不大于15秒;再通过引线键合,真空回流二次焊接,安装管壳,填充密闭剂制备IGBT模块。
2.如权利要求1所的模块;其特征是所述的IGBT芯片并联支路组,每块DBC基板上有若干IGBT芯片和续流二极管芯片并联;IGBT芯片与续流二极管芯片数量比为1:1;所述二极管芯片的阳极与其对应的IGBT芯片的发射极电气连接于同一个发射极汇流结构。
3.如权利要求1所的模块;其特征是所述的双层印刷变温预热焊膏的方法是:第一步,在DBC基板待连接区域利用丝网印刷的方式印制一层30μm~40μm的单层纳米银焊膏,置于100℃~120℃加热装置中预热10min~20min,促使该单层纳米银焊膏中的有机溶剂在100℃~120℃充分挥发;第二步,再次利用丝网印刷的方式,在上述预干燥后的纳米银焊膏层再次印制一层30μm~40μm的纳米银焊膏,随后置于130℃~150℃加热装置中预热10min~20min。
4.如权利要求1所的模块;其特征是所述的脉冲电流辅助无压快速烧结纳米银焊膏的连接过程,IGBT芯片和二极管芯片紧密贴装在预热完成的焊膏上,电极预压在DBC基板上,施加直流脉冲电流值为0.8kA~1.0kA,脉冲电流的占空比为75%~80%,电流导通时间为10s~15s。
CN201811079007.1A 2018-09-17 2018-09-17 一种基于快速烧结纳米银焊膏无压互连技术的1200v/50a igbt功率模块 Pending CN109411464A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201811079007.1A CN109411464A (zh) 2018-09-17 2018-09-17 一种基于快速烧结纳米银焊膏无压互连技术的1200v/50a igbt功率模块

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201811079007.1A CN109411464A (zh) 2018-09-17 2018-09-17 一种基于快速烧结纳米银焊膏无压互连技术的1200v/50a igbt功率模块

Publications (1)

Publication Number Publication Date
CN109411464A true CN109411464A (zh) 2019-03-01

Family

ID=65464821

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201811079007.1A Pending CN109411464A (zh) 2018-09-17 2018-09-17 一种基于快速烧结纳米银焊膏无压互连技术的1200v/50a igbt功率模块

Country Status (1)

Country Link
CN (1) CN109411464A (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110690120A (zh) * 2019-09-27 2020-01-14 天津大学 烧结封装mos芯片双向开关电子模块及其制作方法
WO2021007949A1 (zh) * 2019-07-18 2021-01-21 烟台台芯电子科技有限公司 一种提高igbt模块端子焊接强度的工艺方法
CN115732450A (zh) * 2022-11-18 2023-03-03 南京晟芯半导体有限公司 一种新型功率模块高密度封装结构及其制造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006037145A (ja) * 2004-07-23 2006-02-09 Toda Kogyo Corp Agナノ粒子及びその製造法、Agナノ粒子を含む分散体
CN105336627A (zh) * 2015-10-21 2016-02-17 哈尔滨工业大学 一种脉冲电流低温快速烧结制备高温服役纳米晶接头的方法
CN105489507A (zh) * 2015-12-09 2016-04-13 天津大学 一种igbt芯片与直接覆铜基板的快速烧结连接方法及装置
CN107871675A (zh) * 2017-10-13 2018-04-03 天津大学 一种纳米银焊膏连接裸铜dbc的功率模块制作方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006037145A (ja) * 2004-07-23 2006-02-09 Toda Kogyo Corp Agナノ粒子及びその製造法、Agナノ粒子を含む分散体
CN105336627A (zh) * 2015-10-21 2016-02-17 哈尔滨工业大学 一种脉冲电流低温快速烧结制备高温服役纳米晶接头的方法
CN105489507A (zh) * 2015-12-09 2016-04-13 天津大学 一种igbt芯片与直接覆铜基板的快速烧结连接方法及装置
CN107871675A (zh) * 2017-10-13 2018-04-03 天津大学 一种纳米银焊膏连接裸铜dbc的功率模块制作方法

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
付善灿: "纳米银焊膏无压低温烧结连接方法的绝缘栅双极型晶体管(IGBT)模块封装应用研究", 《中国博士学位论文全文数据库 信息科技辑》 *
唐思熠: "纳米银焊膏低温烧结在IGBT模块制造中的应用", 《中国优秀硕士学位论文全文数据库》 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021007949A1 (zh) * 2019-07-18 2021-01-21 烟台台芯电子科技有限公司 一种提高igbt模块端子焊接强度的工艺方法
CN110690120A (zh) * 2019-09-27 2020-01-14 天津大学 烧结封装mos芯片双向开关电子模块及其制作方法
CN115732450A (zh) * 2022-11-18 2023-03-03 南京晟芯半导体有限公司 一种新型功率模块高密度封装结构及其制造方法
CN115732450B (zh) * 2022-11-18 2024-01-30 南京晟芯半导体有限公司 一种新型功率模块高密度封装结构及其制造方法

Similar Documents

Publication Publication Date Title
JP5587844B2 (ja) パワー半導体モジュールおよびその製造方法
US9324684B2 (en) Semiconductor device and manufacturing method thereof
CN110854103B (zh) 一种嵌入式双面互连功率模块封装结构和制作方法
US9698078B2 (en) Semiconductor module and method for manufacturing the same
US9627350B2 (en) Method for manufacturing semiconductor device
CN109411464A (zh) 一种基于快速烧结纳米银焊膏无压互连技术的1200v/50a igbt功率模块
US10615131B2 (en) Semiconductor device with high quality and reliability wiring connection, and method for manufacturing the same
CN107910324A (zh) 一种基于纳米银焊膏双面互连碳化硅mos器件的模块化封装方法
CN108461484B (zh) 一种igbt模块的封装结构及加工工艺
CN113130455A (zh) 一种高热可靠性的多单元功率集成模块及其加工工艺
JP2014120639A (ja) パワーモジュール半導体装置
US10475721B2 (en) Power semiconductor device and method for manufacturing same
JP2013077745A (ja) 半導体装置およびその製造方法
JP2014053403A (ja) パワーモジュール半導体装置
CN113838821A (zh) 一种用于SiC平面封装结构的散热件及其制备方法
CN109411372B (zh) 一种基于覆铜陶瓷基板均匀电流辅助烧结纳米银焊膏温度场的方法
CN110571204A (zh) 具有双面散热能力的双向开关功率器件及制作方法
CN113707643A (zh) 一种高集成高可靠igbt功率模块及其制造方法
CN206789535U (zh) 一种电力电子器件的扇出型封装结构
US20240055392A1 (en) Method of manufacturing semiconductor device
CN210575917U (zh) Igbt电路板及igbt模块
CN115732450B (zh) 一种新型功率模块高密度封装结构及其制造方法
CN220556592U (zh) 一种dpim三相整流模块
CN218788371U (zh) 封装模组及电子设备
Rochala et al. Chip-level bonding for microelectronic components by induction sintering of micro structured Ag particles

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20190301

RJ01 Rejection of invention patent application after publication