TWI590395B - 多功率晶片的功率封裝模組及功率晶片單元的製造方法 - Google Patents

多功率晶片的功率封裝模組及功率晶片單元的製造方法 Download PDF

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TWI590395B
TWI590395B TW105121051A TW105121051A TWI590395B TW I590395 B TWI590395 B TW I590395B TW 105121051 A TW105121051 A TW 105121051A TW 105121051 A TW105121051 A TW 105121051A TW I590395 B TWI590395 B TW I590395B
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power
power chip
wafer
substrate
package module
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TW105121051A
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TW201709437A (zh
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王濤
趙振清
魯凱
李鋥
曾劍鴻
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台達電子企業管理（上海）有限公司
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Description

多功率晶片的功率封裝模組及功率晶片單元的製造方法
本發明涉及功率晶片封裝技術領域，尤其涉及多功率晶片的功率封裝模組及功率晶片單元的製造方法。
半導體功率模組的封裝形式種類較多，在工業產品中以密封材料區分，常用的兩種封裝形式分別為矽膠填充(Gel type)和塑封(Molding type)兩種結構。無論是矽膠填充，還是塑封，晶片上表面電極和DBC(Direct Bonded Copper，直接覆銅陶瓷)電路圖形均通過引線(多採用鋁線)鍵合工藝(Wire Bonding)實現模組內部電信號的連接。
晶片貼裝工藝通常採用貼片機(Die Bonder)將晶片從切割好的晶圓(Wafer)上拾取，並將晶片貼裝至DBC基板。在晶片貼裝(Die Bonding)過程中，從採用真空通過吸嘴將晶片拾取，到控制壓力將晶片貼裝至所在DBC基板，其受力和位置均可控，從而確保晶片無損傷及其設計的貼裝位置。其中基板包括導電層(Conductive Trace)和絕緣層(Insulation Layer)，在多個功率晶片貼裝工藝中，由於需要將每顆晶片單獨貼裝至基板上，因此兩顆晶片之間的距離P受單顆晶片貼裝位置偏移量W和導電層之間距離G決定，偏移量W主要需要考 慮連接材料(Die attach)的塗覆偏移、晶片貼裝偏移和基板導電層圖形的精度，受到工藝和基板材料的精度限制。在製作過程中包括共導電層和不共導電層，共導電層是指多顆晶片的設置於同一導電層上，不共導電層是指多顆晶片設置於不同的導電層上。圖1為表示兩個功率晶片(Power Chip)11通過連接材料12貼裝至基板13時晶片不共導電層的截面示意圖，圖中14為導電層，圖2為對應圖1的平面圖，其中偏移量W最小為0.1mm，導電層之間的間距G最小為0.2mm，因此對於晶片底部不共導電層的兩顆晶片之間間距P至少為0.4mm(其中P=2*W+G)。如兩顆晶片底部共用導電層，圖3為表示兩個功率晶片通過晶片連接材料貼裝至基板時晶片共導電層的截面示意圖，圖4為對應圖3的平面圖，為防止晶片接觸，W至少為0.1mm，因此晶片之間的間距P最短不小於0.2mm，(其中P=2*W)。
由上可見，對於多功率晶片構成的功率封裝模組，目前的封裝工藝採用共導電層或不共導電層均難以實現更小的晶片間距。
針對現有技術中存在的問題，本發明提供一種多功率晶片的功率封裝模組及功率晶片單元的製造方法，以解決現有技術中功率晶片的間距難以實現更小的間距導致功率模組的效率降低的技術問題。
為實現上述目的，一方面，本發明提供了一種多功率晶片的功率封裝模組，包括：一功率晶片單元，包括至少兩個並行設置的功率晶片和連接該兩個功率晶片的連接體； 一基板，承載該功率晶片單元，該基板包括一金屬層，該金屬層與該功率晶片單元電性連接；密封層，將安置於基板上的功率晶片單元與周邊環境隔離，實現功率晶片單元的密封；該連接體和該密封層的材料各為不同的絕緣材料，該兩個並行設置的功率晶片之間的間隔小於等於預設寬度，該連接體填充於該間隔之中連接且絕緣該兩個並行設置的功率晶片。
在本發明的一個實施例中，該預設寬度為200微米。
在本發明的另一個實施例中，該連接體的厚度範圍為1/3T~T，其中T為該功率晶片的厚度。
在本發明的另一個實施例中，該連接體的材料硬度為邵氏A10以上，絕緣強度大於10kV/mm，電阻大於1.0E11Ω．cm。
在本發明的另一個實施例中，該連接體中還包含有填料，且該填料的最大粒徑小於該預設寬度。
在本發明的另一個實施例中，該填料的材料為石英、氧化鋁、氫氧化鋁、氧化鋅或氮化硼其中的一種或幾種組合。
在本發明的另一個實施例中，該多功率晶片的功率模組還包括金屬鍵合線，該金屬鍵合線連接該功率晶片和該金屬層。
在本發明的另一個實施例中，該功率晶片單元中兩個功率晶片並聯連接，該連接體的寬度小於和等於該預設寬度以提高該連接體連接的兩個並聯連接功率晶片存在的寄生電感的均勻性。
在本發明的另一個實施例中，該功率晶片單元中兩個功率晶片串聯連接，該連接體的寬度小於和等於該預設寬度以減小該連接體連接的兩個串聯連接功率晶片存在的寄生電感。
在本發明的另一個實施例中，該功率晶片為垂直型功率晶片。
另一方面，本發明還提供了一種功率晶片單元的製造方法，該功率晶片單元包括至少兩個並行設置的功率晶片，該製造方法包括：提供一包括若干呈陣列擺佈功率晶片的晶圓；將該晶圓的一面鋪上一襯面後，切割該晶圓的另一面形成功率晶片與功率晶片之間的間隔；在該晶圓的另一面塗覆連接體，使該連接體填充入該功率晶片與功率晶片之間的間隔；切割該晶圓中部分連接體而分離出若干獨立的功率晶片單元，該功率晶片單元中的功率晶片由該連接體連接。
在本發明的一個實施例中，該功率晶片與功率晶片之間的間隔小於預設寬度。
在本發明的另一個實施例中，該預設寬度小於等於200微米。
在本發明的另一個實施例中，該連接體的材料硬度為邵氏A10以上，絕緣強度大於10kV/mm，電阻大於1.0E11Ω．cm。
本發明的有益效果在於，在晶圓處理過程中，通過在並列設置的兩個功率晶片的間隔中填充連接體，完成晶片之間的絕緣連接，實現晶片與晶片之間的近距離連接。在半導體功率模組的封裝中，可將多個功率晶片進行一次貼裝，提高晶片的貼裝效率。同時由於晶片之間的間距縮短，減小功率晶片之間的寄生電感，降低晶片的最大結溫，能夠降低功率晶片的損耗和電壓應力，從而提高功率封裝模組的效率和可靠性。
11‧‧‧功率晶片
12‧‧‧連接材料
13‧‧‧基板
14‧‧‧導電層
101‧‧‧DBC基板
102‧‧‧導電層
103‧‧‧晶片
104‧‧‧焊料
105‧‧‧引線
106‧‧‧電極端子
107‧‧‧柵極信號端子
108‧‧‧矽膠
109‧‧‧塑膠外殼
131‧‧‧功率晶片
132‧‧‧連接體
133‧‧‧基板
134‧‧‧密封層
135‧‧‧連接材料
151‧‧‧基板
153‧‧‧晶片
154‧‧‧連接材料
155‧‧‧引線
156‧‧‧連接體
161‧‧‧基板
162‧‧‧導電層
164‧‧‧連接材料
166‧‧‧連接體
173‧‧‧晶片
201‧‧‧基板
202‧‧‧導電層
202a‧‧‧共襯底
203‧‧‧晶片
204‧‧‧連接材料
205‧‧‧金屬橋
206‧‧‧連接體
207‧‧‧金屬鍵合線
252‧‧‧導電層
253‧‧‧晶片
254‧‧‧連接材料
255‧‧‧導電球
256‧‧‧連接體
312‧‧‧導電層
313‧‧‧晶片
314‧‧‧連接材料
316‧‧‧連接體
317‧‧‧導電柱
A‧‧‧背面
D‧‧‧導電端
D1、D2‧‧‧漏極
G‧‧‧導電端
G1、G2‧‧‧晶片柵極
Ld1+Ls1‧‧‧功率晶片T1兩端漏極(D1)和源極(S1)導電連接的寄生電感
Ld2+Ls2‧‧‧功率晶片T2兩端漏極(D2)和源極(S2)導電連接的寄生電感
Lg1、Lg2‧‧‧晶片柵極(G1/G2)至柵極驅動之間的寄生電感
P‧‧‧間距
Rd1、Rd2‧‧‧
S‧‧‧導電層
S1、S2‧‧‧源極
S11~S14‧‧‧步驟
t‧‧‧厚度
T‧‧‧功率晶片的厚度
T1、T2、T3、T4‧‧‧功率晶片
Vbus+‧‧‧導電端
Vbus-‧‧‧導電端
圖1為現有技術中兩個功率晶片通過晶片連接材料貼裝至基板時晶片不共導電層的截面示意圖。
圖2為現有技術中圖1結構的平面圖。
圖3為現有技術中兩個功率晶片通過晶片連接材料貼裝至基板時晶片共導電層的截面示意圖。
圖4為現有技術中圖3結構的平面圖。
圖5為典型矽膠填充的半導體功率模組結構示意圖。
圖6為典型塑封的半導體功率模組結構示意圖。
圖7為兩個功率晶片並聯結構拓撲示意圖。
圖8為兩個功率晶片半橋結構拓撲示意圖。
圖9為帶有寄生參數的並聯結構的拓撲示意圖。
圖10為採用引線鍵合方式的並聯結構的封裝結構示意圖。
圖11為帶有寄生參數的半橋結構的拓撲示意圖。
圖12為採用引線鍵合方式的半橋結構的封裝結構示意圖。
圖13為本發明實施例一提供的一種多功率晶片的功率封裝模組的結構示意圖。
圖14為本發明實施例一中功率晶片單元的結構示意圖。
圖15為本發明實施例二中採用金屬鍵合線的方式實現不共襯底的串聯晶片封裝模組的結構示意圖。
圖16為本發明實施例三中採用金屬鍵合線的方式實現不共襯底的並聯結構的晶片封裝模組的結構示意圖。
圖17為本發明實施例三中採用金屬鍵合線的方式實現共襯底的並聯結構的晶片封裝模組的結構示意圖。
圖18為本發明實施例三中採用金屬鍵合線的方式實現共D襯底的並聯晶片封裝模組的結構示意圖。
圖19為本發明實施例三中採用金屬鍵合線的方式實現共S襯底的並聯晶片封裝模組的結構示意圖。
圖20為本發明實施例四中採用金屬橋的方式實現不共襯底的半橋結構晶片封裝模組的結構示意圖。
圖21為本發明實施例四中採用金屬橋的方式實現不共襯底的並聯結構晶片封裝模組的結構示意圖。
圖22為本發明實施例四中採用金屬橋的方式實現共襯底的並聯結構晶片封裝模組的結構示意圖。
圖23為本發明實施例四中採用金屬橋的方式實現共D襯底的並聯結構晶片封裝模組的結構示意圖。
圖24為本發明實施例四中採用金屬橋的方式實現共S襯底的並聯結構晶片封裝模組的結構示意圖。
圖25為本發明實施例五中採用晶片倒裝工藝的半橋結構的晶片封裝模組的結構示意圖。
圖26為本發明實施例五中採用晶片倒裝工藝的並聯結構的晶片封裝模組的結構示意圖。
圖27為本發明實施例五中採用含有導電球的晶片倒裝工藝的半橋結構的晶片封裝模組的結構示意圖。
圖28為本發明實施例五中採用含有導電球的晶片倒裝工藝的並聯結構的晶片封裝模組的結構示意圖。
圖29為本發明實施例五中採用含有導電柱的晶片倒裝工藝的半橋結構的晶片封裝模組的結構示意圖。
圖30為本發明實施例五中採用含有導電柱的晶片倒裝工藝的並聯結構的晶片封裝模組的結構示意圖。
圖31為本發明實施例五中對應圖29的半橋結構的封裝模組主回路截面示意圖。
圖32為本發明實施例六中提供的一種功率晶片單元的製造方法的步驟流程圖。
圖33為本發明實施例六中提供的對晶圓的後道處理工藝的流程圖。
圖34為採用圖33的工藝流程得到具有三個功率晶片的功率晶片單元切割時的示意圖。
體現本發明特徵與優點的典型實施例將在以下的說明中詳細敘述。應理解的是，本發明能夠在不同的實施例上具有各種的變化，其皆不脫離本發明的範圍，且其中的說明及圖式在本質上是當作說明之用，而非用以限制本發明。
矽膠填充的半導體功率模組結構如圖5所示，DBC基板101的第一表面和第二表面均設置有金屬層，並對DBC基板101第一表面的金屬層進行刻蝕形成電路圖形(也就是導電層)102，同時DBC基板101還作為晶片103的連接基板，採用焊料(也即是連接材料)104將晶片103整個底面完全焊接至DBC基板101的導電層102上。晶片103上表面電極和導電層102通過引線105(多採用鋁線)鍵合工藝(Wire Bonding)實現模組內部電信號的連接。再通過焊料 104將電極端子(Power terminal)106和柵極信號端子(Gate Terminal)107焊接至DBC基板101上，實現功率模組與外部電路的電連接。由於半導體功率晶片容易受濕氣、離子、粉塵的影響，採用矽膠(Silicone gel)108對其進行封裝和保護。同時還為保證電極端子的結構穩定，一般安裝塑膠外殼(Plastic Housing)109對其進行機械支撐，塑膠外殼形成在DBC基板的第一表面上，也就是DBC基板與其第二表面的金屬層是裸露在外面的。
而典型的塑封的半導體功率模組結構如圖6所示，與圖5中的結構相比，包括DCB基板101、導電層102、晶片103、焊料104、引線105、電極端子106以及柵極信號端子107均同於圖5，另外除了密封材料不同之外(圖6中填充塑封材料109)，其電極端子並非採用獨立端子，一般採用一體的引線框架，焊接至DBC基板101上進行電信號的連接，引線框架之間的連接部分在功率模組封裝完成後，進行切斷和折彎處理。由於塑封材料為環氧類材料，能與其他封裝材料良好連接，同時具備較高的機械強度，能可靠地固定端子。
以上是對封裝不同的兩種功率模組的結構進行介紹，如果以實現不同功能拓撲結構劃分，一般分為並聯結構和半橋結構兩種封裝模組。功率晶片的通流能力會受晶片工藝、散熱等限制，如需應用于更高的功率等級或電流等級，會考慮將多個功率晶片並聯使用，兩個功率晶片並聯結構拓撲示意圖如圖7所示，兩個功率晶片T1和T2的源極S和漏極D並聯，半橋結構拓撲示意圖如圖8所示，所謂「半橋結構」其實質上就是兩個功率晶片串聯，參見圖8，T1的源極S連接T2的漏極D，而T1的漏電極D連接一導電層Vbus+，T2的源電極S連接另一導電層Vbus-。
功率封裝模組中，考慮到電氣連接的路徑，圖1的矽膠填充和圖3的塑封兩種封裝結構中，均是利用鋁線與DCB基板第一表面的導電層連接，這樣就會產生寄生參數。帶有寄生參數的並聯結構的拓撲圖如圖9所示，以兩 個晶片並聯為例，晶片T1的主要寄生參數包括Lg1、Ld1、Ls1等，晶片T2的主要寄生參數包括Lg2、Ld2、Ls2等，其中Lg1/Lg2為晶片柵極(G1/G2)至柵極驅動之間的寄生電感，分別影響晶片T1和T2的開關速度，當Lg1與Lg2不同時，將引起T1，T2晶片開關速度不同，開關損耗不同；(Ld1+Ls1)/(Ld2+Ls2)分別為T1，T2兩端漏極(D1/D2)和源極(S1/S2)導電連接的寄生電感，包括鋁線和部分基板上的導電層，將分別影響T1和T2開通瞬間的電流分佈，Ld1+Ls1與Ld2+Ls2不相等時，將導致晶片不均流，差異越大，開通瞬間電流差異越大，損耗也越大，溫度差異也越大，造成晶片最大結溫上升。以上寄生參數由於晶片佈局的關係，將導致T1，T2晶片的寄生參數不同。採用引線鍵合方式的並聯結構的封裝結構示意圖如圖10所示，包括基板101、導電層102、晶片103、焊料104以及引線105，且D1、D2均連接至獨立的導電層D，G1、G2均連接至獨立的導電層G，S1、S2均連接至獨立的導電層S。通過T1,T2寄生參數分析發現，影響寄生參數的一個因素為並聯晶片之間的間距，如縮短其間距，將減小並聯晶片之間的封裝寄生參數Lg1與Lg2、以及Ld1+Ls1與Ld2+Ls2的差別，能更好地平衡並聯晶片的電流分佈並降低其損耗，從而提高效率，降低晶片最大結溫。其中晶片的最大結溫是指晶片在工作過程中結溫的最大值。
帶有寄生參數的半橋模組結構的拓撲圖如圖11所示，以平面型功率晶片為例，晶片T1的主要寄生參數包括Lg1、Ld1、Ls1等，晶片T2的主要寄生參數包括Lg2、Ld2、Ls2等，其中對應主電路上(Ld1+Ls1)/(Ld2+Ls2)分別為T1，T2兩端漏極(D1/D2)和源極(S1/S2)導電連接的寄生電感，包括鋁線和部分基板上的導電層。其中，減小Ls1+Ld2將降低T2的電壓應力，減小Ls1可提高T1的開關速率，降低其損耗。
採用引線鍵合方式的半橋結構的封裝結構示意圖如圖12所示，包括基板101、導電層102、晶片103、焊料104以及引線105。其中導電層102包 括多個獨立的導電端，例如Vbus+、Vbus-、G1、S1、G2和S2等導電端。圖12中T2的S2連接至獨立的導電端Vbus-及導電端S2，T2的G2連接至獨立的導電端G2，T2的D2以及T1的S1連接至獨立的導電端Phase，T1的S1還連接至獨立的導電端S1，T1的G1連接至獨立的導電端G1，T1的D1連接至獨立的導電端Vbus+。從圖12所示的採用引線鍵合方式的半橋模組的封裝結構示意圖中可以發現，Ls1+Ld2主要受T1源極S1和T2漏極D1之間的電氣連接路徑影響，如縮短T1和T2間距，可減小Ls1和Ld2，降低T2的電壓應力並提高T1的開關速度，提高晶片可靠性和效率。
綜上，基於對功率模組電氣特性的分析，傳統的功率半導體常受到寄生電感的影響，而於功率半導體內產生較大的電壓尖峰，嚴重影響功率半導體乃至於整體電力電子裝置的性能。如能提供一種新的晶片處理工藝和封裝結構，以減小晶片之間的間距，就多晶片並聯結構的封裝模組而言，可使並聯晶片的電流分佈更均勻並降低其損耗，從而提高效率，降低晶片最大結溫；對於半橋結構的封裝模組而言，可降低回路的寄生電感，從而提高晶片可靠性和效率。
實施例一
本實施例提供了一種多功率晶片的功率封裝模組，結構示意圖如圖13所示，包括：一功率晶片單元，包括至少兩個並行設置的功率晶片131和連接兩個功率晶片131的連接體132；一基板133，承載功率晶片單元，基板包括一金屬層(圖中未示出)，金屬層與功率晶片單元電性連接；密封層134，塑封基板133表面以將功率晶片單元與周邊環境隔離； 連接體132和密封層134的材料各為不同的絕緣材料，兩個並行設置的功率晶片T1和T2之間的間隔小於等於預設寬度，連接體132填充於間隔之中連接且絕緣兩個並行設置的功率晶片T1和T2。
其中功率晶片單元的結構示意圖如圖14所示，本實施例中是以功率晶片單元中包括兩個功率晶片T1和T2為例，在實際應用中可以根據需要選擇多個功率晶片，並通過連接體的連接構成具有多個功率晶片的功率晶片單元，在貼裝過程中就可以一次貼裝工藝完成多個晶片的貼裝，可以提高貼裝的效率，同時晶片間距不受貼裝工藝的影響，可以做到很小的晶片間距。兩個晶片之間的間距P主要受晶圓切割工藝限制，一般切割工藝包括使用刀片進行機械切割，激光切割等，將晶圓切割成相互隔開的單顆晶片的切割刀寬度即為晶片之間可實現的間距，目前以上技術的切割寬度至多不超過200微米，因此本實施例中的預設寬度為200微米。
一般地，晶片間隔中的連接體132的熱膨脹係數高於晶片材料的膨脹係數，由於晶片工作時發熱，同時絕緣性質的連接體與晶片材料熱膨脹係數不匹配，使連接體產生熱應力，疊加由於晶片和基板熱膨脹係數不匹配導致晶片連接層的熱應力，使晶片間隔中的連接體更易失效，尤其對於採用矽膠密封的模組風險更大。可通過降低連接體的厚度來減小晶片連接的熱應力，同時還需要連接體具備一定厚度，起到良好連接晶片的作用，因此要求連接體132的厚度t的範圍為1/3T~T，其中T為功率晶片的厚度，參見圖14所示。通常可通過晶圓後道處理工藝中的晶圓切割工藝，在晶片之間連接體的位置處，通過調整機械切割的刀片高度，對絕緣連接材料進行部分切割，以控制連接體的厚度。
考慮連接體能夠粘接晶片，需要一定的機械強度，同時能夠填充在片之間的切割槽中，需要良好的流動性和填縫性，另外，能實現平面型晶 片襯底之間的絕緣。連接體可以為有機矽類樹脂粘接材料，包括純樹脂為基材的有機矽粘接膠，環氧改性有機矽粘接膠，酚醛改性有機矽粘接膠等；還可以是單組份或者雙組份的硫化矽橡膠等；還可以為環氧樹脂等，其成分中可加入填料以調整其物理特性。具體而言，要求連接體的材料硬度為邵氏A10以上，絕緣強度大於10kV/mm，體積電阻大於1.0E11Ω．cm，同時還要保證連接體與功率晶片的粘接強度大於100Pa。連接體的內部還可以含有填料，如含有填料，要求填料的最大粒徑小於預設寬度。填料可為石英，氧化鋁，氫氧化鋁，氧化鋅，氮化硼其中的一種或幾種組合，能通過1000倍以下顯微鏡觀察到填料的存在。
其中功率晶片131可以是平面型晶片，平面型晶片包括平面型IGBT(Insulated-Gate Bipolar Transistor，絕緣柵雙極型晶體管)，MOSFET(Metal-Oxide Semiconductor Field Effect Transistor，金氧半場效晶體管)，二極管等，也包括驅動功率晶片的Driver IC晶片和實現晶片開關控制策略的Control IC，其材料可以為Si，SiC，GaN等。另外，功率晶片還可以由Dirver IC晶片或control IC晶片與前述單一功率晶片集成，或者由Driver IC,control IC，前述單一功率晶片集成。同樣地，本實施例的結構也能夠很好的適用于並聯結構的垂直型開關晶片。
基板133包括PCB(Printed Circuit Board，印刷電路板)、LF(Lead-frame，引線框)、DBC(Direct Bonding Copper，直接覆銅陶瓷)基板、DBA(Direct Bonding Aluminum，直接覆鋁)基板、金屬共燒陶瓷基板和IMS(Insulated Metal Substrate，金屬絕緣基板)基板、金屬或金屬複合基板(如銅、鋁、鋁碳化矽)、陶瓷(如Al2O3，AlN，BeO，Si3N4等，這四種均稱作陶瓷)絕緣基板等。
參見圖13中，功率晶片131與DCB基板133之間還有連接材料135，通過連接材料135將功率晶片安裝在基板上，連接材料135可以是焊料，金屬間化合物(IMC，Intermetalic Compound)，也可以包括低溫燒結材料(如銀、銅焊膏等可在低溫下進行燒結實現晶片與基板之間互聯的材料)、導電銀膠等導電連接材料，也可以為有機矽類、或環氧類絕緣粘接材料，因此連接材料可以是導電的，也可以是絕緣的，需要根據具體的應用環境進行選擇。
功率封裝模組中還需要包括密封層134，用於包覆功率晶片與連接體構成的功率晶片單元以及基板的表面，使其與周圍環境隔離，密封層一般包括矽凝膠、矽橡膠、環氧類塑封材料等，但與功率晶片間隔中的連接體的成分或特性有所不同。
參見圖10和12，基板上通常還設置有一層金屬層(圖13和圖14中未示出)，功率晶片與基板之間就通過這一層金屬層進行電性連接。進一步的，多功率晶片的功率模組還包括金屬鍵合線，用於連接功率晶片和金屬層，其中金屬鍵合線的材料可以為Al，Cu，Au等。
綜上所述，本實施提供的多功率晶片的功率封裝模組通過在並列設置的兩個功率晶片的間隔中填充連接體，完成晶片之間的絕緣連接，實現晶片與晶片之間的近距離連接。在半導體功率模組的封裝中，可將多個功率晶片進行一次貼裝，提高晶片的貼裝效率。同時由於晶片之間的間距縮短，減小功率晶片之間的寄生電感，降低晶片的最大結溫，能夠降低功率晶片的損耗和電壓應力，從而提高功率封裝模組的效率和可靠性。
實施例二
基於上述實施例一中通過金屬鍵合線連接功率晶片和金屬層，本實施例中也提供了一種多功率晶片的功率封裝模組，其中的功率晶片單元中 兩個功率晶片串聯連接，而且並行設置的晶片間隔中的連接體的寬度小於等於預設寬度以減小連接體連接的兩個串聯連接功率晶片存在的寄生電感。
對於採用金屬鍵合線的方式實現串聯晶片封裝模組的結構示意圖如圖15所示，兩個功率晶片為平面型功率晶片，可通過實施例一中所述的設置在晶片153底部的連接材料154將其貼裝至基板151(基板為絕緣材料)上，晶片為不共襯底(不共襯底是指多個晶片的襯底沒有電氣連接)，即晶片的底部直接通過絕緣的連接材料154貼至基板上，沒有導電層，處於懸浮狀態，其表面電氣連接可通過引線155鍵合(Wire bonding)工藝實現。具體引線鍵合的連線實施方案為：晶片T1的漏極D1連接至導電層(圖15中Vbus+端)；晶片T1的源極S1和T2的漏極D2之間直接通過引線連接；晶片T2的源極S2連接至導電層(圖15中Vbus-端)；分別從T1的S1和T2的D2連接至導電層(圖15中phase端)；T1，T2的柵極G1/G2和源極S1/S2的信號端分別連接至獨立的導電層上，晶片T1和T2之間為填充的連接體156。
本實施例中，由於T1的源極S1和T2的漏極D2之間直接電氣連接，且晶片間距短，故連接的路徑變短，減小前述半橋拓撲結構中的寄生參數Ls1和Ld2，從而提高半橋模組的效率和可靠性。
實施例三
基於上述實施例一中通過金屬鍵合線連接功率晶片和金屬層，本實施例中也提供了一種多功率晶片的功率封裝模組，其中的功率晶片單元中兩個功率晶片並聯連接，而且並聯的晶片間隔中的連接體的寬度小於和等於預設寬度以提高連接體連接的兩個並聯連接功率晶片存在的寄生電感的均勻性。
對於採用金屬鍵合線的方式實現並聯晶片封裝模組的結構示意圖如圖16所示，兩個功率晶片可通過實施例一中所述的設置在晶片173底部的連接材料164將其貼裝至基板161(基板為絕緣材料)上，晶片之間通過連接體 166連接，晶片是不共襯底(不共襯底是指多個晶片的襯底沒有電氣連接)，即晶片的底部直接通過連接材料164貼至基板上，沒有導電層，處於懸浮狀態，其表面電氣連接可通過引線鍵合(Wire bonding)工藝實現。具體引線鍵合的連線實施方案為：T1和T2的漏極D1，D2連接至導電層中的導電端(圖16中D端)；T1和T2的源極S1，S2連接至導電層(圖中S端)；T1和T2的柵極G1，G2連接至導電層中的導電端(圖中G端)。
與圖16不同，本實施例中還提供了三種共襯底的並聯晶片封裝模組，結構示意圖分別如圖17、18和19所示，圖17中，並聯晶片底部採用連接材料連接至基板上獨立的導電層162，導電層162處於懸浮狀態；圖18中，並聯晶片底部採用連接材料連接至基板導電層的D端(也就是D端作為導電層162)；圖19中，並聯晶片底部採用連接材料連接至基板導電層的S端(即S端作為導電層162)。
本實施例中，由於晶片之間間距小，減小並聯晶片之間的封裝寄生參數的差別，更好地平衡並聯晶片的電流分佈並降低其損耗，從而降低晶片最大結溫，提高效率。
實施例四
基於上述實施例二和三，可以通過金屬鍵合線實現晶片與金屬層的電氣連接，由於金屬引線的截面積小，其寄生參數仍較大，因此本實施例中還可以通過金屬橋實現晶片與金屬層的電氣連接。
半橋結構的功率封裝模組的結構示意圖如圖20，包括基板201、導電層202、晶片203、連接材料204以及晶片之間的連接體206，半橋模組中可將T1晶片的漏極D1與第一導電層Vbus+端之間、T1的源極S1與T2的漏極D2之間、T2的源極S2與第二導電層Vbus-端之間採用金屬橋205連接方式。該金屬橋材料可以為Al,Cu,Ag,Au等，採用的連接工藝為超聲連接(Ultrasonic bonding)，金屬擴散連接(Metal-metal diffusion bonding)，焊接等，其餘連接線路仍採用金屬鍵合線207或金屬橋205的連接方法。
與上述實施例二相同，採用金屬橋連接的半橋結構的功率封裝模組仍然分為不共襯底和共襯底兩類結構，其中圖20為不共襯底的半橋結構的功率封裝模組的結構示意圖。當然除了圖20中不共襯底的結構，還可以是共襯底結構，可以是共襯底懸浮狀態、或者是共襯底接Vbus-，還或者是共襯底接phase。
並聯結構的功率封裝模組的結構示意圖如圖21-24所示，採用金屬橋的方式實現T1/T2的漏極D1/D2與導電線路的D端之間連接，T1/T2的源極S1/S2與導電線路的S端之間連接，其中圖21為不共襯底的並聯結構的功率封裝模組的結構示意圖，圖22為共襯底(懸浮狀態)的並聯結構的功率封裝模組的結構示意圖，圖23為共襯底(與D端共襯底)的並聯結構的功率封裝模組的結構示意圖，即D端作為共襯底202a，圖24為共襯底(與S端共襯底)的並聯結構的功率封裝模組的結構示意圖，即S端作為共襯底202a。
本實施例中，不論是對於半橋結構而言，還是對於並聯結構而言，採用金屬橋的方式實現晶片與金屬層的電氣連接，能夠增大電氣連接的截面積，進一步減小寄生參數。
實施例五
基於上述實施例四，可以通過金屬橋實現晶片與金屬層的電氣連接，由於金屬橋在進行連接時需要折彎，導致導電路徑較長，相應回路寄生參數仍較大，本實施例中考慮通過晶片倒裝(Flip-chip)工藝能夠縮短電氣路徑。 如果不考慮晶片襯底連接方式(當然，後續實施例中，晶片襯底連接方式仍包括前述不共襯底和共襯底兩類結構)，圖25和26中為使用連接材料將晶片表面貼裝至基板的導電層，實現半橋模組和並聯模組的電氣連接，其中連接材料需為 前面實施例一該導電的連接材料。當晶片G，S，D電極間距較近，採用該方案可能會導致晶片不同電極之間連接材料發生互聯，造成短路。因此，本實施例中在採用晶片倒裝技術的基礎上，還要採用導電球或導電柱將導電層和晶片電極隔開，減小電極短路的風險，圖中包括導電層252、晶片253、連接材料254以及晶片之間的連接體256。
使用導電球將晶片表面貼裝至基板的導電層，實現半橋模組和並聯晶片模組的電氣連接的結構示意圖分別如圖27和28所示，其中圖27和圖28中導電球用255表示，材料可以為焊料，Cu，Au，Ag，或其他合金等。一般地，導電球需採用前述導電的連接材料實現導電球與基板導電層和晶片表面的機械和電氣連接。
使用導電柱將晶片表面貼裝至基板的導電層，實現半橋模組和並聯晶片模組的電氣連接的電氣連接的結構示意圖分別如圖29和30所示，其中導電柱可以為焊料，Cu，Au，Ag，或其他合金等。一般地，導電柱同樣需要採用前述導電晶片連接材料將晶片不同極連接至基板的導電層。金屬導電柱也可通過電鍍工藝在晶片上表面S，D，G端長出導電柱，圖29和30中的導電柱用277表示，實現導電柱和晶片表面金屬層的連接，導電層也可通過電鍍金屬的方式生長而成，最後通過刻蝕技術，形成導電層的圖形。對於圖29的半橋結構的封裝模組主回路截面示意圖如示意如圖31所示，導電柱一般為圓柱狀或倒圓錐狀，圖31中包括導電層312、晶片313、連接材料314、晶片之間的連接體316以及倒圓錐狀的導電柱317。其中導電柱317和導電層312可以為同一導電材質，也可為不同導電材質。
本實施例中，採用晶片倒裝工藝，並結合導電球或導電柱，可以進一步減小回路寄生參數。
實施例六
本實施例還提供了一種功率晶片單元的製造方法，該功率晶片單元包括至少兩個並行設置的功率晶片，該製造方法的步驟流程如圖32所示，包括以下步驟：步驟S11、提供一包括若干呈陣列擺佈功率晶片的晶圓；步驟S12、將晶圓的一面鋪上一襯面後，切割晶圓的另一面形成功率晶片與功率晶片之間的間隔；步驟S13、在晶圓的另一面塗覆連接體，使連接體填充入功率晶片與功率晶片之間的間隔；步驟S14、切割晶圓中部分連接體而分離出若干獨立的功率晶片單元，功率晶片單元中的功率晶片由連接體連接。
其中功率晶片與功率晶片之間的間隔小於預設寬度，本實施例中優選的預設寬度小於等於200微米。同時，對於晶片間隔中的連接體的材料和性能有一定的要求，具體的，連接體的材料硬度為邵氏A10以上，絕緣強度大於10kV/mm，電阻大於1.0E11Ω．cm。另外，連接體的材質雖然也是絕緣材質，但是卻與傳統的封裝功率晶片單元的密封層的成分或特性是有所不同的。 密封層的材料一般是矽凝膠、矽橡膠、環氧類塑封材料等，而連接體可以是有機矽類樹脂粘接材料，包括純樹脂為基材的有機矽粘接膠，環氧改性有機矽粘接膠，酚醛改性有機矽粘接膠等；還可以是單組份或者雙組份的硫化矽橡膠等；還可以為環氧樹脂等，其成分中可加入填料以調整其物理特性。當連接體中含有填料時，需要滿足填料的最大粒徑小於預設寬度。
在進行上述步驟之前還包括對晶片進行晶圓製造的前道工藝，即完成晶片上表面電路金屬化以後，再進行本實施例的晶圓後道處理工藝，實現多個晶片之間的絕緣，以及晶片之間的近距離連接。基於上述，對晶圓的後道處理工藝的流程圖如圖33所示，包括：第一步，先將晶圓331金屬化面貼至 藍膜或UV膜332上；第二步，將晶圓331的背面(圖中用A表示)即襯底朝上，從晶圓的背面(即襯底)，切割刀沿切割槽將晶圓331進行切割，使晶圓上的各平面型晶片獨立，如圖中所示，以晶圓上的四個功率晶片為例，四個功率晶片T1,T2,T3,T4相互隔開；第三步，將流動的連接體333(具有粘接性的絕緣物質)填入切割槽中，填入的方法可以為點膠、旋轉塗覆等，填入的連接體流入到切割槽中，待填充完全後進行固化處理；第四步，將晶圓襯底進行減薄，處理至需要的厚度；第五步，去除上表面，即金屬化面的藍膜，並將晶圓襯底(即A面)貼至藍膜334上，如果平面型晶片襯底連接選擇焊接或燒結等晶片連接工藝，可在晶圓襯底進行表面金屬化處理；第六步，按照封裝需求進行切割，如封裝需要兩顆晶片同時貼裝，則每隔兩顆晶片進行切割。以上晶圓後道處理工藝不僅限於製備兩個功率晶片的連接，亦可用於製備兩顆以上連接的多個功率晶片連接，例如還可以是功率晶片單元中包括三個功率晶片，則切割時的示意圖如圖34所示。
本實施例提供的製造方法，在晶圓處理過程中，通過在並列設置的兩個功率晶片的間隔中填充連接體，相比于傳統工藝中一個一個的貼裝晶片，能夠縮短晶片的間距，通過連接體完成晶片之間的絕緣連接，實現晶片與晶片之間的近距離連接。在半導體功率模組的封裝中，可將多個功率晶片進行一次貼裝，提高晶片的貼裝效率。同時由於晶片之間的間距縮短，減小並行設置的串聯功率晶片之間的寄生電感，降低晶片的最大結溫，利於降低功率晶片的損耗和電壓應力，提高功率封裝模組的效率和可靠性。
本領域技術人員應當意識到在不脫離本發明所附的申請專利範圍所公開的本發明的範圍和精神的情況下所作的更動與潤飾，均屬本發明的申請專利範圍的保護範圍之內。
131‧‧‧功率晶片
132‧‧‧連接體
133‧‧‧基板
134‧‧‧密封層
135‧‧‧連接材料

Claims (14)

  1. 一種多功率晶片的功率封裝模組，其特徵在於，包括：一功率晶片單元，包括至少兩個並行設置的功率晶片和連接該兩個功率晶片的連接體；一基板，承載該功率晶片單元，該基板包括一金屬層，該金屬層與該功率晶片單元電性連接；以及密封層，將安置於該基板上的該功率晶片單元與周邊環境隔離，實現該功率晶片單元的密封；該連接體和該密封層的材料各為不同的絕緣材料，該兩個並行設置的功率晶片之間的間隔小於等於預設寬度，該連接體填充於該間隔之中連接且絕緣該兩個並行設置的功率晶片。
  2. 根據申請專利範圍第1項所述之多功率晶片的功率封裝模組，其特徵在於，該預設寬度為200微米。
  3. 根據申請專利範圍第1項所述之多功率晶片的功率封裝模組，其特徵在於，該連接體的厚度範圍為1/3T~T，其中T為該功率晶片的厚度。
  4. 根據申請專利範圍第1項所述之多功率晶片的功率封裝模組，其特徵在於，該連接體的材料硬度為邵氏A10以上，絕緣強度大於10kV/mm，電阻大於1.0E11Ω．cm。
  5. 根據申請專利範圍第4項所述之多功率晶片的功率封裝模組，其特徵在於，該連接體中還包含有填料，且該填料的最大粒徑小於該預設寬度。
  6. 根據申請專利範圍第5項所述之多功率晶片的功率封裝模組，其特徵在於，該填料的材料為石英、氧化鋁、氫氧化鋁、氧化鋅或氮化硼其中的一種或幾種組合。
  7. 根據申請專利範圍第1項所述之多功率晶片的功率封裝模組，其特徵在於，該多功率晶片的功率模組還包括金屬鍵合線，該金屬鍵合線連接該功率晶片和該金屬層。
  8. 根據申請專利範圍第1項所述之多功率晶片的功率封裝模組，其特徵在於，該功率晶片單元中兩個功率晶片並聯連接，該連接體的寬度小於等於該預設寬度以提高該連接體連接的兩個並聯連接功率晶片存在的寄生電感的均勻性。
  9. 根據申請專利範圍第1項所述之多功率晶片的功率封裝模組，其特徵在於，該功率晶片單元中兩個功率晶片串聯連接，該連接體的寬度小於和等於該預設寬度以減小該連接體連接的兩個串聯連接功率晶片存在的寄生電感。
  10. 根據申請專利範圍第1項所述之多功率晶片的功率封裝模組，其特徵在於，該功率晶片為垂直型功率晶片。
  11. 一種功率晶片單元的製造方法，其特徵在於，該功率晶片單元包括至少兩個並行設置的功率晶片，該功率晶片單元製造方法包括：提供一包括若干呈陣列擺佈功率晶片的晶圓；將該晶圓的一面鋪上一襯面後，切割該晶圓的另一面形成功率晶片與功率晶片之間的間隔；在該晶圓的另一面塗覆連接體，使該連接體填充入該功率晶片與功率晶片之間的間隔；以及切割該晶圓中部分連接體而分離出若干獨立的功率晶片單元，該功率晶片單元中的功率晶片由該連接體連接。
  12. 根據申請專利範圍第11項所述之功率晶片單元的製造方法，其特徵在於，該功率晶片與功率晶片之間的間隔小於預設寬度。
  13. 根據申請專利範圍第12項所述之功率晶片單元的製造方法，其特徵在於，該預設寬度小於等於200微米。
  14. 根據申請專利範圍第11項所述之功率晶片單元的製造方法，其特徵在於，該連接體的材料硬度為邵氏A10以上，絕緣強度大於10kV/mm，電阻大於1.0E11Ω．cm。
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