CN106486458A - 多功率芯片的功率封装模块及功率芯片单元的制造方法 - Google Patents

多功率芯片的功率封装模块及功率芯片单元的制造方法 Download PDF

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CN106486458A
CN106486458A CN201510548984.1A CN201510548984A CN106486458A CN 106486458 A CN106486458 A CN 106486458A CN 201510548984 A CN201510548984 A CN 201510548984A CN 106486458 A CN106486458 A CN 106486458A
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China
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power
chip
power chip
connector
chips
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CN201510548984.1A
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CN106486458B (zh
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王涛
赵振清
鲁凯
李锃
曾剑鸿
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Delta Electronics Shanghai Co Ltd
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Delta Electronics Shanghai Co Ltd
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Priority to CN201510548984.1A priority Critical patent/CN106486458B/zh
Priority to TW105121051A priority patent/TWI590395B/zh
Priority to US15/230,670 priority patent/US10347533B2/en
Publication of CN106486458A publication Critical patent/CN106486458A/zh
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Publication of CN106486458B publication Critical patent/CN106486458B/zh
Priority to US16/428,231 priority patent/US20190287943A1/en
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Abstract

本发明公开了多功率芯片的功率封装模块及功率芯片单元的制造方法，多功率芯片的功率封装模块包括功率芯片单元，包括至少两个并行设置的功率芯片和连接两个功率芯片的连接体；基板，承载功率芯片单元，基板包括金属层，金属层与功率芯片单元电性连接；密封层，将安置于基板上的功率芯片单元与周边环境隔离，实现功率芯片单元的密封；连接体和密封层的材料各为不同的绝缘材料，两个并行设置的功率芯片之间的间隔小于等于预设宽度，连接体填充于间隔之中连接且绝缘两个并行设置的功率芯片。在封装过程中可以一次贴装多个芯片，提高贴装效率，而且缩短功率芯片间距，减小功率芯片之间的寄生电感，利于降低芯片的最大结温，提高功率封装模块的可靠性。

Description

多功率芯片的功率封装模块及功率芯片单元的制造方法
技术领域
本发明涉及功率芯片封装技术领域，尤其涉及多功率芯片的功率封装模块及功率芯片单元的制造方法。
背景技术
半导体功率模块的封装形式种类较多，在工业产品中以密封材料区分，常用的两种封装形式分别为硅胶填充(Gel type)和塑封(Molding type)两种结构。无论是硅胶填充，还是塑封，芯片上表面电极和DBC(Direct Bonded Copper，直接覆铜陶瓷)电路图形均通过引线(多采用铝线)键合工艺(Wire Bonding)实现模块内部电信号的连接。
芯片贴装工艺通常采用贴片机(Die Bonder)将芯片从切割好的晶圆(Wafer)上拾取，并将芯片贴装至DBC基板。在芯片贴装(Die Bonding)过程中，从采用真空通过吸嘴将芯片拾取，到控制压力将芯片贴装至所在DBC基板，其受力和位置均可控，从而确保芯片无损伤及其设计的贴装位置。其中基板包括导电层(Conductive Trace)和绝缘层(Insulation Layer)，在多个功率芯片贴装工艺中，由于需要将每颗芯片单独贴装至基板上，因此两颗芯片之间的距离P受单颗芯片贴装位置偏移量W和导电层之间距离G决定，偏移量W主要需要考虑连接材料(Die attach)的涂覆偏移、芯片贴装偏移和基板导电层图形的精度，受到工艺和基板材料的精度限制。在制作过程中包括共导电层和不共导电层，共导电层是指多颗芯片的设置于同一导电层上，不共导电层是指多颗芯片设置于不同的导电层上。图1为表示两个功率芯片(Power Chip)11通过连接材料12贴装至基板13时芯片不共导电层的截面示意图，图中14为导电层，图2为对应图1的平面图，其中偏移量W最小为0.1mm，导电层之间的间距G最小为0.2mm,因此对于芯片底部不共导电层的两颗芯片之间间距P至少为0.4mm(其中P＝2*W+G)。如两颗芯片底部共 用导电层，图3为表示两个功率芯片通过芯片连接材料贴装至基板时芯片共导电层的截面示意图，图4为对应图3的平面图，为防止芯片接触，W至少为0.1mm，因此芯片之间的间距P最短不小于0.2mm,(其中P＝2*W)。
由上可见，对于多功率芯片构成的功率封装模块，目前的封装工艺采用共导电层或不共导电层均难以实现更小的芯片间距。
发明内容
针对现有技术中存在的问题，本发明提供一种多功率芯片的功率封装模块及功率芯片单元的制造方法，以解决现有技术中功率芯片的间距难以实现更小的间距导致功率模块的效率降低的技术问题。
为实现上述目的，一方面，
本发明提供了一种多功率芯片的功率封装模块，包括：
一功率芯片单元，包括至少两个并行设置的功率芯片和连接所述两个功率芯片的连接体；
一基板，承载所述功率芯片单元，所述基板包括一金属层，所述金属层与所述功率芯片单元电性连接；
密封层，将安置于基板上的功率芯片单元与周边环境隔离，实现功率芯片单元的密封；
所述连接体和所述密封层的材料各为不同的绝缘材料，所述两个并行设置的功率芯片之间的间隔小于等于预设宽度，所述连接体填充于所述间隔之中连接且绝缘所述两个并行设置的功率芯片。
在本发明的一个实施例中，所述预设宽度为200微米。
在本发明的另一个实施例中，所述连接体的厚度范围为1/3T～T，其中T为所述功率芯片的厚度。
在本发明的另一个实施例中，所述连接体的材料硬度为邵氏A10以上，绝缘强度大于10kV/mm，电阻大于1.0E11Ω·cm。
在本发明的另一个实施例中，所述连接体中还包含有填料，且所述填料的最大粒径小于所述预设宽度。
在本发明的另一个实施例中，所述填料的材料为石英、氧化铝、氢氧化铝、氧化锌或氮化硼其中的一种或几种组合。
在本发明的另一个实施例中，所述多功率芯片的功率模块还包括金属键合线，所述金属键合线连接所述功率芯片和所述金属层。
在本发明的另一个实施例中，所述功率芯片单元中两个功率芯片并联连接，所述连接体的宽度小于和等于所述预设宽度以提高所述连接体连接的两个并联连接功率芯片存在的寄生电感的均匀性。
在本发明的另一个实施例中，所述功率芯片单元中两个功率芯片串联连接，所述连接体的宽度小于和等于所述预设宽度以减小所述连接体连接的两个串联连接功率芯片存在的寄生电感。
在本发明的另一个实施例中，所述功率芯片为垂直型功率芯片。
另一方面，
本发明还提供了一种功率芯片单元的制造方法，该功率芯片单元包括至少两个并行设置的功率芯片，所述制造方法包括：
提供一包括若干呈阵列摆布功率芯片的晶圆；
将所述晶圆的一面铺上一衬面后，切割所述晶圆的另一面形成功率芯片与功率芯片之间的间隔；
在所述晶圆的另一面涂覆连接体，使所述连接体填充入所述功率芯片与功率芯片之间的间隔；
切割所述晶圆中部分连接体而分离出若干独立的功率芯片单元，所述功率芯片单元中的功率芯片由所述连接体连接。
在本发明的一个实施例中，所述功率芯片与功率芯片之间的间隔小于预设宽度。
在本发明的另一个实施例中，所述预设宽度小于等于200微米。
在本发明的另一个实施例中，所述连接体的材料硬度为邵氏A10以上，绝缘强度大于10kV/mm，电阻大于1.0E11Ω·cm。
本发明的有益效果在于，在晶圆处理过程中，通过在并列设置的两个功率芯片的间隔中填充连接体，完成芯片之间的绝缘连接，实现芯片与芯片之间的近距离连接。在半导体功率模块的封装中，可将多个功率芯片进行一次贴装，提高芯片的贴装效率。同时由于芯片之间的间距缩短，减小功率芯片之间的寄生电感，降低芯片的最大结温，能够降低功率芯片的损耗和电压应力，从而提高功率封装模块的效率和可靠性。
附图说明
图1为现有技术中两个功率芯片通过芯片连接材料贴装至基板时芯片不共导电层的截面示意图。
图2为现有技术中图1结构的平面图。
图3为现有技术中两个功率芯片通过芯片连接材料贴装至基板时芯片共导电层的截面示意图。
图4为现有技术中图3结构的平面图。
图5为典型硅胶填充的半导体功率模块结构示意图。
图6为典型塑封的半导体功率模块结构示意图。
图7为两个功率芯片并联结构拓扑示意图。
图8为两个功率芯片半桥结构拓扑示意图。
图9为带有寄生参数的并联结构的拓扑示意图。
图10为采用引线键合方式的并联结构的封装结构示意图。
图11为带有寄生参数的半桥结构的拓扑示意图。
图12为采用引线键合方式的半桥结构的封装结构示意图。
图13为本发明实施例一提供的一种多功率芯片的功率封装模块的结构示意图。
图14为本发明实施例一中功率芯片单元的结构示意图。
图15为本发明实施例二中采用金属键合线的方式实现不共衬底的串联芯片封装模块的结构示意图。
图16为本发明实施例三中采用金属键合线的方式实现不共衬底的并联结构的芯片封装模块的结构示意图。
图17为本发明实施例三中采用金属键合线的方式实现共衬底的并联结构的芯片封装模块的结构示意图。
图18为本发明实施例三中采用金属键合线的方式实现共D衬底的并联芯片封装模块的结构示意图。
图19为本发明实施例三中采用金属键合线的方式实现共S衬底的并联芯片封装模块的结构示意图。
图20为本发明实施例四中采用金属桥的方式实现不共衬底的半桥结构 芯片封装模块的结构示意图。
图21为本发明实施例四中采用金属桥的方式实现不共衬底的并联结构芯片封装模块的结构示意图。
图22为本发明实施例四中采用金属桥的方式实现共衬底的并联结构芯片封装模块的结构示意图。
图23为本发明实施例四中采用金属桥的方式实现共D衬底的并联结构芯片封装模块的结构示意图。
图24为本发明实施例四中采用金属桥的方式实现共S衬底的并联结构芯片封装模块的结构示意图。
图25为本发明实施例五中采用芯片倒装工艺的半桥结构的芯片封装模块的结构示意图。
图26为本发明实施例五中采用芯片倒装工艺的并联结构的芯片封装模块的结构示意图。
图27为本发明实施例五中采用含有导电球的芯片倒装工艺的半桥结构的芯片封装模块的结构示意图。
图28为本发明实施例五中采用含有导电球的芯片倒装工艺的并联结构的芯片封装模块的结构示意图。
图29为本发明实施例五中采用含有导电柱的芯片倒装工艺的半桥结构的芯片封装模块的结构示意图。
图30为本发明实施例五中采用含有导电柱的芯片倒装工艺的并联结构的芯片封装模块的结构示意图。
图31为本发明实施例五中对应图29的半桥结构的封装模块主回路截面示意图。
图32为本发明实施例六中提供的一种功率芯片单元的制造方法的步骤流程图。
图33为本发明实施例六中提供的对晶圆的后道处理工艺的流程图。
图34为采用图33的工艺流程得到具有三个功率芯片的功率芯片单元切割时的示意图。
具体实施方式
体现本发明特征与优点的典型实施例将在以下的说明中详细叙述。应理解的是，本发明能够在不同的实施例上具有各种的变化，其皆不脱离本发明的范围，且其中的说明及附图在本质上是当作说明之用，而非用以限制本发明。
硅胶填充的半导体功率模块结构如图5所示，DBC基板101的第一表面和第二表面均设置有金属层，并对DBC基板101第一表面的金属层进行刻蚀形成电路图形(也就是导电层)102，同时DBC基板101还作为芯片103的连接基板，采用焊料(也即是连接材料)104将芯片103整个底面完全焊接至DBC基板101的导电层102上。芯片103上表面电极和导电层102通过引线105(多采用铝线)键合工艺(Wire Bonding)实现模块内部电信号的连接。再通过焊料104将电极端子(Power terminal)106和栅极信号端子(Gate Terminal)107焊接至DBC基板101上，实现功率模块与外部电路的电连接。由于半导体功率芯片容易受湿气、离子、粉尘的影响，采用硅胶(Silicone gel)108对其进行封装和保护。同时还为保证电极端子的结构稳定，一般安装塑胶外壳(Plastic Housing)109对其进行机械支撑，塑胶外壳形成在DBC基板的第一表面上，也就是DBC基板与其第二表面的金属层是裸露在外面的。
而典型的塑封的半导体功率模块结构如图6所示，与图5中的结构相比，包括DCB基板101、导电层102、芯片103、焊料104、引线105、电极端子106以及栅极信号端子107均同于图5，另外除了密封材料不同之外(图6中填充塑封材料109)，其电极端子并非采用独立端子，一般采用一体的引线框架，焊接至DBC基板101上进行电信号的连接，引线框架之间的连接部分在功率模块封装完成后，进行切断和折弯处理。由于塑封材料为环氧类材料，能与其他封装材料良好连接，同时具备较高的机械强度，能可靠地固定端子。
以上是对封装不同的两种功率模块的结构进行介绍，如果以实现不同功能拓扑结构划分，一般分为并联结构和半桥结构两种封装模块。功率芯片的通流能力会受芯片工艺、散热等限制，如需应用于更高的功率等级或电流等级，会考虑将多个功率芯片并联使用，两个功率芯片并联结构拓扑示意图如图7所示，两个功率芯片T1和T2的源极S和漏极D并联，半桥结构拓扑示意图如图8所示，所谓“半桥结构”其实质上就是两个功率芯片串联，参见 图8，T1的源极S连接T2的漏极D，而T1的漏电极D连接一导电层Vbus+，T2的源电极S连接另一导电层Vbus-。
功率封装模块中，考虑到电气连接的路径，图1的硅胶填充和图3的塑封两种封装结构中，均是利用铝线与DCB基板第一表面的导电层连接，这样就会产生寄生参数。带有寄生参数的并联结构的拓扑图如图9所示，以两个芯片并联为例，芯片T1的主要寄生参数包括Lg1、Ld1、Ls1等，芯片T2的主要寄生参数包括Lg2、Ld2、Ls2等，其中Lg1/Lg2为芯片栅极(G1/G2)至栅极驱动之间的寄生电感，分别影响芯片T1和T2的开关速度，当Lg1与Lg2不同时，将引起T1，T2芯片开关速度不同，开关损耗不同；Ld1+Ls1/Ld2+Ls2分别为T1，T2两端漏极(D1/D2)和源极(S1/S2)导电连接的寄生电感，包括铝线和部分基板上的导电层，将分别影响T1和T2开通瞬间的电流分布，Ld1+Ls1与Ld2+Ls2不相等时，将导致芯片不均流，差异越大，开通瞬间电流差异越大，损耗也越大，温度差异也越大，造成芯片最大结温上升。以上寄生参数由于芯片布局的关系，将导致T1，T2芯片的寄生参数不同。采用引线键合方式的并联结构的封装结构示意图如图10所示，包括基板101、导电层102、芯片103、焊料104以及引线105，且D1、D2均连接至独立的导电层D，G1、G2均连接至独立的导电层G，S1、S2均连接至独立的导电层S。通过T1,T2寄生参数分析发现，影响寄生参数的一个因素为并联芯片之间的间距，如缩短其间距，将减小并联芯片之间的封装寄生参数Lg1与Lg2、以及Ld1+Ls1与Ld2+Ls2的差别，能更好地平衡并联芯片的电流分布并降低其损耗，从而提高效率，降低芯片最大结温。其中芯片的最大结温是指芯片在工作过程中结温的最大值。
带有寄生参数的半桥模块结构的拓扑图如图11所示，以平面型功率芯片为例，芯片T1的主要寄生参数包括Lg1、Ld1、Ls1等，芯片T2的主要寄生参数包括Lg2、Ld2、Ls2等，其中对应主电路上Ld1+Ls1/Ld2+Ls2分别为T1，T2两端漏极(D1/D2)和源极(S1/S2)导电连接的寄生电感，包括铝线和部分基板上的导电层。其中，减小Ls1+Ld2将降低T2的电压应力，减小Ls1可提高T1的开关速率，降低其损耗。
采用引线键合方式的半桥结构的封装结构示意图如图12所示，包括基板101、导电层102、芯片103、焊料104以及引线105。其中导电层102包括 多个独立的导电端，例如Vbus+、Vbus-、G1、S1、G2和S2等导电端。图12中T2的S2连接至独立的导电端Vbus-及导电端S2，T2的G2连接至独立的导电端G2，T2的D2以及T1的S1连接至独立的导电端Phase，T1的S1还连接至独立的导电端S1，T1的G1连接至独立的导电端G1，T1的D1连接至独立的导电端Vbus+。从图12所示的采用引线键合方式的半桥模块的封装结构示意图中可以发现，Ls1+Ld2主要受T1源极S1和T2漏极D1之间的电气连接路径影响，如缩短T1和T2间距，可减小Ls1和Ld2，降低T2的电压应力并提高T1的开关速度，提高芯片可靠性和效率。
综上，基于对功率模块电气特性的分析，传统的功率半导体常受到寄生电感的影响，而于功率半导体内产生较大的电压尖峰，严重影响功率半导体乃至于整体电力电子装置的性能。如能提供一种新的芯片处理工艺和封装结构，以减小芯片之间的间距，就多芯片并联结构的封装模块而言，可使并联芯片的电流分布更均匀并降低其损耗，从而提高效率，降低芯片最大结温；对于半桥结构的封装模块而言，可降低回路的寄生电感，从而提高芯片可靠性和效率。
实施例一
本实施例提供了一种多功率芯片的功率封装模块，结构示意图如图13所示，包括：
一功率芯片单元，包括至少两个并行设置的功率芯片131和连接两个功率芯片131的连接体132，；
一基板133，承载功率芯片单元，基板包括一金属层(图中未示出)，金属层与功率芯片单元电性连接；
密封层134，塑封基板133表面以将功率芯片单元与周边环境隔离；
连接体132和密封层134的材料各为不同的绝缘材料，两个并行设置的功率芯片T1和T2之间的间隔小于等于预设宽度，连接体132填充于间隔之中连接且绝缘两个并行设置的功率芯片T1和T2。
其中功率芯片单元200的结构示意图如图14所示，本实施例中是以功率芯片单元200中包括两个功率芯片T1和T2为例，在实际应用中可以根据需要选择多个功率芯片，并通过连接体的连接构成具有多个功率芯片的功率芯 片单元，在贴装过程中就可以一次贴装工艺完成多个芯片的贴装，可以提高贴装的效率，同时芯片间距不受贴装工艺的影响，可以做到很小的芯片间距。两个芯片之间的间距P主要受晶圆切割工艺限制，一般切割工艺包括使用刀片进行机械切割，激光切割等，将晶圆切割成相互隔开的单颗芯片的切割刀宽度即为芯片之间可实现的间距，目前以上技术的切割宽度至多不超过200微米，因此本实施例中的预设宽度为200微米。
一般地，芯片间隔中的连接体202的热膨胀系数高于芯片材料的膨胀系数，由于芯片工作时发热，同时绝缘性质的连接体与芯片材料热膨胀系数不匹配，使连接体产生热应力，叠加由于芯片和基板热膨胀系数不匹配导致芯片连接层的热应力，使芯片间隔中的连接体更易失效，尤其对于采用硅胶密封的模块风险更大。可通过降低连接体的厚度来减小芯片连接的热应力，同时还需要连接体具备一定厚度，起到良好连接芯片的作用，因此要求连接体202的厚度t的范围为1/3T～T，其中T为功率芯片的厚度，参见图14所示。通常可通过晶圆后道处理工艺中的晶圆切割工艺，在芯片之间连接体的位置处，通过调整机械切割的刀片高度，对绝缘连接材料进行部分切割，以控制连接体的厚度。
考虑连接体能够粘接芯片，需要一定的机械强度，同时能够填充在片之间的切割槽中，需要良好的流动性和填缝性，另外，能实现平面型芯片衬底之间的绝缘。连接体可以为有机硅类树脂粘接材料，包括纯树脂为基材的有机硅粘接胶，环氧改性有机硅粘接胶，酚醛改性有机硅粘接胶等；还可以是单组份或者双组份的硫化硅橡胶等；还可以为环氧树脂等，其成分中可加入填料以调整其物理特性。具体而言，要求连接体的材料硬度为邵氏A10以上，绝缘强度大于10kV/mm，体积电阻大于1.0E11Ω·cm，同时还要保证连接体与功率芯片的粘接强度大于100Pa。连接体的内部还可以含有填料，如含有填料，要求填料的最大粒径小于预设宽度。填料可为石英，氧化铝，氢氧化铝，氧化锌，氮化硼其中的一种或几种组合，能通过1000倍以下显微镜观察到填料的存在。
其中功率芯片201可以是平面型芯片，平面型芯片包括平面型IGBT(Insulated-Gate Bipolar Transistor，绝缘栅双极型晶体管)，MOSFET(Metal-Oxide Semiconductor Field Effect Transistor，金氧半场效晶体 管)，二极管等，也包括驱动功率芯片的Driver IC芯片和实现芯片开关控制策略的Control IC，其材料可以为Si，SiC，GaN等。另外，功率芯片还可以由Dirver IC芯片或control IC芯片与前述单一功率芯片集成，或者由Driver IC,control IC，前述单一功率芯片集成。同样地，本实施例的结构也能够很好的适用于并联结构的垂直型开关芯片。
基板203包括PCB(Printed Circuit Board，印刷电路板)、LF(Lead-frame，引线框)、DBC(Direct Bonding Copper，直接覆铜陶瓷)基板、DBA(Direct Bonding Aluminum，直接覆铝)基板、金属共烧陶瓷基板和IMS(Insulated Metal Substrate，金属绝缘基板)基板、金属或金属复合基板(如铜、铝、铝碳化硅)、陶瓷(如Al2O3，AlN，BeO，Si3N4等，这四种均称作陶瓷)绝缘基板等。
参见图13中，功率芯片201与DCB基板203之间还有连接材料135，通过连接材料135将功率芯片安装在基板上，连接材料135可以是焊料，金属间化合物(IMC，Intermetalic Compound)，也可以包括低温烧结材料(如银、铜焊膏等可在低温下进行烧结实现芯片与基板之间互联的材料)、导电银胶等导电连接材料，也可以为有机硅类、或环氧类绝缘粘接材料，因此连接材料可以是导电的，也可以是绝缘的，需要根据具体的应用环境进行选择。
功率封装模块中还需要包括密封层134，用于包覆功率芯片与连接体构成的功率芯片单元以及基板的表面，使其与周围环境隔离，密封层一般包括硅凝胶、硅橡胶、环氧类塑封材料等，但与功率芯片间隔中的连接体的成分或特性有所不同。
参见图10和12，基板上通常还设置有一层金属层(图13和图14中未示出)，功率芯片与基板之间就通过这一层金属层进行电性连接。进一步的，多功率芯片的功率模块还包括金属键合线，用于连接功率芯片和金属层，其中金属键合线的材料可以为Al，Cu，Au等。
综上所述，本实施提供的多功率芯片的功率封装模块通过在并列设置的两个功率芯片的间隔中填充连接体，完成芯片之间的绝缘连接，实现芯片与芯片之间的近距离连接。在半导体功率模块的封装中，可将多个功率芯片进行一次贴装，提高芯片的贴装效率。同时由于芯片之间的间距缩短，减小功率芯片之间的寄生电感，降低芯片的最大结温，能够降低功率芯片的损耗和 电压应力，从而提高功率封装模块的效率和可靠性。
实施例二
基于上述实施例一中通过金属键合线连接功率芯片和金属层，本实施例中也提供了一种多功率芯片的功率封装模块，其中的功率芯片单元中两个功率芯片串联连接，而且并行设置的芯片间隔中的连接体的宽度小于和等于预设宽度以减小连接体连接的两个串联连接功率芯片存在的寄生电感。
对于采用金属键合线的方式实现串联芯片封装模块的结构示意图如图15所示，两个功率芯片为平面型功率芯片，可通过实施例一中所述的设置在芯片153底部的连接材料154将其贴装至基板151(基板为绝缘材料)上，芯片为不共衬底(不共衬底是指多个芯片的衬底没有电气连接)，即芯片的底部直接通过绝缘的连接材料154贴至基板上，没有导电层，处于悬浮状态，其表面电气连接可通过引线155键合(Wire bonding)工艺实现。具体引线键合的连线实施方案为：芯片T1的漏极D1连接至导电层(图15中Vbus+端)；芯片T1的源极S1和T2的漏极D2之间直接通过引线连接；芯片T2的源极S2连接至导电层(图15中Vbus-端)；分别从T1的S1和T2的D2连接至导电层(图15中phase端)；T1，T2的栅极G1/G2和源极S1/S2的信号端分别连接至独立的导电层上，芯片T1和T2之间为填充的连接体156。
本实施例中，由于T1的源极S1和T2的漏极D2之间直接电气连接，且芯片间距短，故连接的路径变短，减小前述半桥拓扑结构中的寄生参数Ls1和Ld2，从而提高半桥模块的效率和可靠性。
实施例三
基于上述实施例一中通过金属键合线连接功率芯片和金属层，本实施例中也提供了一种多功率芯片的功率封装模块，其中的功率芯片单元中两个功率芯片并联连接，而且并联的芯片间隔中的连接体的宽度小于和等于预设宽度以提高连接体连接的两个并联连接功率芯片存在的寄生电感的均匀性。
对于采用金属键合线的方式实现并联芯片封装模块的结构示意图如图16所示，两个功率芯片可通过实施例一中所述的设置在芯片173底部的连接材料164将其贴装至基板161(基板为绝缘材料)上，芯片之间通过连接体 166连接，芯片是不共衬底(不共衬底是指多个芯片的衬底没有电气连接)，即芯片的底部直接通过连接材料164贴至基板上，没有导电层，处于悬浮状态，其表面电气连接可通过引线键合(Wire bonding)工艺实现。具体引线键合的连线实施方案为：T1和T2的漏极D1，D2连接至导电层中的导电端(图16中D端)；T1和T2的源极S1，S2连接至导电层(图中S端)；T1和T2的栅极G1，G2连接至导电层中的导电端(图中G端)。
与图16不同，本实施例中还提供了三种共衬底的并联芯片封装模块，结构示意图分别如图17、18和19所示，图17中，并联芯片底部采用连接材料连接至基板上独立的导电层162，导电层162处于悬浮状态；图18中，并联芯片底部采用连接材料连接至基板导电层的D端(也就是D端作为导电层162)；图19中，并联芯片底部采用连接材料连接至基板导电层的S端(即S端作为导电层162)。
本实施例中，由于芯片之间间距小，减小并联芯片之间的封装寄生参数的差别，更好地平衡并联芯片的电流分布并降低其损耗，从而降低芯片最大结温，提高效率。
实施例四
基于上述实施例二和三，可以通过金属键合线实现芯片与金属层的电气连接，由于金属引线的截面积小，其寄生参数仍较大，因此本实施例中还可以通过金属桥实现芯片与金属层的电气连接。
半桥结构的功率封装模块的结构示意图如图20，包括基板201、导电层202、芯片203、连接材料204以及芯片之间的连接体206，半桥模块中可将T1芯片的漏极D1与第一导电层Vbus+端之间、T1的源极S1与T2的漏极D2之间、T2的源极S2与第二导电层Vbus-端之间采用金属桥205连接方式。该金属桥材料可以为Al,Cu,Ag,Au等，采用的连接工艺为超声连接(Ultrasonic bonding)，金属扩散连接(Metal-metal diffusion bonding)，焊接等，其余连接线路仍采用金属键合线207或金属桥205的连接方法。
与上述实施例二相同，采用金属桥连接的半桥结构的功率封装模块仍然分为不共衬底和共衬底两类结构，其中图20为不共衬底的半桥结构的功率封装模块的结构示意图。当然除了图20中不共衬底的结构，还可以是共衬底结 构，可以是共衬底悬浮状态、或者是共衬底接Vbus-，还或者是共衬底接phase。
并联结构的功率封装模块的结构示意图如图21-24所示，采用金属桥的方式实现T1/T2的漏极D1/D2与导电线路的D端之间连接，T1/T2的源极S1/S2与导电线路的S端之间连接，其中图21为不共衬底的并联结构的功率封装模块的结构示意图，图22为共衬底(悬浮状态)的并联结构的功率封装模块的结构示意图，图23为共衬底(与D端共衬底)的并联结构的功率封装模块的结构示意图，即D端作为共衬底202a，图24为共衬底(与S端共衬底)的并联结构的功率封装模块的结构示意图，即S端作为共衬底202a。
本实施例中，不论是对于半桥结构而言，还是对于并联结构而言，采用金属桥的方式实现芯片与金属层的电气连接，能够增大电气连接的截面积，进一步减小寄生参数。
实施例五
基于上述实施例四，可以通过金属桥实现芯片与金属层的电气连接，由于金属桥在进行连接时需要折弯，导致导电路径较长，相应回路寄生参数仍较大，本实施例中考虑通过芯片倒装(Flip-chip)工艺能够缩短电气路径。如果不考虑芯片衬底连接方式(当然，后续实施例中，芯片衬底连接方式仍包括前述不共衬底和共衬底两类结构)，图25和26中为使用连接材料将芯片表面贴装至基板的导电层，实现半桥模块和并联模块的电气连接，其中连接材料需为前面实施例一所述导电的连接材料。当芯片G，S，D电极间距较近，采用该方案可能会导致芯片不同电极之间连接材料发生互联，造成短路。因此，本实施例中在采用芯片倒装技术的基础上，还要采用导电球或导电柱将导电层和芯片电极隔开，减小电极短路的风险，图中包括导电层252、芯片253、连接材料254以及芯片之间的连接体256。
使用导电球将芯片表面贴装至基板的导电层，实现半桥模块和并联芯片模块的电气连接的结构示意图分别如图27和28所示，其中图27和图28中导电球用255表示，材料可以为焊料，Cu，Au，Ag，或其他合金等。一般地，导电球需采用前述导电的连接材料实现导电球与基板导电层和芯片表面的机械和电气连接。
使用导电柱将芯片表面贴装至基板的导电层，实现半桥模块和并联芯片 模块的电气连接的电气连接的结构示意图分别如图29和30所示，其中导电柱可以为焊料，Cu，Au，Ag，或其他合金等。一般地，导电柱同样需要采用前述导电芯片连接材料将芯片不同极连接至基板的导电层。金属导电柱也可通过电镀工艺在芯片上表面S，D，G端长出导电柱，图29和30中的导电柱用277表示，实现导电柱和芯片表面金属层的连接，导电层也可通过电镀金属的方式生长而成，最后通过刻蚀技术，形成导电层的图形。对于图29的半桥结构的封装模块主回路截面示意图如示意如图31所示，导电柱一般为圆柱状或倒圆锥状，图31中包括导电层312、芯片313、连接材料314、芯片之间的连接体316以及倒圆锥状的导电柱317。其中导电柱317和导电层312可以为同一导电材质，也可为不同导电材质。
本实施例中，采用芯片倒装工艺，并结合导电球或导电柱，可以进一步减小回路寄生参数。
实施例六
本实施例还提供了一种功率芯片单元的制造方法，该功率芯片单元包括至少两个并行设置的功率芯片，该制造方法的步骤流程如图34所示，包括以下步骤：
步骤S11、提供一包括若干呈阵列摆布功率芯片的晶圆；
步骤S12、将晶圆的一面铺上一衬面后，切割晶圆的另一面形成功率芯片与功率芯片之间的间隔；
步骤S13、在晶圆的另一面涂覆连接体，使连接体填充入功率芯片与功率芯片之间的间隔；
步骤S14、切割晶圆中部分连接体而分离出若干独立的功率芯片单元，功率芯片单元中的功率芯片由连接体连接。
其中功率芯片与功率芯片之间的间隔小于预设宽度，本实施例中优选的预设宽度小于等于200微米。同时，对于芯片间隔中的连接体的材料和性能有一定的要求，具体的，连接体的材料硬度为邵氏A10以上，绝缘强度大于10kV/mm，电阻大于1.0E11Ω·cm。另外，连接体的材质虽然也是绝缘材质，但是却与传统的封装功率芯片单元的密封层的成分或特性是有所不同的。密封层的材料一般是硅凝胶、硅橡胶、环氧类塑封材料等，而连接体可以是有 机硅类树脂粘接材料，包括纯树脂为基材的有机硅粘接胶，环氧改性有机硅粘接胶，酚醛改性有机硅粘接胶等；还可以是单组份或者双组份的硫化硅橡胶等；还可以为环氧树脂等，其成分中可加入填料以调整其物理特性。当连接体中含有填料时，需要满足填料的最大粒径小于预设宽度。
在进行上述步骤之前还包括对芯片进行晶圆制造的前道工艺，即完成芯片上表面电路金属化以后，再进行本实施例的晶圆后道处理工艺，实现多个芯片之间的绝缘，以及芯片之间的近距离连接。基于上述，对晶圆的后道处理工艺的流程图如图33所示，包括：第一步，先将晶圆331金属化面贴至蓝膜或UV膜332上；第二步，将晶圆331的背面(图中用A表示)即衬底朝上，从晶圆的背面(即衬底)，切割刀沿切割槽将晶圆331进行切割，使晶圆上的各平面型芯片独立，如图中所示，以晶圆上的四个功率芯片为例，四个功率芯片T1,T2,T3,T4相互隔开；第三步，将流动的连接体 333(具有粘接性的绝缘物质)填入切割槽中，填入的方法可以为点胶、旋转涂覆等，填入的连接体流入到切割槽中，待填充完全后进行固化处理；第四步，将晶圆衬底进行减薄，处理至需要的厚度；第五步，去除上表面，即金属化面的蓝膜，并将晶圆衬底(即A面)贴至蓝膜334上，如果平面型芯片衬底连接选择焊接或烧结等芯片连接工艺，可在晶圆衬底进行表面金属化处理；第六步，按照封装需求进行切割，如封装需要两颗芯片同时贴装，则每隔两颗芯片进行切割。以上晶圆后道处理工艺不仅限于制备两个功率芯片的连接，亦可用于制备两颗以上连接的多个功率芯片连接,例如还可以是功率芯片单元中包括三个功率芯片，则切割时的示意图如图34所示。
本实施例提供的制造方法，在晶圆处理过程中，通过在并列设置的两个功率芯片的间隔中填充连接体，相比于传统工艺中一个一个的贴装芯片，能够缩短芯片的间距，通过连接体完成芯片之间的绝缘连接，实现芯片与芯片之间的近距离连接。在半导体功率模块的封装中，可将多个功率芯片进行一次贴装，提高芯片的贴装效率。同时由于芯片之间的间距缩短，减小并行设置的串联功率芯片之间的寄生电感，降低芯片的最大结温，利于降低功率芯片的损耗和电压应力，提高功率封装模块的效率和可靠性。
本领域技术人员应当意识到在不脱离本发明所附的权利要求所公开的本发明的范围和精神的情况下所作的更动与润饰，均属本发明的权利要求的保护范围之内。

Claims (14)

1.一种多功率芯片的功率封装模块，其特征在于，包括：
一功率芯片单元，包括至少两个并行设置的功率芯片和连接所述两个功率芯片的连接体；
一基板，承载所述功率芯片单元，所述基板包括一金属层，所述金属层与所述功率芯片单元电性连接；
密封层，将安置于所述基板上的所述功率芯片单元与周边环境隔离，实现所述功率芯片单元的密封；
所述连接体和所述密封层的材料各为不同的绝缘材料，所述两个并行设置的功率芯片之间的间隔小于等于预设宽度，所述连接体填充于所述间隔之中连接且绝缘所述两个并行设置的功率芯片。
2.根据权利要求1所述的多功率芯片的功率封装模块，其特征在于，所述预设宽度为200微米。
3.根据权利要求1所述的多功率芯片的功率封装模块，其特征在于，所述连接体的厚度范围为1/3T～T，其中T为所述功率芯片的厚度。
4.根据权利要求1所述的多功率芯片的功率封装模块，其特征在于，所述连接体的材料硬度为邵氏A10以上，绝缘强度大于10kV/mm，电阻大于1.0E11Ω·cm。
5.根据权利要求4所述的多功率芯片的功率封装模块，其特征在于，所述连接体中还包含有填料，且所述填料的最大粒径小于所述预设宽度。
6.根据权利要求5所述的多功率芯片的功率封装模块，其特征在于，所述填料的材料为石英、氧化铝、氢氧化铝、氧化锌或氮化硼其中的一种或几种组合。
7.根据权利要求1所述的多功率芯片的功率封装模块，其特征在于，所述多功率芯片的功率模块还包括金属键合线，所述金属键合线连接所述功率芯片和所述金属层。
8.根据权利要求1所述的多功率芯片的功率封装模块，其特征在于，所述功率芯片单元中两个功率芯片并联连接，所述连接体的宽度小于和等于所述预设宽度以提高所述连接体连接的两个并联连接功率芯片存在的寄生电感的均匀性。
9.根据权利要求1所述的多功率芯片的功率封装模块，其特征在于，所述功率芯片单元中两个功率芯片串联连接，所述连接体的宽度小于和等于所述预设宽度以减小所述连接体连接的两个串联连接功率芯片存在的寄生电感。
10.根据权利要求1所述的多功率芯片的功率封装模块，其特征在于，所述功率芯片为垂直型功率芯片。
11.一种功率芯片单元的制造方法，其特征在于，该功率芯片单元包括至少两个并行设置的功率芯片，所述功率芯片单元制造方法包括：
提供一包括若干呈阵列摆布功率芯片的晶圆；
将所述晶圆的一面铺上一衬面后，切割所述晶圆的另一面形成功率芯片与功率芯片之间的间隔；
在所述晶圆的另一面涂覆连接体，使所述连接体填充入所述功率芯片与功率芯片之间的间隔；
切割所述晶圆中部分连接体而分离出若干独立的功率芯片单元，所述功率芯片单元中的功率芯片由所述连接体连接。
12.根据权利要求11所述的功率芯片单元的制造方法，其特征在于，所述功率芯片与功率芯片之间的间隔小于预设宽度。
13.根据权利要求12所述的功率芯片单元的制造方法，其特征在于，所述预设宽度小于等于200微米。
14.根据权利要求11所述的功率芯片单元的制造方法，其特征在于，所述连接体的材料硬度为邵氏A10以上，绝缘强度大于10kV/mm，电阻大于1.0E11Ω·cm。
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