CN202178252U - 多圈排列无载体双ic芯片封装件 - Google Patents

多圈排列无载体双ic芯片封装件 Download PDF

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CN202178252U
CN202178252U CN201120228061.5U CN201120228061U CN202178252U CN 202178252 U CN202178252 U CN 202178252U CN 201120228061 U CN201120228061 U CN 201120228061U CN 202178252 U CN202178252 U CN 202178252U
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chip
chips
pin
bumps
salient point
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朱文辉
慕蔚
李习周
郭小伟
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Tianshui Huatian Technology Co Ltd
Huatian Technology Xian Co Ltd
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Tianshui Huatian Technology Co Ltd
Huatian Technology Xian Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

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Abstract

一种多圈排列无载体双IC芯片封装件，包括引线框架、内引脚、IC芯片及塑封体，引线框架四边呈数圈排列有引线框架内引脚，设有带凸点的IC芯片和不带凸点的IC芯片，带凸点的IC芯片的凸点设置在第一圈内引脚上，带凸点的IC芯片背面设有粘片胶，粘接不带凸点的IC芯片，不带凸点的IC芯片上的焊盘与第二圈内引脚之间焊线连接，形成键合线。本实用新型比同样面积的单排引线框架的引脚数设计增加40%以上；IC芯片倒装上芯，热传导距离短，具有较好的热性能，信号传输快，失真小，具有良好的电性能和良好的高频性能。倒装上芯的凸点＋助焊剂的高度远小于焊线弧高，使封装产品厚度可以低于0.5mm，避免了焊线的交丝和开路，提高了测试良率和可靠性。

Description

多圈排列无载体双IC芯片封装件
技术领域
本实用新型涉及电子信息自动化元器件制造技术领域，尤其涉及到四边扁平无引脚IC芯片封装，具体说是一种多圈排列无载体双IC芯片封装件。
背景技术    
近年来，随着移动通信和移动计算机领域便捷式电子元器件的迅猛发展，小型封装和高密度组装技术得到了长足的发展；同时，也对小型封装技术提出了一系列严格要求，诸如，要求封装外形尺寸尽量缩小，尤其是封装高度小于1 mm。封装后的连接可靠性尽可能提高，适应无铅化焊接（保护环境）和有效降低成本。
QFN(Quad Flat No Lead Package) 型多圈IC芯片倒装封装的集成电路封装技术是近几年发展起来的一种新型微小形高密度封装技术，是最先进的表面贴装封装技术之一。由于无引脚、贴装占有面积小，安装高度低等特点，为满足移动通信和移动计算机领域的便捷式电子机器，如PDA、3G手机、MP3、MP4、MP5等超薄型电子产品发展的需要应用而生并迅速成长起来的一种新型封装技术。目前的四边扁平无引脚封装件，由于引脚少，即I/O少，满足不了高密度、多I/O封装的需要，同时焊线长，影响高频应用。而且QFN一般厚度控制在0.82mm～1.0 mm，满足不了超薄型封装产品的需要。
实用新型内容
本实用新型所要解决的技术问题是提供一种能实现引脚间距为0.65mm～0.50 mm，I/O数达200个的高密度封装四边扁平无引脚的一种多圈排列无载体双IC芯片封装件。 
本实用新型的技术问题采用下述技术方案实现：
一种多圈排列无载体双IC芯片封装件，包括引线框架、内引脚、IC芯片及塑封体，引线框架四边呈数圈排列有引线框架内引脚，所述引线框架采用无载体引线框架，所述IC芯片设有带凸点的IC芯片和不带凸点的IC芯片，带凸点的IC芯片的凸点设置在第一圈内引脚上，带凸点的IC芯片背面设有粘片胶或胶膜片，粘片胶或胶膜片上粘接不带凸点的IC芯片，不带凸点的IC芯片上的焊盘与第二圈内引脚之间焊线连接，形成键合线。
所述的绕圈排列的内引脚包括第一圈内引脚、第二圈内引脚、第三圈内引脚及第四圈内引脚，每圈之间通过中筋和边筋相连接，同一圈的内引脚之间相连接。
所述引线框架每边的内引脚平行排列。
所述引线框架每边的内引脚交错排列。
所述的IC芯片为倒装上芯。
本实用新型的多圈QFN引线框架设计，可以比同样面积的单排引线框架的引脚数设计增加40%以上； IC芯片封装件倒装上芯，由于凸点与框架（基板、芯片）直接接触，其特点是热传导距离短，具有较好的热性能，减小了电路内部焊接电感和电容，使信号传输快，失真小，具有良好的电性能和良好的高频性能。另外，倒装上芯的凸点＋助焊剂的高度远小于焊线弧高，因此，封装产品厚度可以低于0.5mm。避免了焊线的交丝和开路，提高了测试良率和可靠性。
附图说明
图1为本实用新型结构示意图；
图2为本实用新型腐蚀后的剖面示意图；
图3为本实用新型磨削分离引脚后剖面示意图；
图4为激光分离引脚后剖面示意图；
图5为本实用新型内引脚平行排列俯视图；
图6为本实用新型内引脚交错排列俯视图。
具体实施方式
下面结合附图对本实用新型进行详细说明：
一种多圈排列无载体双IC芯片封装件，包括引线框架、内引脚、IC芯片及塑封体，引线框架采用无载体引线框架，引线框架的四边呈数圈排列有引线框架内引脚，包括第一圈内引脚8、第二圈内引脚9、第三圈内引脚16及第四圈内引脚18，每圈之间通过中筋g和边筋f相连接，同一圈的内引脚之间相连接。引线框架四边a、b、c、d的每边区域的内引脚平行排列，或者交错排列。
IC芯片设有带凸点的IC芯片3和不带凸点的IC芯片7，带凸点的IC芯片3为倒装上芯，凸点4粘接在第一圈内引脚8上，带凸点的IC芯片3背面带有粘片胶13，粘片胶或胶膜片上粘接不带凸点的IC芯片7，不带凸点的IC芯片7上的焊盘与第二圈内引脚9之间焊线连接，形成键合线11。
首先,在带凸点的IC芯片3架上印刷上焊料2，接着将带凸点的IC芯片3倒装上芯并回流焊，使带凸点的IC芯片3上的凸点4及焊料2和第一内引脚8进行充分结合；其次,使用下填料将带凸点的IC芯片3上的凸点4及第一内引脚8包裹并烘烤；然后,在带凸点的IC芯片3背面使用绝缘胶13进行不带凸点的IC芯片7的第二次上芯；接着,使用传统压焊工艺,通过键合线11将不带凸点的IC芯片7上的焊点和第二内引脚9导通连接；由带凸点的IC芯片3及凸点4、第一圈内引脚8、不带凸点的IC芯片7、键合线11、第二圈内引脚9、第三圈内引脚16及第四圈内引脚18构成电路的电源和信号通道。通过塑封，塑封体12包围了引线框架、焊料2、带凸点的IC芯片3、凸点4、绝缘胶13、第一圈内引脚8、第二圈内引脚9、、凹坑14、键合线11构成电路整体，并对带凸点的IC芯片3和不带凸点的IC芯片7、键合线11起到保护和支撑作用。
然后进行后固化、打印。将打印完的产品框架底部进行腐蚀和磨削结合方法或激光切割,达到分离互相连接引脚的目的。
最后通过切割分离产品入盘，测试、编带完成四边扁平无引脚多圈排列的产品生产。

Claims (6)

1.一种多圈排列无载体双IC芯片封装件，包括引线框架、内引脚、IC芯片及塑封体，引线框架四边呈数圈排列有引线框架内引脚，其特征在于所述引线框架采用无载体引线框架，所述IC芯片设有带凸点的IC芯片（3）和不带凸点的IC芯片（7），带凸点的IC芯片（3）的凸点（4）设置在第一圈内引脚（8）上，带凸点的IC芯片（3）背面设有粘片胶（13），粘片胶或胶膜片上粘接不带凸点的IC芯片（7），不带凸点的IC芯片（7）上的焊盘与第二圈内引脚（9）之间焊线连接，形成键合线（11）。
2.根据权利要求1所述的多圈排列无载体双IC芯片封装件，其特征在于所述的绕圈排列的内引脚包括第一圈内引脚（8）、第二圈内引脚（9）、第三圈内引脚（16）及第四圈内引脚（18），每圈之间通过中筋（g）和边筋（f）相连接，同一列的内引脚之间相连接。
3.根据权利要求1或2所述的多圈排列无载体双IC芯片封装件，其特征在于所述引线框架每边（a、b、c、d）的内引脚平行排列。
4.根据权利要求3所述的多圈排列无载体双IC芯片封装件，其特征在于所述引线框架每边（a、b、c、d）的内引脚交错排列。
5.根据权利要求1或2所述的多圈排列无载体双IC芯片封装件，其特征在于所述的IC芯片（3）的凸点（4）连接在第一圈内引脚（8）上。
6.根据权利要求5所述的多圈排列无载体双IC芯片封装件，其特征在于所述的带凸点的IC芯片（3）为倒装上芯。
CN201120228061.5U 2011-06-30 2011-06-30 多圈排列无载体双ic芯片封装件 Expired - Fee Related CN202178252U (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102231376A (zh) * 2011-06-30 2011-11-02 天水华天科技股份有限公司 多圈排列无载体双ic芯片封装件及其生产方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102231376A (zh) * 2011-06-30 2011-11-02 天水华天科技股份有限公司 多圈排列无载体双ic芯片封装件及其生产方法
CN102231376B (zh) * 2011-06-30 2013-06-26 天水华天科技股份有限公司 多圈排列无载体双ic芯片封装件及其生产方法

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