CN201523004U - 一种小载体四面扁平无引脚封装件 - Google Patents

一种小载体四面扁平无引脚封装件 Download PDF

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CN201523004U
CN201523004U CN200920144093XU CN200920144093U CN201523004U CN 201523004 U CN201523004 U CN 201523004U CN 200920144093X U CN200920144093X U CN 200920144093XU CN 200920144093 U CN200920144093 U CN 200920144093U CN 201523004 U CN201523004 U CN 201523004U
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carrier
pins
packaging part
chip
pin
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郭小伟
慕蔚
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Xi'an TianSheng Electronics Co., Ltd.
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Tianshui Huatian Technology Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

一种小载体四面扁平无引脚封装件,包括引线框架载体、粘片胶、IC芯片、IC芯片上的焊盘、键合线及塑封体,其特征在于在切割分离前,所有内引脚向内延伸与所述载体相连,载体与内引脚之间设有凹槽,内引脚底部设有凹槽,载体背面设有一圈防溢料凹槽。本实用新型的特点是载体缩小,在切割分离前,内引脚向内延伸与载体相连,内引脚与载体相连处有0.10mm的凹坑,凹坑外的引脚长度比普通QFN引脚长1mm,并且载体下部有一圈防溢料槽,可避免溢料继续向载体背面扩散。

Description

一种小载体四面扁平无引脚封装件
技术领域
本实用新型涉及电子信息自动化元器件制造技术领域,尤其涉及到一种小载体四面扁平无引脚封装件。
背景技术
近年来,移动通信和移动计算机领域的便捷式电子机器市场火爆,直接推动了小型封装和高密度组装技术的发展。同时,也对小型封装技术提出了一系列严格要求,诸如,要求封装外形尺寸尽量缩小,尤其是封装高度小于1mm;封装后的产品可靠性尽可能提高,为了保护环境适应无铅化焊接,及力图降低成本。小型化封装结构已有多种,如球栅阵列BGA封装等,但是,其内部的布线成本高,远不如QFP可实现低成本化。然而现行的QFP结构内部引出的引线呈羽翼状扇出,占用较大装配面积(手机内装面积十分有限),不能满足要求。2000年JEDEC制定出一种改进型规格,叫做QFN(Quad Flat Non-LeadedPackage),顾名思义,QFN把QFP扇出的引出线折回到封装底部(变成条状接触线),故可节省装配面积,进一步实现小型化。但是目前QFN(0707×0.75-0.50)载体较大,内引脚长度固定,而当IC芯片较小,致使焊线长度长,造成焊线成本较高,制约了产品的利润空间。
实用新型内容
本实用新型的目的就是针对上述QFN缺点,提供一种缩小了载体尺寸,在分离切割前所有的内引脚与载体相连的四面扁平无引脚封装件,从芯片上的焊盘(PAD)到内引脚的距离缩短。相应,从芯片焊盘到内引脚的焊线长度缩短,可降低焊线成本,适合于小芯片四面扁平无引脚产品封装。
本实用新型的目的通过下述技术方案实现:
一种小载体四面扁平无引脚封装件,包括引线框架载体、粘片胶、IC芯片、IC芯片上的焊盘、键合线及塑封体,其特征在于在切割分离前,所有内引脚向内延伸与所述载体相连,载体与内引脚之间设有凹槽,内引脚底部设有凹槽,载体背面设有一圈防溢料凹槽。
本实用新型的小载体四面扁平无引脚封装的特点是载体缩小,在切割分离前,内引脚向内延伸与载体相连,内引脚与载体相连处有0.10mm的凹坑,凹坑外的引脚长度比普通QFN引脚长1mm,并且载体下部有一圈防溢料槽。
附图说明
图1为本实用新型切割前的剖视图;
图2为本实用新型切割后的剖视图;
图3为本实用新型仰视图。
具体实施方式
下面结合附图对本实用新型进行详细说明:
本实用新型包括引线框架载体1,粘片胶2,IC芯片3,芯片3上的焊盘,内引线脚4,键合线5,塑封体6,在切割分离前,所有内引脚4向内延伸与载体1相连,载体1与内引脚4之间设有凹槽7,引线和载体相连处设有切割线10。引线框架载体1上是粘片胶2,粘片胶2为导电胶或绝缘胶,粘片胶2上是IC芯片3,IC芯片3上的焊盘上的键合线5与内引脚4相连,构成了电路的电流和信号通道。塑封料6包围了引线框架载体1、粘片胶2、IC芯片3、IC芯片3上的焊盘与内引脚4连接的键合线5、凹槽7,及内引脚4背面的凹槽9,构成电路整体,对IC芯片3和键合线5起到支撑和保护作用。载体1底部有一圈防溢料凹槽8,防溢料凹槽8接收了流出的溢料,可避免溢料继续向载体1背面扩散。

Claims (2)

1.一种小载体四面扁平无引脚封装件,包括引线框架载体、粘片胶、IC芯片、IC芯片上的焊盘、内引脚、键合线及塑封体,其特征在于在切割分离前,所有内引脚(4)向内延伸与所述引线框架载体(1)相连,载体(1)与内引脚(4)之间设有凹槽(7),内引脚(4)底部设有凹槽(9)。
2.根据权利要求1所述的小载体四面扁平无引脚封装件,其特征在于所述载体(1)背面设有一圈防溢料凹槽(8)。
CN200920144093XU 2009-10-11 2009-10-11 一种小载体四面扁平无引脚封装件 Expired - Fee Related CN201523004U (zh)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101697348A (zh) * 2009-10-11 2010-04-21 天水华天科技股份有限公司 一种小载体四面扁平无引脚封装件及其制备方法
CN107204299A (zh) * 2016-03-17 2017-09-26 东芝存储器株式会社 半导体装置的制造方法及半导体装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101697348A (zh) * 2009-10-11 2010-04-21 天水华天科技股份有限公司 一种小载体四面扁平无引脚封装件及其制备方法
CN107204299A (zh) * 2016-03-17 2017-09-26 东芝存储器株式会社 半导体装置的制造方法及半导体装置
CN107204299B (zh) * 2016-03-17 2019-10-25 东芝存储器株式会社 半导体装置的制造方法及半导体装置

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