CN202150453U - 一种双扁平无载体无引线内引脚交错型ic芯片封装件 - Google Patents
一种双扁平无载体无引线内引脚交错型ic芯片封装件 Download PDFInfo
- Publication number
- CN202150453U CN202150453U CN201120198061U CN201120198061U CN202150453U CN 202150453 U CN202150453 U CN 202150453U CN 201120198061 U CN201120198061 U CN 201120198061U CN 201120198061 U CN201120198061 U CN 201120198061U CN 202150453 U CN202150453 U CN 202150453U
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- CN
- China
- Prior art keywords
- chip
- inner pin
- pin
- frame inner
- carrier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
Claims (2)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201120198061U CN202150453U (zh) | 2011-06-13 | 2011-06-13 | 一种双扁平无载体无引线内引脚交错型ic芯片封装件 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201120198061U CN202150453U (zh) | 2011-06-13 | 2011-06-13 | 一种双扁平无载体无引线内引脚交错型ic芯片封装件 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN202150453U true CN202150453U (zh) | 2012-02-22 |
Family
ID=45591505
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201120198061U Expired - Lifetime CN202150453U (zh) | 2011-06-13 | 2011-06-13 | 一种双扁平无载体无引线内引脚交错型ic芯片封装件 |
Country Status (1)
Country | Link |
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CN (1) | CN202150453U (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102664175A (zh) * | 2012-05-02 | 2012-09-12 | 无锡虹光半导体技术有限公司 | 一种电源转换芯片的多芯片封装结构 |
-
2011
- 2011-06-13 CN CN201120198061U patent/CN202150453U/zh not_active Expired - Lifetime
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102664175A (zh) * | 2012-05-02 | 2012-09-12 | 无锡虹光半导体技术有限公司 | 一种电源转换芯片的多芯片封装结构 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C53 | Correction of patent for invention or patent application | ||
C56 | Change in the name or address of the patentee |
Owner name: HUATIAN TECHNOLOGY (XI'AN) CO., LTD. Free format text: FORMER NAME: XI'AN TIANSHENG ELECTRONICS CO., LTD. |
|
CB03 | Change of inventor or designer information |
Inventor after: Guo Xiaowei Inventor after: Xie Jianyou Inventor after: Ji Jinping Inventor after: Wang Jian Inventor after: Chen Xin Inventor before: Guo Xiaowei Inventor before: Liu Jianjun Inventor before: Chen Xin |
|
COR | Change of bibliographic data |
Free format text: CORRECT: INVENTOR; FROM: GUO XIAOWEI LIU JIANJUN CHEN XIN TO: GUO XIAOWEI XIE JIANYOU JI JINPING WANG JIAN CHEN XIN |
|
CP01 | Change in the name or title of a patent holder |
Address after: 710018 No. five, No. 105, Fengcheng economic and Technological Development Zone, Shaanxi, Xi'an Patentee after: Huatian Technology (Xi'an) Co., Ltd. Address before: 710018 No. five, No. 105, Fengcheng economic and Technological Development Zone, Shaanxi, Xi'an Patentee before: Xi'an TianSheng Electronics Co., Ltd. |
|
CX01 | Expiry of patent term |
Granted publication date: 20120222 |
|
CX01 | Expiry of patent term |