CN202150453U - 一种双扁平无载体无引线内引脚交错型ic芯片封装件 - Google Patents

一种双扁平无载体无引线内引脚交错型ic芯片封装件 Download PDF

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CN202150453U
CN202150453U CN201120198061U CN201120198061U CN202150453U CN 202150453 U CN202150453 U CN 202150453U CN 201120198061 U CN201120198061 U CN 201120198061U CN 201120198061 U CN201120198061 U CN 201120198061U CN 202150453 U CN202150453 U CN 202150453U
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郭小伟
刘建军
陈欣
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Huatian Technology Xian Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

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Abstract

一种双扁平无载体无引线内引脚交错型IC芯片封装件,包括框架内引脚,框架内引脚通过第一DAF膜和第一IC芯片相连,第一IC芯片通过第一键合线和框架内引脚上连接,塑封体包围了框架内引脚、第一DAF膜、第一IC芯片、第一键合线构成了电路的整体,塑封体对第一IC芯片和第一键合线起到了支撑和保护作用,第一IC芯片、第一键合线、框架内引脚构成了电路的电源和信号通道,采用DAF膜粘片,芯片与框架100%结合,生产的良品率极高;具有无载体无引线的特点,芯片直接放于框架之上,节省材料;切割一致性好;打线非常的方便、灵活,避免压焊时短路;引脚节距小,减小封装尺寸。

Description

一种双扁平无载体无引线内引脚交错型IC芯片封装件
技术领域
本实用新型涉及一种芯片封装结构,具体涉及一种双扁平无载体无引线内引脚交错型IC芯片封装件。
背景技术
DFN系列微小形封装集成电路是近几年发展起来的一种新型微小形封装。由于无引脚、贴装占有面积小,安装高度低等特点,为满足手机、MP3、MP4等超薄型电子产品发展的需要应用而生的逐渐成长起来的一种新型封装。该封装由于引线短小、塑封体尺寸小、封装体薄,可以使CPU体积缩小30%-50%。所以它能提供卓越的电性能,同时,它还通过外露的引线框架焊盘提供了出色的散热性能。普通的DFN封装主要存在以下不足:
因为普通的DFN封装,只用于一般产品,没有高可靠性要求,所以使用的引线框架没有专门的防分层缺陷设计要求,使用的封装材料也是一般材料。同时,在制造过程中没有采取防缺陷(分层)工艺措施,所以存在以下不足:
1、集成电路芯片和载体的结合力不好,当受外界环境变化的影响时,会造成产品内部产生分层缺陷,致使性能褪化,甚至失效;
2、载体背面和塑封料的结合力不好,当受外界环境的影响,会造成产品产生缺陷(分层);或外露载体(基岛)上有较厚的溢料,给后续去溢料带来困难,增加了产生分层缺陷的几率;
3、DFN外观第一脚位置不易区分,对封装制造过程和客户使用带来了不必要的麻烦。
实用新型内容
为了克服上述现有技术的缺点,本实用新型的目的是提供一种双扁平无载体无引线内引脚交错型IC芯片封装件,采用DAF膜粘片,芯片与框架100%结合,生产的良品率极高;具有无载体无引线的特点,芯片直接放于框架之上,节省材料;切割一致性好;打线非常的方便、灵活,避免压焊时短路;引脚节距小,减小封装尺寸。
为了达到上述目的,本实用新型采取的技术方案为:
一种双扁平无载体无引线内引脚交错型IC芯片封装件,包括框架内引脚1,框架内引脚1通过第一DAF膜2和第一IC芯片3相连,第一IC芯片3通过第一键合线6和框架内引脚1上连接。
一种双扁平无载体无引线内引脚交错型IC芯片封装件,包括框架内引脚1,框架内引脚1通过第一DAF膜2和第一IC芯片3相连,第一IC芯片3通过第一键合线6和框架内引脚1上连接,第一IC芯片3通过第二DAF膜4和第二IC芯片5相连,第二IC芯片5通过第二键合线7和第一IC芯片3连接,第二IC芯片5通过第三键合线8和框架内引脚1连接。
本实用新型采用DAF膜粘片,芯片与框架100%结合,不会产生偏斜,生产的良品率极高;采用冲压型框架,生产效率高,成本低,开发周期需3个月;具有无载体无引线的特点,芯片直接放于框架之上,可以节省材料;切割一致性好,芯片引脚交叉排列密度高,芯片与引脚接触面积大;该实用新型封装中采用的框架其管脚是交错排列的,管脚密集度非常高,焊打线时直接用键合线从芯片打到管脚内引脚或外引脚上,打线非常的方便、灵活,同时可以避免压焊时造成键合线碰丝而引起的焊线短路;引脚节距0.3mm∽0.65mm,从而大大减小封装尺寸;塑封、切割模具可以共用,每个产品一个模具。
附图说明
图1为本实用新型单芯片封装件的剖面图。
图2为本实用新型单芯片封装件的俯视图。
图3为本实用新型多芯片堆叠式封装件的剖面图。
具体实施方式
下面结合附图对本实用新型作进一步详细的说明。
本实用新型包括单芯片封装、多芯片堆叠式封装。
参照图1和图2,一种双扁平无载体无引线内引脚交错型IC芯片封装件,包括框架内引脚1,框架内引脚1通过第一DAF膜2和第一IC芯片3相连,第一IC芯片3通过第一键合线6和框架内引脚1上连接。第一键合线6直接从第一IC芯片3打到框架内引脚1上,框架内引脚1上是第一DAF膜2,第一DAF膜2上是第一IC芯片3,第一IC芯片3上的焊点与内引脚间的焊线是第一键合线6,塑封体9包围了框架内引脚1、第一DAF膜2、第一IC芯片3、第一键合线6构成了电路的整体,塑封体9对第一IC芯片3和第一键合线6起到了支撑和保护作用,第一IC芯片3、第一键合线6、框架内引脚1构成了电路的电源和信号通道。
参照图3,一种双扁平无载体无引线内引脚交错型IC芯片封装件,包括框架内引脚1,框架内引脚1通过第一DAF膜2和第一IC芯片3相连,第一IC芯片3通过第一键合线6和框架内引脚1上连接,第一IC芯片3通过第二DAF膜4和第二IC芯片5相连,第二IC芯片5通过第二键合线7和第一IC芯片3连接,第二IC芯片5通过第三键合线8和框架内引脚1连接。塑封体9包围了框架内引脚1、第一IC芯片3、第二IC芯片5、第一DAF膜2、第二DAF膜4、第一键合线6、第二键合线7、第三键合线8构成了电路整体。并且塑封体9对第一IC芯片3、第二IC芯片5、第一键合线6、第二键合线7、第三键合线8起到了支撑和保护作用,第一IC芯片3、第二IC芯片5、第一键合线6、第二键合线7、第三键合线8和框架内引脚1构成了电路的电源和信号通道。
无载体封装中芯片尺寸可以非常小,键合线既可以从芯片打到框架内引脚上,也可以从芯片直接打到另一个芯片上,从而大大缩短键合线长度,进而节省材料,并且可以减小封装尺寸。芯片、DAF膜、框架引脚、金线全被塑封体包围成一个整体。
一种双扁平无载体无引线内引脚交错型IC芯片封装件的生产方法,具体如下:
流程1-单芯片封装件
晶圆减薄→划片→上芯(粘片)→压焊→塑封→后固化→电镀→打印→产品分离→检验→包装→入库。
其中的减薄、划片、压焊、塑封、后固化、电镀、打印、包装与常规DFN封装生产相同,其他工艺流程如下:
在“上芯”站中,采用的框架无载体无引线,且内引脚交错排列,上芯时采用DAF膜将芯片直接粘贴于框架管脚上;压焊时,由于框架无引线,所以打线从芯片直接打到管脚上,焊线可以为金线或铜线,并且框架内引脚交错排列,打线时既可以打到内引脚的前端又可以打到后端;产品分离时,通过招标选择供应商制造冲切分离模具、系统,发合格框架空封和带芯片压焊线的模塑半成品供客户试验,满足产品尺寸要求。
流程2-多芯片堆叠封装件
晶圆减薄→划片→上芯(粘片)→压焊→塑封→后固化→电镀→打印→产品分离→检验→包装→入库。
其中减薄、划片、后固化、电镀、打印、包装与常规DFN封装生产相同,其他工艺流程如下:
上芯时,采用无载体无引线的框架,芯片与芯片堆叠放置,下层芯片用DAF膜粘贴于框架上,上层芯片与下层芯片也用DAF膜相连;压焊站中,焊线既可以从芯片打到引脚上,也可以从一个芯片打到另一个芯片上。

Claims (2)

1.一种双扁平无载体无引线内引脚交错型IC芯片封装件,包括框架内引脚(1),其特征在于:框架内引脚(1)通过第一DAF膜(2)和第一IC芯片(3)相连,第一IC芯片(3)通过第一键合线(6)和框架内引脚(1)上连接。
2.一种双扁平无载体无引线内引脚交错型IC芯片封装件,包括框架内引脚(1),其特征在于:框架内引脚(1)通过第一DAF膜(2)和第一IG芯片(3)相连,第一IC芯片(3)通过第一键合线(6)和框架内引脚(1)上连接,第一IC芯片(3)通过第二DAF膜(4)和第二IC芯片(5)相连,第二IC芯片(5)通过第二键合线(7)和第一IC芯片(3)连接,第二IC芯片(5)通过第三键合线(8)和框架内引脚(1)连接。
CN201120198061U 2011-06-13 2011-06-13 一种双扁平无载体无引线内引脚交错型ic芯片封装件 Expired - Lifetime CN202150453U (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102664175A (zh) * 2012-05-02 2012-09-12 无锡虹光半导体技术有限公司 一种电源转换芯片的多芯片封装结构

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102664175A (zh) * 2012-05-02 2012-09-12 无锡虹光半导体技术有限公司 一种电源转换芯片的多芯片封装结构

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Address after: 710018 No. five, No. 105, Fengcheng economic and Technological Development Zone, Shaanxi, Xi'an

Patentee after: Huatian Technology (Xi'an) Co., Ltd.

Address before: 710018 No. five, No. 105, Fengcheng economic and Technological Development Zone, Shaanxi, Xi'an

Patentee before: Xi'an TianSheng Electronics Co., Ltd.

CX01 Expiry of patent term

Granted publication date: 20120222

CX01 Expiry of patent term