CN203103287U - 一种带有方形凹槽的冲压框架的扁平多芯片封装件 - Google Patents

一种带有方形凹槽的冲压框架的扁平多芯片封装件 Download PDF

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CN203103287U
CN203103287U CN201220738085XU CN201220738085U CN203103287U CN 203103287 U CN203103287 U CN 203103287U CN 201220738085X U CN201220738085X U CN 201220738085XU CN 201220738085 U CN201220738085 U CN 201220738085U CN 203103287 U CN203103287 U CN 203103287U
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chip
bonding
lead frame
square groove
bonding wire
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郭小伟
蒲鸿鸣
崔梦
刘卫东
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Huatian Technology Xian Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector

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Abstract

本实用新型公开了一种带有方形凹槽的冲压框架的扁平多芯片封装件，主要由引线框架、方形凹槽、下芯片、上芯片、下粘片胶、上粘片胶、下键合线、中键合线、上键合线和塑封体组成；所述引线框架开有方形凹槽，所述引线框架通过下粘片胶与下芯片粘接，所述下芯片通过上粘片胶与上芯片粘接，所述下键合线连接引线框架和下芯片，所述中键合线连接下粘片胶和上粘片胶，所述上键合线连接上粘片胶和引线框架，所述塑封体包围引线框架、下芯片、上芯片、下粘片胶、上粘片胶、下键合线、中键合线、上键合线，特别是塑封体填充方形凹槽，引线框架、下芯片、上芯片、下键合线、中键合线、上键合线构成电路的电源和信号通道。本实用新型的塑封体与引线框架的结合更牢固，抗分层效果更好。

Description

一种带有方形凹槽的冲压框架的扁平多芯片封装件
技术领域
本实用新型属于集成电路封装技术领域，具体是一种带有方形凹槽的冲压框架的扁平多芯片封装件。
背景技术
QFN（四面扁平无引脚封装）及DFN（双扁平无引脚封装）封装是在近几年随着通讯及便携式小型数码电子产品的产生(数码相机、手机、PC、MP3)而发展起来的、适用于高频、宽带、低噪声、高导热、小体积，高速度等电性要求的中小规模集成电路的封装。我们知道QFN/DFN封装有效地利用了引线脚的封装空间，从而大幅度地提高了封装效率。但目前大部分半导体封装厂商QFN/DFN的制造过程中对于框架的选用都面临一些难题，现有框架为冲压框架和蚀刻框架两种，冲压框架，其模具采用机械法工形成，生产效率高，单颗产品成本较低，但对于一些特殊图形的引线框架，无法选用冲压法加工，例如QFN/DFN/QFP等载体外露的框架，载体与内引脚之间有一定的高度差，形成一定的台阶，冲压法难以实现及控制好该台阶；化学蚀刻框架，其模具费用低，开发周期短，可达到2周～1个月，封装时塑封、切割模具可共用，投入成本低，但其生产效率低，且单颗产品成本较高。
现有QFN/DFN工艺的塑封工序中，由于框架结构的局限性，导致QFN/DFN封装存在以下不足：
1. 集成电路芯片和载体的结合力不好，当受外界环境变化的影响时，会造成产品内部产生分层缺陷，致使性能褪化，甚至失效；
2. 载体背面和塑封料的结合力不好，当受外界环境的影响，会造成产品产生缺陷(分层)；或外露载体（基岛）上有较厚的溢料。
实用新型内容
针对上诉常规冲压框架、蚀刻框架的缺陷，本实用新型提供一种带有方形凹槽的冲压框架的扁平多芯片封装件，其塑封体与引线框架的结合更牢固，抗分层效果更好。。
本实用新型的技术方案是：一种带有方形凹槽的冲压框架的扁平多芯片封装件，主要由引线框架、方形凹槽、下芯片、上芯片、下粘片胶、上粘片胶、下键合线、中键合线、上键合线和塑封体组成；所述引线框架开有方形凹槽，所述引线框架通过下粘片胶与下芯片粘接，所述下芯片通过上粘片胶与上芯片粘接，所述下键合线连接引线框架和下芯片，所述中键合线连接下粘片胶和上粘片胶，所述上键合线连接上粘片胶和引线框架，所述塑封体包围引线框架、下芯片、上芯片、下粘片胶、上粘片胶、下键合线、中键合线、上键合线，特别是塑封体填充方形凹槽，引线框架、下芯片、上芯片、下键合线、中键合线、上键合线构成电路的电源和信号通道。
本实用新型采用一种新型的框架，该框架采用冲压法加工而成，并采用冲压或钻孔的方法在框架上形成方形凹槽，用以替代蚀刻法在框架上蚀刻出台阶从而起到抗分层的作用，集成电路封装过程中塑封体填入方形凹槽中，从而在框架与塑封料之间形成有效的防拖拉结构，使塑封体与框架间的结合力更好，极大的降低了分层的可能性，显著提高产品可靠性。同时解决了以往研磨框架及半腐蚀框架费用高的缺陷，极大的降低了成本。
说明书附图
   图1为引线框架剖面图；
图2为多芯片封装剖面图。
图中，引线框架1、下粘片胶2、下芯片3、下键合线4、方形凹槽5、塑封体6、上粘片胶7、上芯片8、中键合线9、上键合线10。
具体实施方式
如图所示，一种带有方形凹槽的冲压框架的扁平多芯片封装件，主要由引线框架1、方形凹槽5、下芯片3、上芯片8、下粘片胶2、上粘片胶7、下键合线4、中键合线9、上键合线10和塑封体6组成；所述引线框架1开有方形凹槽5，所述引线框架1通过下粘片胶2与下芯片3粘接，所述下芯片3通过上粘片胶7与上芯片8粘接，所述下键合线4连接引线框架1和下芯片3，所述中键合线9连接下粘片胶2和上粘片胶7，所述上键合线10连接上粘片胶7和引线框架1，所述塑封体6包围引线框架1、下芯片3、上芯片8、下粘片胶2、上粘片胶7、下键合线4、中键合线9、上键合线10，特别是塑封体6填充方形凹槽5，引线框架1、下芯片3、上芯片8、下键合线4、中键合线9、上键合线10构成电路的电源和信号通道。
本实用新型也可用于单芯片封装。
本实用新型采用的不同于以往的冲压框架，在引线框架1上用冲孔或钻孔的方法开方形凹槽5后，塑封时塑封体6会自动填入方形凹槽5，在引线框架1与塑封体6之间形成有效的防拖拉结构，大大降低封装件分层情况的发生几率，极大提高产品可靠性，优于传统半蚀刻冲压框架的塑封效果。

Claims (1)

1.一种带有方形凹槽的冲压框架的扁平多芯片封装件，其特征在于：主要由引线框架（1）、方形凹槽（5）、下芯片（3）、上芯片（8）、下粘片胶（2）、上粘片胶（7）、下键合线（4）、中键合线（9）、上键合线（10）和塑封体（6）组成；所述引线框架（1）开有方形凹槽（5），所述引线框架（1）通过下粘片胶（2）与下芯片（3）粘接，所述下芯片（3）通过上粘片胶（7）与上芯片（8）粘接，所述下键合线（4）连接引线框架（1）和下芯片（3），所述中键合线（9）连接下粘片胶（2）和上粘片胶（7），所述上键合线（10）连接上粘片胶（7）和引线框架（1），所述塑封体（6）包围引线框架（1）、下芯片（3）、上芯片（8）、下粘片胶（2）、上粘片胶（7）、下键合线（4）、中键合线（9）、上键合线（10），特别是塑封体（6）填充方形凹槽（5），引线框架（1）、下芯片（3）、上芯片（8）、下键合线（4）、中键合线（9）、上键合线（10）构成电路的电源和信号通道。
CN201220738085XU 2012-12-28 2012-12-28 一种带有方形凹槽的冲压框架的扁平多芯片封装件 Expired - Fee Related CN203103287U (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103021996A (zh) * 2012-12-28 2013-04-03 华天科技（西安）有限公司 一种带有方形凹槽的冲压框架的扁平多芯片封装件及其制作方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103021996A (zh) * 2012-12-28 2013-04-03 华天科技（西安）有限公司 一种带有方形凹槽的冲压框架的扁平多芯片封装件及其制作方法

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