CN201655787U - 半导体封装结构 - Google Patents

半导体封装结构 Download PDF

Info

Publication number
CN201655787U
CN201655787U CN2010201678743U CN201020167874U CN201655787U CN 201655787 U CN201655787 U CN 201655787U CN 2010201678743 U CN2010201678743 U CN 2010201678743U CN 201020167874 U CN201020167874 U CN 201020167874U CN 201655787 U CN201655787 U CN 201655787U
Authority
CN
China
Prior art keywords
chip
semiconductor
encapsulation
semiconductor chip
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CN2010201678743U
Other languages
English (en)
Inventor
阮春燕
陈松
马慧舒
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Semiconductor China R&D Co Ltd
Samsung Electronics Co Ltd
Original Assignee
Samsung Semiconductor China R&D Co Ltd
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Semiconductor China R&D Co Ltd, Samsung Electronics Co Ltd filed Critical Samsung Semiconductor China R&D Co Ltd
Priority to CN2010201678743U priority Critical patent/CN201655787U/zh
Application granted granted Critical
Publication of CN201655787U publication Critical patent/CN201655787U/zh
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本实用新型提供一种半导体封装结构，其特征在于所述半导体封装结构包括：半导体芯片，半导体芯片上设置有多个接合焊盘；塑封料，包封半导体芯片，芯片背面暴露于空气中，塑封料上形成有与外界电连接所需要的图案，所述图案上形成有暴露接合焊盘的通孔；导电材料，填充所述通孔，用于将焊盘与外部电连接。所述多个接合焊盘以矩阵形式排列。所述半导体封装结构利用模塑通孔技术并采用无衬底封装，减小了封装尺寸，缩短了互连距离，具有优良的电信号连接和良好的散热性能，实现了低成本的芯片尺寸封装。

Description

半导体封装结构
技术领域
本实用新型涉及一种半导体封装结构，具体地讲，涉及一种利用模塑通孔技术并采用无衬底封装的半导体封装结构。
背景技术
近年来，随着半导体技术的不断进步，电子产品朝着轻薄、小巧的方向发展。而在电子产品的制造过程中，半导体芯片的封装对最终的产品的尺寸及性能有着重要的影响。因此，对半导体器件的封装提出了越来越高的要求。
在传统的半导体封装结构中，引线键合(wire bonding)是一种常用的封装形式。图1是示出引线键合封装结构的示意图。参照图1，芯片通过胶或薄膜粘在基板上并由基板支撑，芯片通过金线与基板实现互连，基板通过内部走线实现位置再分布，基板背面贴有焊球以实现封装器件与外部系统器件的电气互连，芯片由塑胶包封，从而得到保护。然而，这种封装结构的问题在于由于使用引线键合，互连距离较长，封装结构的厚度较大，难以实现封装件薄小化的要求，且由于使用金线，也产生制造成本较高的问题。此外，这种封装结构的散热性能较差，且由于导线的电阻会造成信号延迟，从而降低了芯片的电学性能。
倒装片(flip chip)是另一种传统的封装形式。图2是示出倒装片封装结构的示意图。如图2所示，芯片通过焊球与基板倒装互连。倒装片封装结构具有优良的电学性能及封装尺寸小等优点，然而，倒装片封装成本高，价格昂贵。
因此，需要散热性能好、具有优良的电学性能且封装成本较低的封装结构。
实用新型内容
本实用新型的目的在于提供一种半导体封装结构，其特征在于所述半导体封装结构包括：半导体芯片，半导体芯片上设置有多个接合焊盘；塑封料，包封半导体芯片，芯片背面暴露于空气中，塑封料上形成有与外界电连接所需要的图案，所述图案上形成有暴露接合焊盘的通孔；导电材料，填充所述通孔，用于将焊盘与外部电连接。所述多个接合焊盘以矩阵形式排列。与外界电连接所需要的图案可以是球形栅格阵列封装的焊盘或智能卡接触面。
附图说明
通过下面结合附图进行的描述，本实用新型的上述和其他目的和特点将会变得更加清楚，其中：
图1是示出引线键合封装结构的示意图；
图2是示出倒装片封装结构的示意图；
图3是示出形成在临时载板上的芯片的示意图；
图4是示出包封芯片的塑封料的示意图；
图5是示出在塑封料上形成通孔的示意图；
图6是示出导电材料填充通孔的示意图；
图7是示出去除临时载板后半导体封装结构的示意图。
具体实施方式
以下，参照附图来详细说明本实用新型的实施例。
参照图7，半导体封装结构包括：半导体芯片1，半导体芯片1上设置有多个接合焊盘2，半导体芯片1固定于临时载板5上，临时载板5被去除后，半导体芯片1的背面暴露于空气中；塑封料3，设置在半导体芯片1上，包封半导体芯片1，塑封料上形成有与外界电连接所需要的图案，所述图案上形成有暴露接合焊盘的通孔；导电材料4，填充所述通孔。导电材料4用于将焊盘2与外部电连接。形成临时载板5的材料可包括玻璃或树脂。与外界电连接所需要的图案可以是例如球形栅格阵列封装的焊盘(FBGA ball land)或智能卡接触面(Card contact surface)等。与外界电连接所需要的图案可通过模具成型。
形成半导体封装结构的过程包括如下步骤：参照图3，首先在芯片1上设置多个接合焊盘2，接合焊盘2可以以矩阵形式排列，将芯片1设置在临时载板5上；之后，参照图4，用塑封料3将半导体芯片1包封，并形成与外界电连接所需要的图案；参照图5，在所述图案上形成通孔以暴露接合焊盘；参照图6，用导电材料4填充通孔以与外界实现电连接；最后，参照图7，去除临时载板5，使芯片背面暴露于空气中。
所述半导体封装结构利用模塑通孔技术并采用无衬底封装，减小了封装尺寸，缩短了互连距离，具有优良的电信号连接和良好的散热性能，实现了低成本的芯片尺寸封装。

Claims (3)

1.一种半导体封装结构，其特征在于所述半导体封装结构包括：
半导体芯片，半导体芯片上设置有多个接合焊盘；
塑封料，包封半导体芯片，芯片背面暴露于空气中，塑封料上形成有与外界电连接所需要的图案，所述图案上形成有暴露接合焊盘的通孔；
导电材料，填充所述通孔，用于将焊盘与外部电连接。
2.如权利要求1所述的半导体封装结构，其特征在于，所述多个接合焊盘以矩阵形式排列。
3.如权利要求1所述的半导体封装结构，其特征在于，与外界电连接所需要的图案是球形栅格阵列封装的焊盘或智能卡接触面。
CN2010201678743U 2010-04-06 2010-04-06 半导体封装结构 Expired - Lifetime CN201655787U (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2010201678743U CN201655787U (zh) 2010-04-06 2010-04-06 半导体封装结构

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2010201678743U CN201655787U (zh) 2010-04-06 2010-04-06 半导体封装结构

Publications (1)

Publication Number Publication Date
CN201655787U true CN201655787U (zh) 2010-11-24

Family

ID=43121031

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2010201678743U Expired - Lifetime CN201655787U (zh) 2010-04-06 2010-04-06 半导体封装结构

Country Status (1)

Country Link
CN (1) CN201655787U (zh)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102376655A (zh) * 2011-10-28 2012-03-14 三星半导体(中国)研究开发有限公司 具有金属层的芯片封装结构
CN102610597A (zh) * 2011-01-18 2012-07-25 矽品精密工业股份有限公司 具有发光元件的封装件及其制法
CN103681386A (zh) * 2012-08-31 2014-03-26 南茂科技股份有限公司 半导体结构与其制造方法
WO2017054470A1 (zh) * 2015-09-28 2017-04-06 中芯长电半导体（江阴）有限公司 扇出型晶圆级封装方法
CN111354718A (zh) * 2020-03-23 2020-06-30 江苏中科智芯集成科技有限公司 含多芯片封装结构的芯片排列布线方法、装置及电子设备

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102610597A (zh) * 2011-01-18 2012-07-25 矽品精密工业股份有限公司 具有发光元件的封装件及其制法
CN102376655A (zh) * 2011-10-28 2012-03-14 三星半导体(中国)研究开发有限公司 具有金属层的芯片封装结构
CN103681386A (zh) * 2012-08-31 2014-03-26 南茂科技股份有限公司 半导体结构与其制造方法
US9576820B2 (en) 2012-08-31 2017-02-21 Chipmos Technologies Inc Semiconductor structure and method of manufacturing the same
CN103681386B (zh) * 2012-08-31 2017-04-26 南茂科技股份有限公司 半导体结构与其制造方法
WO2017054470A1 (zh) * 2015-09-28 2017-04-06 中芯长电半导体（江阴）有限公司 扇出型晶圆级封装方法
CN111354718A (zh) * 2020-03-23 2020-06-30 江苏中科智芯集成科技有限公司 含多芯片封装结构的芯片排列布线方法、装置及电子设备
CN111354718B (zh) * 2020-03-23 2022-02-25 江苏中科智芯集成科技有限公司 含多芯片封装结构的芯片排列布线方法、装置及电子设备

Similar Documents

Publication Publication Date Title
CN105428334B (zh) 半导体封装结构
CN102456677B (zh) 球栅阵列封装结构及其制造方法
CN101506975B (zh) 堆叠管芯封装
CN206282838U (zh) 无源器件与有源器件的集成封装结构
US9147600B2 (en) Packages for multiple semiconductor chips
CN106898591A (zh) 一种散热的多芯片框架封装结构及其制备方法
CN201655787U (zh) 半导体封装结构
US20080237833A1 (en) Multi-chip semiconductor package structure
CN202549824U (zh) 芯片封装结构
KR20080005735A (ko) 적층형 반도체 패키지 및 그 제조방법
CN100466246C (zh) 用于封装的柔性基板
CN104347612B (zh) 集成的无源封装、半导体模块和制造方法
CN203055893U (zh) 一种再布线热增强型fcqfn封装器件
CN115832147A (zh) 一种堆叠类封装体结构、工艺及发光芯片器件
US20080237831A1 (en) Multi-chip semiconductor package structure
CN207602549U (zh) 一种三维芯片堆叠芯片尺寸封装结构
CN108573933A (zh) 半导体装置及其制造方法
CN104064557B (zh) 一种芯片背面裸露的重构晶圆结构及制造方法
CN208460760U (zh) 三维系统级封装结构
CN107993992A (zh) 一种三维芯片堆叠芯片尺寸封装结构及制造方法
CN105590904A (zh) 一种指纹识别多芯片封装结构及其制备方法
TWI389296B (zh) 可堆疊式封裝結構及其製造方法及半導體封裝結構
CN205621701U (zh) 一种面阵列无引脚csp封装件
CN100403532C (zh) 散热型球格阵列封装结构
CN203877910U (zh) 一种封装结构

Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
CX01 Expiry of patent term
CX01 Expiry of patent term

Granted publication date: 20101124