CN203589007U - 一种基于框架的多器件smt扁平封装件 - Google Patents

一种基于框架的多器件smt扁平封装件 Download PDF

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CN203589007U
CN203589007U CN201320267292.6U CN201320267292U CN203589007U CN 203589007 U CN203589007 U CN 203589007U CN 201320267292 U CN201320267292 U CN 201320267292U CN 203589007 U CN203589007 U CN 203589007U
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chip
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李万霞
魏海东
李站
王振宇
崔梦
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Huatian Technology Xian Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

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Abstract

本实用新型公开了一种基于框架的多器件SMT扁平封装件，所述封装件主要由引线框架，绝缘胶，芯片，键合线，电感、电阻、电容和封装成品，塑封体组成。所述引线框架通过绝缘胶与芯片连接，引线框架与电感、电阻、电容和封装成品通过电感、电阻、电容和封装成品的引脚连接，所述键合线直接连接芯片和引线框架，塑封体包围了引线框架、绝缘胶、芯片、键合线、电感，电感、电阻、电容和封装成品并构成了电路的整体。本实用新型能有效缩小体积，减轻重量并提高封装件可靠性，抗震能力强，焊点缺陷率低。

Description

一种基于框架的多器件SMT扁平封装件
技术领域
本实用新型属于集成电路封装技术领域，具体是一种基于框架的多器件SMT扁平封装件。
背景技术
电子电路表面组装技术（Surface Mount Technology，SMT），称为表面贴装或表面安装技术。它是一种将无引脚或短引线表面组装元器件（简称SMC/SMD，中文称片状元器件）安装在印制电路板（Printed Circuit Board，PCB）的表面或其它基板的表面上，通过回流焊或浸焊等方法加以焊接组装的电路装连技术。
　　组装密度高、电子产品体积小、重量轻，贴片元件的体积和重量只有传统插装元件的1/10左右，一般采用SMT之后，电子产品体积缩小40%~60%，重量减轻60%~80%；可靠性高、抗震能力强；焊点缺陷率低；高频特性好；减少了电磁和射频干扰；易于实现自动化，提高生产效率；降低成本达30%~50%，节省材料、能源、设备、人力、时间等。
QFN（四面扁平无引脚封装）及DFN（双扁平无引脚封装）封装是在近几年随着通讯及便携式小型数码电子产品的产生(数码相机、手机、PC、MP3)而发展起来的、适用于高频、宽带、低噪声、高导热、小体积，高速度等电性要求的中小规模集成电路的封装。我们知道QFN/DFN封装有效地利用了引线脚的封装空间，从而大幅度地提高了封装效率。
而随着电子产品功能日趋更加完整，所采用的集成电路(IC）已
无穿孔元件，特别是大规模、高集成IC，不得不采用表面贴片元件。而随着产品批量化，生产自动化，厂方要以低成本高产量，出产优质产品以迎合顾客需求及加强市场竞争力。由于技术限制，目前SMT技术只用于基板类封装产品，难以使得框架产品实现SMT技术，即在框架上连接电感、电阻、电容和封装成品等器件。
实用新型内容
就上述现有技术存在的问题，本实用新型提供了一种基于框架的多器件SMT扁平封装件，能有效缩小体积，减轻重量并提高封装件可靠性，抗震能力强，焊点缺陷率低。
一种基于框架的多器件SMT扁平封装件主要由引线框架，绝缘胶，芯片，键合线，电感、电阻、电容和封装成品，塑封体组成。所述引线框架通过绝缘胶与芯片连接，引线框架与电感、电阻、电容和封装成品通过电感、电阻、电容和封装成品的引脚连接，所述键合线直接连接芯片和引线框架，塑封体包围了引线框架、绝缘胶、芯片、键合线、电感, 电感、电阻、电容和封装成品并构成了电路的整体，塑封体对芯片和键合线起到了支撑和保护作用，芯片、键合线、电感、电阻、电容和封装成品、引线框架构成了电路的电源和信号通道。
一种基于框架的多器件SMT扁平封装件的制作工艺的流程：电感、电阻、电容和封装成品的引脚沾锡→晶圆减薄→划片→上芯（粘片）→压焊→塑封→后固化→锡化→ 打印→产品分离→检验→包装→入库。
附图说明
 图1引线框架剖面图；
图2粘接电感、电阻、电容和封装成品后产品剖面图；
图3上芯后产品剖面图；
图4压焊后产品剖面图；
图5塑封后产品剖面图；
图6产品成品剖面图。
图中，1为引线框架，2为绝缘胶，3为芯片，4为键合线，5为电感、电阻、电容和封装成品，6为塑封体。
具体实施方式
下面结合附图对本实用新型做进一步的说明。
如图6所示，一种基于框架的多器件SMT扁平封装件主要由引线框架1，绝缘胶2，芯片3，键合线4，电感、电阻、电容和封装成品5，塑封体6组成。所述引线框架1通过绝缘胶2与芯片3连接，引线框架1与电感、电阻、电容和封装成品5通过电感、电阻、电容和封装成品5的引脚连接，所述键合线4直接连接芯片3和引线框架1，塑封体6包围了引线框架1、绝缘胶2、芯片3、键合线4、电感, 电感、电阻、电容和封装成品5并构成了电路的整体，塑封体6对芯片3和键合线4起到了支撑和保护作用，芯片3、键合线4、电感、电阻、电容和封装成品5、引线框架1构成了电路的电源和信号通道。
一种基于框架的多器件SMT扁平封装件的制作工艺的流程：电感、电阻、电容和封装成品的引脚沾锡→晶圆减薄→划片→上芯（粘片）→压焊→塑封→后固化→锡化→ 打印→产品分离→检验→包装→入库。
如图1到图6所示，一种基于框架的多器件SMT扁平封装件的制作工艺的主要步骤如下：
1、电感、电阻、电容和封装成品5引脚沾锡，与引线框架1相连；
2、减薄、划片：减薄厚度50μm～200μm，150μm以上晶圆同普通QFN划片工艺，但厚度在150μm以下晶圆，使用双刀划片机及其工艺；
3、上芯（粘片）：采用绝缘胶2将芯片3与引线框架1相连；
4、压焊：压焊同常规QFN/DFN工艺相同；
5、塑封、后固化、磨胶、锡化、打印、产品分离、检验、包装等均与常规QFN/DFN工艺相同。

Claims (1)

1.一种基于框架的多器件SMT扁平封装件，其特征在于：主要由引线框架（1），绝缘胶（2），芯片（3），键合线（4），电感、电阻、电容和封装成品（5），塑封体（6）组成；所述引线框架（1）通过绝缘胶（2）与芯片（3）连接，引线框架（1）与电感、电阻、电容和封装成品（5）通过电感、电阻、电容和封装成品（5）的引脚连接，所述键合线（4）直接连接芯片（3）和引线框架（1），塑封体（6）包围了引线框架（1）、绝缘胶（2）、芯片（3）、键合线（4）、电感, 电感、电阻、电容和封装成品（5）并构成了电路的整体，芯片（3）、键合线（4）、电感、电阻、电容和封装成品（5）、引线框架（1）构成了电路的电源和信号通道。
CN201320267292.6U 2013-05-16 2013-05-16 一种基于框架的多器件smt扁平封装件 Expired - Lifetime CN203589007U (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103325756A (zh) * 2013-05-16 2013-09-25 华天科技（西安）有限公司 一种基于框架的多器件smt扁平封装件及其制作工艺

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103325756A (zh) * 2013-05-16 2013-09-25 华天科技（西安）有限公司 一种基于框架的多器件smt扁平封装件及其制作工艺

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