CN103065977A - 一种基于框架可实现smt的扁平封装件制作工艺 - Google Patents

一种基于框架可实现smt的扁平封装件制作工艺 Download PDF

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CN103065977A
CN103065977A CN2012105492836A CN201210549283A CN103065977A CN 103065977 A CN103065977 A CN 103065977A CN 2012105492836 A CN2012105492836 A CN 2012105492836A CN 201210549283 A CN201210549283 A CN 201210549283A CN 103065977 A CN103065977 A CN 103065977A
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framework
smt
chip
manufacturing craft
technique
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李万霞
谢建友
崔梦
魏海东
李站
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Huatian Technology Xian Co Ltd
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Huatian Technology Xian Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Semiconductor Integrated Circuits (AREA)

Abstract

本发明涉及一种基于框架可实现SMT的扁平封装件制作工艺，属于集成电路封装技术领域，在框架上电感和引脚直接连接，芯片和电感用绝缘胶相连，后将芯片用金线和引脚连接，从而形成电路整体，可以有效缩小体积，减轻重量并提高封装件可靠性、抗震能力强，焊点缺陷率低。

Description

一种基于框架可实现SMT的扁平封装件制作工艺
 
技术领域
本发明涉及一种基于框架可实现SMT的扁平封装件制作工艺，属于集成电路封装技术领域。 
背景技术
电子电路表面组装技术（Surface Mount Technology，SMT），称为表面贴装或表面安装技术。它是一种将无引脚或短引线表面组装元器件（简称SMC/SMD，中文称片状元器件）安装在印制电路板（Printed Circuit Board，PCB）的表面或其它基板的表面上，通过回流焊或浸焊等方法加以焊接组装的电路装连技术。
组装密度高、电子产品体积小、重量轻，贴片元件的体积和重量只有传统插装元件的1/10左右，一般采用SMT之后，电子产品体积缩小40%~60%，重量减轻60%~80%。可靠性高、抗震能力强。焊点缺陷率低。
高频特性好。减少了电磁和射频干扰。易于实现自动化，提高生产效率。降低成本达30%~50%。节省材料、能源、设备、人力、时间等。
QFN（四面扁平无引脚封装）及DFN（双扁平无引脚封装）封装是在近几年随着通讯及便携式小型数码电子产品的产生(数码相机、手机、PC、MP3)而发展起来的、适用于高频、宽带、低噪声、高导热、小体积，高速度等电性要求的中小规模集成电路的封装。我们知道QFN/DFN封装有效地利用了引线脚的封装空间，从而大幅度地提高了封装效率。
而随着电子产品功能日趋更加完整，所采用的集成电路(IC）已无穿孔元件，特别是大规模、高集成IC，不得不采用表面贴片元件。而随着产品批量化，生产自动化，厂方要以低成本高产量，出产优质产品以迎合顾客需求及加强市场竞争力。由于技术限制，目前SMT技术只用于基板类封装产品，我司现使用一种新的生产方法，使得框架产品实现SMT技术。
发明内容
基于上述问题，本发明采用一种基于框架可实现SMT的扁平封装件制作工艺，在框架上电感和引脚直接连接，芯片和电感用绝缘胶相连，后将芯片用金线和引脚连接，从而形成电路整体，可以有效缩小体积，减轻重量并提高封装件可靠性、抗震能力强。焊点缺陷率低。
本发明采用的技术方案：一种基于框架可实现SMT的扁平封装件制作工艺，按照下面步骤进行：
第一步、方形电感引脚沾锡，并与引线框架相连；
第二步、减薄、划片：晶圆厚度50μm～200μm，厚度在150μm以上晶圆同普通QFN划片工艺；厚度在150μm以下晶圆，使用双刀划片机及其工艺；
第三步、上芯：采用绝缘胶将芯片与方形电感相连；
第四步、压焊：压焊同常规QFN/DFN工艺相同；
第五步、塑封，后固化、磨胶、锡化、打印、产品分离、检验、包装等均与常规QFN/DFN工艺相同。
本发明的有益效果：在框架上电感和引脚直接连接，芯片和电感用绝缘胶相连，后将芯片用金线和引脚连接，从而形成电路整体，可以有效缩小体积，减轻重量并提高封装件可靠性、抗震能力强，焊点缺陷率低。
附图说明
   图1  引线框架剖面图；
图2  粘接电感后产品剖面图；
图3  上芯后产品剖面图；
图4  压焊后产品剖面图；
图5  塑封后产品剖面图；
图6  产品成品剖面图；
图中：1—引线框架、2—绝缘胶、3—芯片、4—键合线、5—方形电感、6—塑封体。
具体实施方式
下面结合附图和实施例对本发明做进一步说明，以方便技术人员理解。
如图1-6所示：一种基于框架可实现SMT的扁平封装件制作工艺，按照下面步骤进行；
实施例1
第一步、方形电感5引脚沾锡，并与引线框架1相连；
第二步、减薄、划片：晶圆厚度50μm，厚度在150μm以下晶圆，使用双刀划片机及其工艺；
第三步、上芯：采用绝缘胶2将芯片与方形电感5相连；
第四步、压焊：压焊同常规QFN/DFN工艺相同；
第五步、塑封，后固化、磨胶、锡化、打印、产品分离、检验、包装等均与常规QFN/DFN工艺相同。
实施例2
第一步、方形电感5引脚沾锡，并与引线框架1相连；
第二步、减薄、划片：晶圆厚度130μm，厚度在150μm以下晶圆，使用双刀划片机及其工艺；
第三步、上芯：采用绝缘胶2将芯片与方形电感5相连；
第四步、压焊：压焊同常规QFN/DFN工艺相同；
第五步、塑封，后固化、磨胶、锡化、打印、产品分离、检验、包装等均与常规QFN/DFN工艺相同。
实施例3
第一步、方形电感5引脚沾锡，并与引线框架1相连；
第二步、减薄、划片：减薄厚度200μm，厚度在150μm以上晶圆同普通QFN划片工艺； 
第三步、上芯：采用绝缘胶2将芯片与方形电感5相连；
第四步、压焊：压焊同常规QFN/DFN工艺相同；
第五步、塑封，后固化、磨胶、锡化、打印、产品分离、检验、包装等均与常规QFN/DFN工艺相同。
本发明通过具体实施过程进行说明的，在不脱离本发明范围的情况下，还可以对本发明专利进行各种变换及等同代替，因此，本发明专利不局限于所公开的具体实施过程，而应当包括落入本发明专利权利要求范围内的全部实施方案。

Claims (1)

1.一种基于框架可实现SMT的扁平封装件制作工艺，其特征在于：按照下面步骤进行：
第一步、方形电感引脚沾锡，并与引线框架相连；
第二步、减薄、划片：晶圆厚度50μm～200μm，厚度在150μm以上晶圆同普通QFN划片工艺；厚度在150μm以下晶圆，使用双刀划片机及其工艺；
第三步、上芯：采用绝缘胶将芯片与方形电感相连；
第四步、压焊：压焊同常规QFN/DFN工艺相同；
第五步、塑封，后固化、磨胶、锡化、打印、产品分离、检验、包装等均与常规QFN/DFN工艺相同。
CN2012105492836A 2012-12-18 2012-12-18 一种基于框架可实现smt的扁平封装件制作工艺 Pending CN103065977A (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101064208A (zh) * 2006-03-17 2007-10-31 索尼株式会社 半导体模块、电感器元件及其制作方法
CN101383342A (zh) * 2007-09-05 2009-03-11 半导体元件工业有限责任公司 半导体元器件及制造方法
US20120104588A1 (en) * 2006-12-27 2012-05-03 Nan-Jang Chen Method for manufacturing leadframe, packaging method for using the leadframe and semiconductor package product
CN202259243U (zh) * 2011-06-13 2012-05-30 西安天胜电子有限公司 一种球焊后框架贴膜封装件
CN102738365A (zh) * 2012-06-05 2012-10-17 华天科技（西安）有限公司 一种基于dfn、qfn的新型led封装件及其制作方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101064208A (zh) * 2006-03-17 2007-10-31 索尼株式会社 半导体模块、电感器元件及其制作方法
US20120104588A1 (en) * 2006-12-27 2012-05-03 Nan-Jang Chen Method for manufacturing leadframe, packaging method for using the leadframe and semiconductor package product
CN101383342A (zh) * 2007-09-05 2009-03-11 半导体元件工业有限责任公司 半导体元器件及制造方法
CN202259243U (zh) * 2011-06-13 2012-05-30 西安天胜电子有限公司 一种球焊后框架贴膜封装件
CN102738365A (zh) * 2012-06-05 2012-10-17 华天科技（西安）有限公司 一种基于dfn、qfn的新型led封装件及其制作方法

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Application publication date: 20130424