CN103021995A - 一种基于圆柱形电感可实现smt的单芯片封装件及其制作工艺 - Google Patents

一种基于圆柱形电感可实现smt的单芯片封装件及其制作工艺 Download PDF

Info

Publication number
CN103021995A
CN103021995A CN2012105827793A CN201210582779A CN103021995A CN 103021995 A CN103021995 A CN 103021995A CN 2012105827793 A CN2012105827793 A CN 2012105827793A CN 201210582779 A CN201210582779 A CN 201210582779A CN 103021995 A CN103021995 A CN 103021995A
Authority
CN
China
Prior art keywords
chip
lead frame
cylindrical
inductance
packaging piece
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN2012105827793A
Other languages
English (en)
Inventor
李万霞
魏海东
崔梦
李站
王霞
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huatian Technology Xian Co Ltd
Original Assignee
Huatian Technology Xian Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huatian Technology Xian Co Ltd filed Critical Huatian Technology Xian Co Ltd
Priority to CN2012105827793A priority Critical patent/CN103021995A/zh
Publication of CN103021995A publication Critical patent/CN103021995A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Coils Or Transformers For Communication (AREA)

Abstract

本发明涉及一种基于圆柱形电感可实现SMT的单芯片封装件及其制作工艺，属于集成电路封装技术领域，芯片封装件包括引线框架、绝缘胶、芯片、键合线、圆柱形电感、塑封体；其中芯片与引线框架通过绝缘胶相连，圆柱形电感与框架通过圆柱形电感的引脚相连，键合线直接从芯片打到引线框架上，引线框架上是圆柱形电感，圆柱形电感上市绝缘胶，绝缘胶上是芯片，芯片上的焊点与内引脚间的焊线是键合线，塑封体对芯片的键合线起到了支撑和保护作用，塑封体包围了引线框架、绝缘胶、芯片、键合线、圆柱形电感并一起构成了电路的整体，芯片、键合线、圆柱形电感、引线框架构成了电路的电源和信号通道。本发明可以有效缩小体积，减轻重量并提高封装件可靠性、抗震能力强，焊点缺陷率低。

Description

一种基于圆柱形电感可实现SMT的单芯片封装件及其制作工艺
技术领域
本发明涉及一种基于圆柱形电感可实现SMT的单芯片封装件及其制作工艺，属于集成电路封装技术领域。 
背景技术
电子电路表面组装技术（Surface Mount Technology，SMT），称为表面贴装或表面安装技术。它是一种将无引脚或短引线表面组装元器件（简称SMC/SMD，中文称片状元器件）安装在印制电路板（Printed Circuit Board，PCB）的表面或其它基板的表面上，通过回流焊或浸焊等方法加以焊接组装的电路装连技术。
　　组装密度高、电子产品体积小、重量轻，贴片元件的体积和重量只有传统插装元件的1/10左右，一般采用SMT之后，电子产品体积缩小40%~60%，重量减轻60%~80%。可靠性高、抗震能力强。焊点缺陷率低。
　　高频特性好。减少了电磁和射频干扰。易于实现自动化，提高生产效率。降低成本达30%~50%。节省材料、能源、设备、人力、时间等。
QFN（四面扁平无引脚封装）及DFN（双扁平无引脚封装）封装是在近几年随着通讯及便携式小型数码电子产品的产生(数码相机、手机、PC、MP3)而发展起来的、适用于高频、宽带、低噪声、高导热、小体积，高速度等电性要求的中小规模集成电路的封装。我们知道QFN/DFN封装有效地利用了引线脚的封装空间，从而大幅度地提高了封装效率。
而随着电子产品功能日趋更加完整，所采用的集成电路(IC）已无穿孔元件，特别是大规模、高集成IC，不得不采用表面贴片元件。而随着产品批量化，生产自动化，厂方要以低成本高产量，出产优质产品以迎合顾客需求及加强市场竞争力。由于技术限制，目前SMT技术只用于基板类封装产品，我司现使用一种新的生产方法，使得框架产品实现SMT技术。
发明内容
基于上述问题，本发明采用一种基于圆柱形电感可实现SMT的单芯片封装件及其制作工艺，在框架上电感和引脚直接连接，芯片和电感用绝缘胶相连，后将芯片用金线和引脚连接，从而形成电路整体，可以有效缩小体积，减轻重量并提高封装件可靠性、抗震能力强。焊点缺陷率低。
本发明采用的技术方案：一种基于圆柱形电感可实现SMT的单芯片封装件包括：引线框架、绝缘胶、芯片、键合线、圆柱形电感、塑封体；其中芯片与引线框架通过绝缘胶相连，圆柱形电感与框架通过圆柱形电感的引脚相连，键合线直接从芯片打到引线框架上，引线框架上是圆柱形电感，圆柱形电感上是绝缘胶，绝缘胶上是芯片，芯片上的焊点与内引脚间的焊线是键合线，对芯片的键合线起到了支撑和保护作用塑封体包围了引线框架、绝缘胶、芯片、键合线、圆柱形电感并一起构成了电路的整体，芯片、键合线、圆柱形电感、引线框架构成了电路的电源和信号通道。
一种基于圆柱形电感可实现SMT的单芯片封装件的制作工艺，按照以下步骤进行：
第一步、圆柱形电感引脚沾锡，与框架相连；
第二步、减薄、划片：减薄厚度50μm～200μm，150μm以上晶圆同普通QFN划片工艺，但厚度在150μm以下晶圆，使用双刀划片机及其工艺；
第三步、上芯粘片：采用绝缘胶将芯片与电感相连；
第四步、压焊：压焊同常规QFN/DFN工艺相同；
第五步、塑封，后固化、磨胶、锡化、打印、产品分离、检验、包装等均与常规QFN/DFN工艺相同。
本发明的有益效果：在框架上电感和引脚直接连接，芯片和电感用绝缘胶相连，后将芯片用金线和引脚连接，从而形成电路整体，可以有效缩小体积，减轻重量并提高封装件可靠性、抗震能力强，焊点缺陷率低。
附图说明
图1  引线框架剖面图；
图2  粘接电感后产品剖面图；
图3  上芯后产品剖面图；
图4  压焊后产品剖面图；
图5  塑封后产品剖面图；
图6  产品成品剖面图。
图中：1—引线框架、2—绝缘胶、3—芯片、4—键合线、5—圆柱形电感、6—塑封体。
具体实施方式
下面结合附图对本发明做进一步说明，以方便技术人员理解。
如图1所示：一种基于圆柱形电感可实现SMT的单芯片封装件包括：引线框架1、绝缘胶2、芯片3、键合线4、圆柱形电感5、塑封体6；其中芯片3与引线框架1通过绝缘胶2相连，圆柱形电感5与框架1通过圆柱形电感5的引脚相连，键合线4直接从芯片3打到引线框架1上，引线框架1上是圆柱形电感5，圆柱形电感5上市绝缘胶2，绝缘胶2上是芯片3，芯片3上的焊点与内引脚间的焊线是键合线4，塑封体6对芯片3的键合线4起到了支撑和保护作用，塑封体6包围了引线框架1、绝缘胶2、芯片3、键合线4、圆柱形电感5并一起构成了电路的整体，芯片3、键合线4、圆柱形电感5、引线框架1构成了电路的电源和信号通道。
一种基于圆柱形电感可实现SMT的单芯片封装件的制作工艺，按照以下步骤进行：
第一步、圆柱形电感引脚沾锡，与框架相连；
第二步、减薄、划片：减薄厚度50μm～200μm，150μm以上晶圆同普通QFN划片工艺，但厚度在150μm以下晶圆，使用双刀划片机及其工艺；
第三步、上芯粘片：采用绝缘胶将芯片与电感相连；
第四步、压焊：压焊同常规QFN/DFN工艺相同；
第五步、塑封，后固化、磨胶、锡化、打印、产品分离、检验、包装等均与常规QFN/DFN工艺相同。
本发明通过具体实施过程进行说明的，在不脱离本发明范围的情况下，还可以对本发明专利进行各种变换及等同代替，因此，本发明专利不局限于所公开的具体实施过程，而应当包括落入本发明专利权利要求范围内的全部实施方案。

Claims (2)

1.一种基于圆柱形电感可实现SMT的单芯片封装件，其特征在于：单芯片封装件包括引线框架、绝缘胶、芯片、键合线、圆柱形电感、塑封体；其中芯片与引线框架通过绝缘胶相连，圆柱形电感与框架通过圆柱形电感的引脚相连，键合线直接从芯片打到引线框架上，引线框架上是圆柱形电感，圆柱形电感上是绝缘胶，绝缘胶上是芯片，芯片上的焊点与内引脚间的焊线是键合线，塑封体包围了引线框架、绝缘胶、芯片、键合线、圆柱形电感并一起构成了电路的整体，芯片、键合线、圆柱形电感、引线框架构成了电路的电源和信号通道。
2.一种基于圆柱形电感可实现SMT的单芯片封装件的制作工艺，其特征在于：所述制作工艺是按照以下步骤进行：
第一步、圆柱形电感引脚沾锡，与框架相连；
第二步、减薄、划片：减薄厚度50μm～200μm，150μm以上晶圆同普通QFN划片工艺，但厚度在150μm以下晶圆，使用双刀划片机及其工艺；
第三步、上芯粘片：采用绝缘胶将芯片与电感相连；
第四步、压焊：压焊同常规QFN/DFN工艺相同；
第五步、塑封，后固化、磨胶、锡化、打印、产品分离、检验、包装等均与常规QFN/DFN工艺相同。
CN2012105827793A 2012-12-28 2012-12-28 一种基于圆柱形电感可实现smt的单芯片封装件及其制作工艺 Pending CN103021995A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2012105827793A CN103021995A (zh) 2012-12-28 2012-12-28 一种基于圆柱形电感可实现smt的单芯片封装件及其制作工艺

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2012105827793A CN103021995A (zh) 2012-12-28 2012-12-28 一种基于圆柱形电感可实现smt的单芯片封装件及其制作工艺

Publications (1)

Publication Number Publication Date
CN103021995A true CN103021995A (zh) 2013-04-03

Family

ID=47970425

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2012105827793A Pending CN103021995A (zh) 2012-12-28 2012-12-28 一种基于圆柱形电感可实现smt的单芯片封装件及其制作工艺

Country Status (1)

Country Link
CN (1) CN103021995A (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103325756A (zh) * 2013-05-16 2013-09-25 华天科技（西安）有限公司 一种基于框架的多器件smt扁平封装件及其制作工艺
CN105609231A (zh) * 2015-12-24 2016-05-25 合肥祖安投资合伙企业(有限合伙) 叠层电感器及其制造方法以及叠层封装组件
CN115841958A (zh) * 2023-02-20 2023-03-24 广州丰江微电子有限公司 提高引线框架与塑封料结合力的方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101383342A (zh) * 2007-09-05 2009-03-11 半导体元件工业有限责任公司 半导体元器件及制造方法
US20100207244A1 (en) * 2001-04-06 2010-08-19 Oki Electric Industry Co., Ltd. Semiconductor apparatus with decoupling capacitor
US20120104588A1 (en) * 2006-12-27 2012-05-03 Nan-Jang Chen Method for manufacturing leadframe, packaging method for using the leadframe and semiconductor package product
CN202259243U (zh) * 2011-06-13 2012-05-30 西安天胜电子有限公司 一种球焊后框架贴膜封装件
CN203103286U (zh) * 2012-12-28 2013-07-31 华天科技（西安）有限公司 一种基于圆柱形电感可实现smt的单芯片封装件

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100207244A1 (en) * 2001-04-06 2010-08-19 Oki Electric Industry Co., Ltd. Semiconductor apparatus with decoupling capacitor
US20120104588A1 (en) * 2006-12-27 2012-05-03 Nan-Jang Chen Method for manufacturing leadframe, packaging method for using the leadframe and semiconductor package product
CN101383342A (zh) * 2007-09-05 2009-03-11 半导体元件工业有限责任公司 半导体元器件及制造方法
CN202259243U (zh) * 2011-06-13 2012-05-30 西安天胜电子有限公司 一种球焊后框架贴膜封装件
CN203103286U (zh) * 2012-12-28 2013-07-31 华天科技（西安）有限公司 一种基于圆柱形电感可实现smt的单芯片封装件

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103325756A (zh) * 2013-05-16 2013-09-25 华天科技（西安）有限公司 一种基于框架的多器件smt扁平封装件及其制作工艺
CN105609231A (zh) * 2015-12-24 2016-05-25 合肥祖安投资合伙企业(有限合伙) 叠层电感器及其制造方法以及叠层封装组件
CN115841958A (zh) * 2023-02-20 2023-03-24 广州丰江微电子有限公司 提高引线框架与塑封料结合力的方法

Similar Documents

Publication Publication Date Title
CN102237342A (zh) 一种无线通讯模块产品
CN103474406A (zh) 一种aaqfn框架产品无铜扁平封装件及其制作工艺
CN103021995A (zh) 一种基于圆柱形电感可实现smt的单芯片封装件及其制作工艺
CN203103286U (zh) 一种基于圆柱形电感可实现smt的单芯片封装件
CN203367241U (zh) 功率模块pcb板安装结构及功率模块
CN103325756A (zh) 一种基于框架的多器件smt扁平封装件及其制作工艺
CN203589007U (zh) 一种基于框架的多器件smt扁平封装件
CN101593746B (zh) 一种芯片封装结构
CN103021883A (zh) 一种基于腐蚀塑封体的扁平封装件制作工艺
CN203055901U (zh) 一种基于框架可实现smt的单芯片封装件
CN203260570U (zh) 一种基于框架腐蚀凸点的无载体式新型封装件
CN103021882A (zh) 一种基于磨屑塑封体的扁平封装件制作工艺
CN202084540U (zh) 一种表面贴装型功率晶体管模块
CN103065977A (zh) 一种基于框架可实现smt的扁平封装件制作工艺
CN102738009A (zh) 一种基于刷磨的aaqfn框架产品扁平封装件制作工艺
CN103606540A (zh) 一种基于框架的小间距多器件smt封装件及其制作工艺
CN201435390Y (zh) 一种新型芯片封装结构
CN202772130U (zh) 一种基于aaqfn可用于单芯片封装的封装件
CN111885849A (zh) 一种qfp封装芯片焊接方法
CN103400811A (zh) 一种基于框架采用特殊点胶技术的扁平封装件及其制作工艺
CN110600455A (zh) 一种内置电容的ic芯片及封装方法
CN203339152U (zh) 一种基于冲压框架的单芯片扁平封装件
CN203481210U (zh) 一种基于框架采用点胶技术的扁平封装件
CN202772132U (zh) 一种基于冲压框架的多芯片堆叠式扁平封装件
CN202178252U (zh) 多圈排列无载体双ic芯片封装件

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20130403