CN102738009A - 一种基于刷磨的aaqfn框架产品扁平封装件制作工艺 - Google Patents
一种基于刷磨的aaqfn框架产品扁平封装件制作工艺 Download PDFInfo
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- CN102738009A CN102738009A CN2012101926041A CN201210192604A CN102738009A CN 102738009 A CN102738009 A CN 102738009A CN 2012101926041 A CN2012101926041 A CN 2012101926041A CN 201210192604 A CN201210192604 A CN 201210192604A CN 102738009 A CN102738009 A CN 102738009A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Dicing (AREA)
Abstract
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Claims (4)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2012101926041A CN102738009A (zh) | 2012-06-13 | 2012-06-13 | 一种基于刷磨的aaqfn框架产品扁平封装件制作工艺 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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CN2012101926041A CN102738009A (zh) | 2012-06-13 | 2012-06-13 | 一种基于刷磨的aaqfn框架产品扁平封装件制作工艺 |
Publications (1)
Publication Number | Publication Date |
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CN102738009A true CN102738009A (zh) | 2012-10-17 |
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CN2012101926041A Pending CN102738009A (zh) | 2012-06-13 | 2012-06-13 | 一种基于刷磨的aaqfn框架产品扁平封装件制作工艺 |
Country Status (1)
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CN (1) | CN102738009A (zh) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103021884A (zh) * | 2012-12-10 | 2013-04-03 | 华天科技(西安)有限公司 | 一种基于薄型框架的扁平封装件制作工艺 |
CN103050415A (zh) * | 2012-12-10 | 2013-04-17 | 华天科技(西安)有限公司 | 一种基于先棕化后刷绿漆的扁平封装件制作工艺 |
CN105161424A (zh) * | 2015-07-30 | 2015-12-16 | 南通富士通微电子股份有限公司 | 半导体叠层封装方法 |
Citations (8)
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CN101501937A (zh) * | 2006-06-02 | 2009-08-05 | 内奥科尼克斯公司 | 包括弹性触头臂杆(15)的连接器(17) |
CN101694837A (zh) * | 2009-10-17 | 2010-04-14 | 天水华天科技股份有限公司 | 一种双排引脚的四面扁平无引脚封装件及其生产方法 |
CN101694838A (zh) * | 2009-10-17 | 2010-04-14 | 天水华天科技股份有限公司 | 一种双扁平无引脚封装件及其生产方法 |
CN101826501A (zh) * | 2009-03-06 | 2010-09-08 | 李同乐 | 高密度接点的无引脚集成电路元件 |
CN102074541A (zh) * | 2010-11-26 | 2011-05-25 | 天水华天科技股份有限公司 | 一种无载体无引脚栅格阵列ic芯片封装件及其生产方法 |
CN102412140A (zh) * | 2010-09-17 | 2012-04-11 | 台湾积体电路制造股份有限公司 | 半导体平坦化中降低非均匀性 |
CN102446702A (zh) * | 2010-10-15 | 2012-05-09 | 中芯国际集成电路制造(上海)有限公司 | 湿法处理方法及回蚀方法 |
CN102456648A (zh) * | 2010-10-26 | 2012-05-16 | 欣兴电子股份有限公司 | 封装基板及其制法 |
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2012
- 2012-06-13 CN CN2012101926041A patent/CN102738009A/zh active Pending
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101501937A (zh) * | 2006-06-02 | 2009-08-05 | 内奥科尼克斯公司 | 包括弹性触头臂杆(15)的连接器(17) |
CN101826501A (zh) * | 2009-03-06 | 2010-09-08 | 李同乐 | 高密度接点的无引脚集成电路元件 |
CN101694837A (zh) * | 2009-10-17 | 2010-04-14 | 天水华天科技股份有限公司 | 一种双排引脚的四面扁平无引脚封装件及其生产方法 |
CN101694838A (zh) * | 2009-10-17 | 2010-04-14 | 天水华天科技股份有限公司 | 一种双扁平无引脚封装件及其生产方法 |
CN102412140A (zh) * | 2010-09-17 | 2012-04-11 | 台湾积体电路制造股份有限公司 | 半导体平坦化中降低非均匀性 |
CN102446702A (zh) * | 2010-10-15 | 2012-05-09 | 中芯国际集成电路制造(上海)有限公司 | 湿法处理方法及回蚀方法 |
CN102456648A (zh) * | 2010-10-26 | 2012-05-16 | 欣兴电子股份有限公司 | 封装基板及其制法 |
CN102074541A (zh) * | 2010-11-26 | 2011-05-25 | 天水华天科技股份有限公司 | 一种无载体无引脚栅格阵列ic芯片封装件及其生产方法 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103021884A (zh) * | 2012-12-10 | 2013-04-03 | 华天科技(西安)有限公司 | 一种基于薄型框架的扁平封装件制作工艺 |
CN103050415A (zh) * | 2012-12-10 | 2013-04-17 | 华天科技(西安)有限公司 | 一种基于先棕化后刷绿漆的扁平封装件制作工艺 |
CN105161424A (zh) * | 2015-07-30 | 2015-12-16 | 南通富士通微电子股份有限公司 | 半导体叠层封装方法 |
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C53 | Correction of patent of invention or patent application | ||
CB03 | Change of inventor or designer information |
Inventor after: Chen Shiguang Inventor after: Zhu Wenhui Inventor after: Wang Hu Inventor after: Liu Weidong Inventor after: Luo Yuguang Inventor before: Luo Yuguang Inventor before: Guo Xiaowei Inventor before: Cui Meng Inventor before: Chen Shiguang Inventor before: Liu Jianjun |
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COR | Change of bibliographic data |
Free format text: CORRECT: INVENTOR; FROM: LUO YUGUANG GUO XIAOWEI CUI MENG CHEN SHIGUANG LIU JIANJUN TO: CHEN SHIGUANG ZHU WENHUI WANG HU LIU WEIDONG LUO YUGUANG |
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Application publication date: 20121017 |