CN102074541A - 一种无载体无引脚栅格阵列ic芯片封装件及其生产方法 - Google Patents
一种无载体无引脚栅格阵列ic芯片封装件及其生产方法 Download PDFInfo
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Abstract
一种无载体栅格阵列IC芯片封装件及其制备方法,包括内引脚、IC芯片、焊盘、键合线及塑封体,所述内引脚在封装件正面设为多排矩阵式,背面为外露的多排近似正方形的圆形镀金触点;所述内引脚上面为IC芯片,内引脚和IC芯片之间由胶膜片粘接,IC芯片上的焊盘通过键合线与内引脚相连,所述塑封体包围胶膜片、IC芯片、键合线及内引脚边缘,构成电路整体。本发明采用近似正方形的圆球状阵列触点,结构简单灵活,散热效果好。铜引线框架(L/F)成品率高并降低了材料成本。采用引线框架(L/F)代替陶瓷基板、PCB基板或BT基板,省去了复杂的版图设计,设计制造周期较短,加快了试制生产进程,促使产品提早上市,取得市场先机。
Description
技术领域
本发明属于电子信息自动化元器件制造技术领域,涉及一种IC芯片封装件,具体涉及一种无载体无引脚栅格阵列IC芯片封装件,本发明还涉及该封装件的制备方法。
背景技术
LGA(Land Grid Array)封装是栅格阵列封装,以层压基片为基础的精细间距芯片级封装。LGA用金属触点式封装技术取代了过去的PGA(Pin Grid Array,针脚栅格阵列)是一种跨越性技术革命。PGA(针脚栅格阵列)封装技术一般使用陶瓷基板、PCB基板或BT基板(逻辑关系不清楚),并且版图结构设计较为复杂,使用陶瓷基板、PCB基板或BT基板材料成本高,并且基板生产合格率低、制造周期较长,散热效果不好。
发明内容
为了克服上述现有的PGA(针脚栅格阵列)技术中存在的框架版图结构设计较为复杂,合格率低,致使材料成本高的问题,本发明提供一种省去了复杂的版图设计,采用铜引线框架(L/F)良率高,材料成本较低,并且制造周期短的一种扁平无载体无引脚栅格陈列IC芯片封装件,本发明的另一目的是提供一种上述IC芯片封装件的制备方法。
本发明采用的技术方案如下:
一种无载体栅格阵列IC芯片封装件及其制备方法,包括内引脚,内引脚上面为胶膜片,胶膜片上是IC芯片、IC芯片上的焊盘通过键合线与内引脚相连,塑封体包围胶膜片、IC芯片、键合线、内引脚边缘;其特征在于所述的内引脚设为多排矩阵式内引脚及外露的多排近似正方形的圆形镀金触点。
所述多排矩阵式内引脚设为A、B、C三排引脚,其中A排设有3个内引脚,分别为A1、A2、A3,B排左边2个内引脚B1、B2连在一起,右边设1个单独的内引脚B3,C排设有3个单独的内引脚C1、C2、C3。
所述外露的多排近似正方形的圆形镀金触点为所述封装件背面A排引脚上设有3个大小相同近似正方形的圆形独立引脚触点a1、a2、a3;b排也设有3个近似正方形的圆形独立触点b1、b2、b3;其中b2的左上角成0.10×45°斜角,其斜角正对的a排触点为该电路Pin 1脚;C排也设有3个大小相同的近似正方形圆形独立触点c1、c2、c3。
所述封装件有单芯片封装形式;
所述封装件有多芯片封装形式;
所述封装件设有双芯片堆叠封装形式,在原IC芯片上端设有另一IC芯片,IC芯片之间设有胶膜片粘接,原IC芯片上的焊盘通过键合线与内引脚相连,原IC芯片上的另一焊盘再利用另一键合线与其上端的IC芯片相连,构成电路的电流和信号通道,塑封体包围胶膜片、IC芯片、键合线、内引脚边缘,构成电路整体。
所述单芯片封装件的生产方法包括晶圆减薄、划片、上芯、压焊、塑封、后固化、打印、切割分离、检验、包装、入库,其中后固化、打印、包装、入库同普通QFN生产,其余的操作按下述工艺步骤进行:
减薄、划片
先将晶圆减薄到150μm~200μm,清洗干净并烘干后,背面贴上胶膜片,去掉减薄胶膜,然后将贴有胶膜片的晶圆切成单个芯片,只划透胶膜层,不划保护层;
上芯
在胶膜片专用上芯机上,将芯片自动放置到L/F设置位置的正中央,加热后IC芯片粘在B排内引脚和其余几个内引脚边缘,通过烘烤达到牢固性粘贴;
压焊
本封装IC芯片上焊盘距离内引脚焊点较近,采用小折弯焊线;
塑封
塑封采用全自动包封系统:Y-series E60T, CEL9220HF10TS系列环保塑封料。其工艺条件如下:
模温(℃):165~185,合模式压力(Ton):35~55;注塑压力(Ton):
0.75~1.33;注塑时间(s):6~15;固化时间(s):90~120。
后固化采用QFN固化烘箱,150℃,7小时。
切割
采用本产品NLGA1/NLGA2专用切割夹具,按正常QFN切割工艺切割。
所述多芯片封装的减薄、划片,塑封,打印,切割与单芯片封装相同,其它步骤方法如下:
上芯、
在胶膜片专用上芯机上,将芯片自动放置到相应L/F内引脚设置位置上,加热后IC芯片粘在中间排内引脚和其余几个内引脚边缘,通过烘烤达到牢固性粘贴;
压焊
采用小折弯焊线。
所述双芯片堆叠封装的的减薄、划片,打印,切割与单芯片封装相同,其它步骤的生产方法如下:
上芯、
在胶膜片专用上芯机上,将芯片自动放置到相应L/F内引脚设置位置上,加热后IC芯片6粘在中间排内引脚和其余几个内引脚边缘,完成全部第一次上芯后,在IC芯片6上采用同样方法,将带胶膜片的IC芯片9粘在IC芯片6上,通过烘烤达到牢固性粘贴;
压焊
采用小折弯焊线;
塑封
塑封采用全自动包封系统:Y-series E60T, CEL9220HF10TS系列环保塑封料。其工艺条件如下:
模温(℃):165~185,合模式压力(Ton):35~55;注塑压力(Ton):
0.75~1.33;注塑时间(s):6~15;固化时间(s):90~120。
后固化采用QFN固化烘箱, 150℃,7小时。
本发明采用近似正方形的圆球状阵列触点,结构简单灵活,散热效果好。铜引线框架(L/F)成品率高并且材料利用率高,降低了材料成本。采用引线框架(L/F)代替陶瓷基板、PCB基板或BT基板,省去了复杂的版图设计,设计制造周期较短,加快了试制生产进程,促使产品提早上市,取得市场先机。
附图说明
图1为本发明IC芯片封装件的单芯片结构示意图;
图2为图1的俯视图;
图3为图1的仰视图;
图4为本发明IC芯片封装件的堆叠封装的实施例结构示意图;
图5为图4的俯视图;
图6为图4的仰视图;
图7为本发明IC芯片封装件的多芯片封装的实施例结构示意图;
图8为图7的俯视图;
图9为图7的仰视图。
图中,1.第一列引脚(凸点),2. 第二列引脚(凸点),3. 第三列引脚(凸点),4.第四列引脚(凸点);5.胶膜片,6.IC芯片1,7.键合线,8.塑封体,9. IC芯片2,10. 芯片与芯片间键合线,11. 第二胶膜片;A为第一行内引脚,B为第二行内引脚,C为第三行内引脚,D为第四行内引脚;a第一行金凸点,b 为第二行金凸点,c为第三行金凸点,d为第四行金凸点。
具体实施方式
下面结合附图和实施例对本发明进行详细说明。
一种无载体栅格阵列IC芯片封装件,包括内引脚,胶膜片,IC芯片(单、双),多条键合线,塑封体,外露的多排近似正方形的圆形镀金触点。该封装引线框架无载体,在内引脚上面是芯片,内引脚和芯片之间用胶膜片5粘贴,如果是堆叠封装,IC芯片上又是一层胶膜片,胶膜片上是另一IC芯片,原IC芯片上的焊盘通过键合线与内引脚或另一IC芯片相连,构成了电路的电流和信号通道,塑封体包围了胶膜片、IC芯片、键合线、内引脚边缘,构成电路整体。并且,塑封体对多条键合线、IC芯片和近似正方形的圆形镀金触点起到保护和支撑作用。最底层胶膜片上的IC芯片全靠内引脚支撑。该封装件有单芯片封装、多芯片封装、堆叠封装形式。
本发明采用无载体的矩阵式多触点引线框架,是一种无载体的矩阵式多触点框架。
本发明的典型三排圆形镀金触点(NLGA9)封装件的外形尺寸如下:
塑封体长度:1.50±0.05; 塑封体宽度:1.50±0.05
塑封体厚度:0.75±0.05 安装高度:0.02±0.01
引脚宽度:0.25±0.05 引脚厚度:0.20REF
引脚间距:0.50BSC
由于该封装用无载体的引线框架(L/F),后固化、打印、包装同普通QFN生产,其余工序生产方法如下:
A.单芯片封装
1、减薄、划片
先将晶圆减薄到150μm~200μm,清洗干净并烘干后,背面贴上胶膜片,去掉减薄胶膜。然后将贴有胶膜片的晶圆切成单个芯片,只划透胶膜层,不划保护层。
2、上芯
采用NLGA9L专用框架和胶膜片,在专用上芯机上,引线框架自动传送到上芯机轨道,将芯片自动放置到B1、B2内引脚和B3、A1、A2、A3、C1、C2、C3其余几个内引脚边缘。即对典型三排引脚来说,由于NLGA框架无载体,带胶膜片的芯片粘在B排双引脚(如NLGA9L,B1,B2、B3)和其余几个引脚(如NLGA9L,A1、A2、A3、C1、C2、C3)的边缘,通过烘烤达到牢固性粘贴。
3、压焊
由于IC芯片6粘在内引脚上,IC芯片6上焊盘距离内引脚焊点较近,不能按正常QFN键合工艺,只能采用短焊线低弧度键合,其压焊参数如下:
预热温度:130℃,加热温度:150℃。
第一焊点,芯片上的焊盘,焊接时间(ms):3~10;
第一焊点焊接力 ( mN) :100~150(一般QFN压焊120~300);
第一焊点焊接功率(%): 15~28;
第二焊点,内引线脚,焊接时间(ms):4~10;
第二焊点(内引线脚)焊接力(mN):450~800(一般QFN压焊600~1000):
第二焊点,内引线脚,功率(%):110~160;
最小焊线长度(mm):0.5~0.6,一般QFN产品0.6~0.8。
4、塑封
由于键合采用短焊线低弧度键合,且焊线拉得相对较紧,不能按正常QFN塑封工艺塑封,采用CEL9220环保塑封料,经DOE(Design Of Experiment实验设计,简称DOE)试验,最后确定其塑封工艺参数如下;
模具温度(℃):175±10; 合模压力(MPa);40~120.
注塑压强(Ton):0.80~1.80; 注塑时间(sec):10±2;
固化时间(sec):90±30。
后固化:150(℃),7h。
5、打印
按常规QFN激光打印工艺。
6、电镀
引线框架采用镀金触点,不需要电镀。
7、切割
采用本产品NLGA-01(3排引脚)/02(多排引脚)专用切割夹具,按正常QFN切割工艺切割。
B.双芯片堆叠封装
双芯片堆叠封装的减薄、划片,打印,切割与单芯片封装相同,矩阵式镀金触点,不用电镀。
1、减薄、划片
先将晶圆减薄到100μm~150μm,清洗干净并烘干后,背面贴上胶膜片,去掉减薄胶膜。然后将贴有胶膜片的晶圆切成单个芯片,根据减薄后晶圆厚度+胶膜片的胶膜厚度调整划片深度参数,只划透胶膜层,不划保护层。
2、上芯
在胶膜片专用上芯机上,将芯片自动放置到相应L/F内引脚设置位置上,加热后IC芯片6粘在中间排内引脚和其余几个内引脚边缘。对典型四排引脚来说,由于NLGA框架无载体,带胶膜片的芯片粘在B排和C排引脚(如NLGA16L,B2、B3、C2、C3)的边缘。完成全部第一次上芯后,采用同样方法,将IC芯片9粘在B4和C4引脚上,通过烘烤达到牢固性粘贴。
3、压焊
由于IC芯片6粘在内引脚上,焊盘距离内引脚焊点较近,另外,双芯片堆叠封装,IC芯片9粘在IC芯片6上,IC芯片9与IC芯片6之间还要焊线,所以,只能采用短引线低弧度焊线和反向打线。其压焊参数如下:
预热温度:130℃,加热温度:150℃。
第一焊点(芯片上的焊盘)焊接时间(ms):3~10;
第一焊点焊接力 ( mN) :100~150(一般QFN压焊120~300);
第一焊点焊接功率(%): 15~28;
第二焊点(内引线脚)焊接时间(ms):4~10;
第二焊点(内引线脚)焊接力(mN):450~800(一般QFN压焊600~1000):
第二焊点(内引线脚)功率(%):110~160;
最小焊线长度(mm):0.5~0.6,一般QFN产品0.6~0.8。
4、塑封
由于双芯片堆叠封装,IC芯片9与IC芯片6之间还要焊线,塑封的注塑过程,塑封料流动和冲线与单芯片差别较大,要通过工艺试验,不断调整和优化注塑工艺参数才能达到塑封不冲丝、不断线和无离层的最佳结果。
塑封工艺参数如下;
模具温度(℃):175±10; 合模压力(MPa);40~120.
注塑压强(Ton):0.80~1.33; 注塑时间(sec):10±2;
固化时间(sec):90±30。
后固化:150℃,7h。
C.多芯片封装
多芯片封装的减薄、划片,打印,切割与单芯片封装相同,矩阵式引线框架采用镀金触点,不需要电镀。
1、上芯
在胶膜片专用上芯机上,将芯片自动放置到相应L/F内引脚设置位置上,加热后IC芯片6粘在中间排内引脚和其余几个内引脚边缘。对典型四排引脚来说,由于NLGA框架无载体,带胶膜片的IC芯片6粘在B排和C排引脚(如NLGA16L:B2、B3和C2、C3)上,带胶膜片的IC芯片9粘在B4和C4引脚的边缘。
2、压焊
由于IC芯片6粘在内引脚上,IC芯片上焊盘距离内引脚焊点较近,不能按正常QFN键合工艺,只能采用短引线低弧度焊线和反向打线。其压焊参数如下:
预热温度:130℃,加热温度:150℃。
第一焊点(芯片上的焊盘)焊接时间(ms):3~10;
第一焊点焊接力 ( mN) :100~150(一般QFN压焊120~300);
第一焊点焊接功率(%): 15~28;
第二焊点(内引线脚)焊接时间(ms):4~10;
第二焊点(内引线脚)焊接力(mN):450~800(一般QFN压焊600~1000):
第二焊点(内引线脚)功率(%):110~160;
最小焊线长度(mm):0.5~0.6,一般QFN产品0.6~0.8。
3、塑封
由于双芯片堆叠封装,IC芯片9与IC芯片6之间还要焊线,塑封的注塑过程,塑封料流动和冲线与单芯片差别较大,要通过工艺试验,不断调整和优化注塑工艺参数才能达到塑封不冲丝、不断线和无离层的最佳结果。其塑工艺参数如下:
模具温度(℃):175±10; 合模压力(MPa);40~120;
注塑压强(Ton):0.80~1.33; 注塑时间(sec):10±2;
固化时间(sec):90±30。
后固化:150℃,7h。
实施例1
单芯片封装
1、减薄、划片
先将晶圆减薄到150μm,清洗干净并烘干后,背面贴上胶膜片,去掉减薄胶膜。然后将贴有胶膜片的晶圆切成单个芯片,只划透胶膜层,不划保护层。
2、上芯
采用NLGA9L专用框架和胶膜片,在专用上芯机上,引线框架自动传送到上芯机轨道,将芯片自动放置到B1、B2内引脚和B3、A1、A2、A3、C1、C2、C3其余几个内引脚边缘。即对典型三排引脚来说,由于NLGA框架无载体,带胶膜片的芯片粘在B排双引脚(如NLGA9L,B1,B2、B3)和其余几个引脚(如NLGA9L,A1、A2、A3、C1、C2、C3)的边缘,通过烘烤达到牢固性粘贴。
3、压焊
由于IC芯片6粘在内引脚上,IC芯片6上焊盘距离内引脚焊点较近,采用短焊线低弧度键合。其压焊参数如下:
预热温度:130℃,加热温度:150℃。
第一焊点(芯片上的焊盘)焊接时间(ms):9;
第一焊点焊接力 ( mN) :120(一般QFN压焊120~300);
第一焊点焊接功率(%):21;
第二焊点(内引线脚)焊接时间(ms):8;
第二焊点(内引线脚)焊接力(mN):650 (一般QFN压焊600~1000):
第二焊点(内引线脚)功率(%):125。
4、塑封
由于键合采用短焊线低弧度键合,且焊线拉得相对较紧,不能按正常QFN塑封工艺塑封,获得塑封不冲丝、不断线和无离层的预期效果。采用CEL9220环保塑封料,其塑封工艺参数如下;
模具温度(℃):175; 合模压力(MPa):120;
注塑压强(Ton):1.0; 注塑时间(sec):12;
固化时间(sec):90。
后固化:150℃,7h。
5、打印
按正常QFN激光打印工艺。
6、电镀
引线框架采用镀金触点,不需要电镀。
7、切割
采用本产品NLGA-01(3排引脚)/02(多排引脚)专用切割夹具,按正常QFN切割工艺切割。
实施例2
双芯片堆叠封装
多芯片堆叠封装的减薄、划片,打印,切割与单芯片封装相同,矩阵式镀金触点,不用电镀。
1、减薄、划片
先将下层晶圆减薄到200μm,层晶圆减薄到100μm,清洗干净并烘干后,背面贴上胶膜片,去掉减薄胶膜。然后将贴有胶膜片的晶圆切成单个芯片,根据减薄后晶圆厚度+胶膜片的胶膜厚度调整划片深度参数,只划透胶膜层,不划保护层。
2、上芯
在胶膜片专用上芯机上,将芯片自动放置到相应L/F内引脚设置位置上,加热后IC芯片6粘在中间排内引脚和其余几个内引脚边缘。对典型四排引脚来说,由于NLGA框架无载体,带胶膜片的芯片粘在B排和C排引脚(如NLGA16L,B2、B3、C2、C3)的边缘。完成全部第一次上芯后,采用同样方法,将IC芯片9粘在B4和C4引脚上,通过烘烤达到牢固性粘贴。
3、压焊
由于IC芯片6粘在内引脚上,焊盘距离内引脚焊点较近,另外,双芯片堆叠封装,IC芯片9粘在IC芯片6上,IC芯片9与IC芯片6之间还要焊线,所以,只能采用短引线低弧度焊线和反向打线。其压焊参数如下:
预热温度:130℃,加热温度:150℃。
第一焊点(芯片上的焊盘)焊接时间(ms):8;
第一焊点焊接力 ( mN) :110(一般QFN压焊120~300);
第一焊点焊接功率(%): 20;
第二焊点(内引线脚)焊接时间(ms):6;
第二焊点(内引线脚)焊接力(mN):550 (一般QFN压焊600~1000):
第二焊点(内引线脚)功率(%):130;
4、塑封
由于双芯片堆叠封装,IC芯片9与IC芯片6之间还要焊线,塑封的注塑过程。塑封工艺参数如下;
模具温度(℃):175; 合模压力(MPa);45;
注塑压强(Ton):0.90; 注塑时间(sec):9;
固化时间(sec):90。
后固化:150℃,7h。
5、打印
按正常QFN激光打印工艺。
6、电镀
引线框架采用镀金触点,不需要电镀。
7、切割
采用本产品NLGA-01(3排引脚)/02(多排引脚)专用切割夹具,按正常QFN切割工艺切割。
实施例3
多芯片封装
多芯片封装的减薄、划片,打印,切割与单芯片封装相同,矩阵式引线框架采用镀金触点,不需要电镀。
1、减薄、划片
同实施例1
2、上芯
在胶膜片专用上芯机上,将芯片自动放置到相应L/F内引脚设置位置上,加热后IC芯片6粘在中间排内引脚和其余几个内引脚边缘。对典型四排引脚来说,由于NLGA框架无载体,带胶膜片的IC芯片6粘在B排和C排引脚(如NLGA16L:B2、B3和C2、C3)上,带胶膜片的IC芯片9粘在B4和C4引脚的边缘。
3、压焊
由于IC芯片6粘在内引脚上,IC芯片上焊盘距离内引脚焊点较近,不能按正常QFN键合工艺,只能采用短引线低弧度焊线和反向打线。其压焊参数如下:
预热温度:130℃,加热温度:150℃。
第一焊点(芯片上的焊盘)焊接时间(ms):9;
第一焊点焊接力 ( mN) :125(一般QFN压焊120~300);
第一焊点焊接功率(%):23;
第二焊点(内引线脚)焊接时间(ms):8;
第二焊点(内引线脚)焊接力(mN):650 (一般QFN压焊600~1000):
第二焊点(内引线脚)功率(%):140;
4、塑封
由于双芯片堆叠封装,IC芯片9与IC芯片6之间还要焊线,塑封的注塑过程。塑封工艺参数如下:
模具温度(℃):175; 合模压力(MPa);50;
注塑压强(Ton):1.1; 注塑时间(sec):12;
固化时间(sec):90;
后固化:150℃,7h。
5、打印
同实施例1
6、电镀
同实施例1。
7、切割
同实施例1
实施例4
单芯片封装
1、减薄、划片
先将下层芯片晶圆减薄到200μm,清洗干净并烘干后,背面贴上胶膜片,去掉减薄胶膜。然后将贴有胶膜片的晶圆切成单个芯片,只划透胶膜层,不划保护层。
2、上芯
采用NLGA9L专用框架和胶膜片,在专用上芯机上,引线框架自动传送到上芯机轨道,将芯片自动放置到B1、B2内引脚和B3、A1、A2、A3、C1、C2、C3其余几个内引脚边缘。即对典型三排引脚来说,由于NLGA框架无载体,带胶膜片的芯片粘在B排双引脚(如NLGA9L,B1,B2、B3)和其余几个引脚(如NLGA9L,A1、A2、A3、C1、C2、C3)的边缘,通过烘烤达到牢固性粘贴。
3、压焊
由于IC芯片6粘在内引脚上,IC芯片6上焊盘距离内引脚焊点较近,不能按正常QFN键合工艺,只能采用短焊线低弧度键合(是本发明方法采用的特殊焊线,),难度较大,需要攻关,必须与塑封工序合作试验解决。其压焊参数如下:
预热温度:130℃,加热温度:150℃。
第一焊点(芯片上的焊盘)焊接时间(ms):8.5;
第一焊点焊接力 ( mN) :110(一般QFN压焊120~300);
第一焊点焊接功率(%):23;
第二焊点(内引线脚)焊接时间(ms):8;
第二焊点(内引线脚)焊接力(mN):650 (一般QFN压焊600~1000):
第二焊点(内引线脚)功率(%):135;
4、塑封
由于键合采用短焊线低弧度键合,且焊线拉得相对较紧,不能按正常QFN塑封工艺塑封,需要与键合配合,攻关试验调整工艺参数,获得塑封不冲丝、不断线和无离层的预期效果。采用CEL9220环保塑封料,其塑封工艺参数如下;
模具温度(℃):180; 合模压力(MPa); 120.
注塑压强(Ton): 1.20; 注塑时间(sec):10;
固化时间(sec):120;
后固化:150℃,7h。
5、打印
按正常QFN激光打印工艺。
6、电镀
引线框架采用镀金触点,不需要电镀。
7、切割
采用本产品NLGA-01(3排引脚)/02(多排引脚)专用切割夹具(请给出该专用切割夹具的型号),按正常QFN切割工艺切割。
实施例5
双芯片堆叠封装
1、减薄、划片
先将下层晶圆减薄到150μm,层晶圆减薄到100μm,清洗干净并烘干后,背面贴上胶膜片,去掉减薄胶膜。然后将贴有胶膜片的晶圆切成单个芯片,根据减薄后晶圆厚度+胶膜片的胶膜厚度调整划片深度参数,只划透胶膜层,不划保护层。
2、上芯
在胶膜片专用上芯机上,将芯片自动放置到相应L/F内引脚设置位置上,加热后IC芯片6粘在中间排内引脚和其余几个内引脚边缘。对典型四排引脚来说,由于NLGA框架无载体,带胶膜片的芯片粘在B排和C排引脚(如NLGA16L,B2、B3、C2、C3)的边缘。完成全部第一次上芯后,采用同样方法,将IC芯片9粘在B4和C4引脚上,通过烘烤达到牢固性粘贴。
3、压焊
由于IC芯片6粘在内引脚上,焊盘距离内引脚焊点较近,另外,双芯片堆叠封装,IC芯片9粘在IC芯片6上,IC芯片9与IC芯片6之间还要焊线,所以,只能采用短引线低弧度焊线和反向打线。其压焊参数如下:
预热温度:130℃,加热温度:150℃。
第一焊点(芯片上的焊盘)焊接时间(ms):9;
第一焊点焊接力 ( mN) : 135(一般QFN压焊120~300);
第一焊点焊接功率(%):25;
第二焊点(内引线脚)焊接时间(ms):10;
第二焊点(内引线脚)焊接力(mN):700 (一般QFN压焊600~1000):
第二焊点(内引线脚)功率(%):145;
4、塑封
由于双芯片堆叠封装,IC芯片9与IC芯片6之间还要焊线,塑封的注塑过程,塑封料流动和冲线与单芯片差别较大,要通过工艺试验,不断调整和优化注塑工艺参数才能达到塑封不冲丝、不断线和无离层的最佳结果。塑封工艺参数如下;
模具温度(℃):180; 合模压力(MPa);110;
注塑压强(Ton):1.23; 注塑时间(sec):8;
固化时间(sec):11
后固化:150℃,7h。
5、打印
按正常QFN激光打印工艺。
6、电镀
引线框架采用镀金触点,不需要电镀。
7、切割
采用本产品NLGA-01(3排引脚)/02(多排引脚)专用切割夹具(请给出该专用切割夹具的型号),按正常QFN切割工艺切割。
实施例6
多芯片封装
多芯片封装的减薄、划片,打印,切割与单芯片封装相同,矩阵式引线框架采用镀金触点,不需要电镀。
1、减薄、划片
同实施例5
2、上芯
在胶膜片专用上芯机上,将芯片自动放置到相应L/F内引脚设置位置上,加热后IC芯片6粘在中间排内引脚和其余几个内引脚边缘。对典型四排引脚来说,由于NLGA框架无载体,带胶膜片的IC芯片6粘在B排和C排引脚(如NLGA16L:B2、B3和C2、C3)上,带胶膜片的IC芯片9粘在B4和C4引脚的边缘。
3、压焊
由于IC芯片6粘在内引脚上,IC芯片上焊盘距离内引脚焊点较近,不能按正常QFN键合工艺,只能采用短引线低弧度焊线和反向打线。其压焊参数如下:
预热温度:130℃,加热温度:150℃。
第一焊点(芯片上的焊盘)焊接时间(ms):9;
第一焊点焊接力 ( mN) :138(一般QFN压焊120~300);
第一焊点焊接功率(%):25;
第二焊点(内引线脚)焊接时间(ms):9;
第二焊点(内引线脚)焊接力(mN):450~800(一般QFN压焊600~1000):
第二焊点(内引线脚)功率(%):150;
4、塑封
由于双芯片堆叠封装,IC芯片9与IC芯片6之间还要焊线,塑封的注塑过程,塑封料流动和冲线与单芯片差别较大,要通过工艺试验,不断调整和优化注塑工艺参数才能达到塑封不冲丝、不断线和无离层的最佳结果。其塑工艺参数如下:
模具温度(℃): 165; 合模压力(MPa);100;
注塑压强(Ton):1.20; 注塑时间(sec):9;
固化时间(sec):100;
后固化:150℃,7h 。
5、打印
同实施例5。
6、电镀
同实施例5。
7、切割
同实施例5
Claims (9)
1.一种无载体栅格阵列IC芯片封装件,包括内引脚、IC芯片、焊盘、键合线及塑封体,其特征在于所述内引脚在封装件正面设为多排矩阵式,背面为外露的多排近似正方形的圆形镀金触点;所述内引脚上面为IC芯片(6),内引脚和IC芯片(6)之间由胶膜片(5)粘接, IC芯片(6)上的焊盘通过键合线(7)与内引脚相连,所述塑封体(8)包围胶膜片(5)、IC芯片(6)、键合线(7)及内引脚边缘,构成电路整体。
2.根据权利要求1所述的一种无载体栅格阵列IC芯片封装件,其特征在于所述多排矩阵式内引脚设为A、B、C三排引脚,其中A排设有3个内引脚,分别为A1、A2、A3,B排左边2个内引脚B1、B2连在一起,右边设1个单独的内引脚B3,C排设有3个单独的内引脚C1、C2、C3。
3.根据权利要求1所述的一种一种无载体栅格阵列IC芯片封装件,其特征在于所述外露的多排近似正方形的圆形镀金触点为所述封装件背面A排引脚上设有3个大小相同近似正方形的圆形独立引脚触点a1、a2、a3;b排也设有3个近似正方形的圆形独立触点b1、b2、b3,其中b2的左上角成0.10×45°斜角,其斜角正对的a排触点为该电路Pin 1脚;C排也设有3个大小相同的近似正方形圆形独立触点c1、c2、c3。
4.根据权利要求1所述的一种无载体栅格阵列IC芯片封装件,其特征在于所述封装件设有单芯片封装形式。
5.根据权利要求1所述的一种无载体栅格阵列IC芯片封装件,其特征在于所述封装件设有多芯片封装形式。
6.根据权利要求1所述的一种无载体栅格阵列IC芯片封装件,其特征在于所述封装件设有双芯片堆叠封装形式,在原IC芯片(6)上端设有另一IC芯片(9),IC芯片(6)和IC芯片(9)之间设有胶膜片(5)粘接, IC芯片(6)上的焊盘通过键合线(7)与内引脚或IC芯片(9)相连,构成电路的电流和信号通道,塑封体包围胶膜片、IC芯片、键合线、内引脚边缘,构成电路整体。
7.根据权利要求1、2、3或4所述的一种无载体栅格阵列IC芯片封装件的生产方法,其特征在于所述单芯片封装件的生产方法包括:晶圆减薄、划片、上芯、压焊、塑封、后固化、打印、切割分离、检验、包装、入库,其中后固化、打印、包装、入库同普通QFN生产,其余的操作按下述工艺步骤进行:
减薄、划片
先将晶圆减薄到150μm~-200μm,清洗干净并烘干后,背面贴上胶膜片,去掉减薄胶膜,然后将贴有胶膜片的晶圆切成单个芯片,只划透胶膜层,不划保护层;
上芯
在胶膜片专用上芯机上,将芯片自动放置到L/F设置位置的正中央,加热后IC芯片粘在B排内引脚和其余几个内引脚边缘,通过烘烤达到牢固性粘贴;
压焊
本封装IC芯片上焊盘距离内引脚焊点较近,采用小折弯焊线;
塑封
由于键合采用小折弯焊线,且焊线拉得较紧,塑封时要调整工艺参数,防止脱球;其塑封工艺参数如下:
模具温度(℃):175±10; 合模压力(MPa);40~120;
注塑压强(Ton):0.80~1.33; 注塑时间(sec):10±2;
固化时间(sec):90±30;
后固化:150℃,7h;
切割
采用本产品NLGA1/NLGA2专用切割夹具,按正常QFN切割工艺切割。
8.根据权利要求1、2、3或5所述一种无载体栅格阵列IC芯片封装件的生产方法,包括晶圆减薄、划片、上芯、压焊、塑封、后固化、打印、切割分离、检验、包装、入库,其特征在于多芯片封装的减薄、划片,塑封,打印,切割与单芯片封装相同,其它步骤方法如下:
上芯、
在胶膜片专用上芯机上,将芯片自动放置到相应L/F内引脚设置位置上,加热后IC芯片粘在中间排内引脚和其余几个内引脚边缘,通过烘烤达到牢固性粘贴;
压焊
采用小折弯焊线,其工艺参数如下:
预热温度:130℃,加热温度:150℃;
第一焊点为芯片上的焊盘,焊接时间(ms):3~10;
第一焊点焊接力 ( mN) :100~150;
第一焊点焊接功率(%): 15~28;
第二焊点内引线脚,焊接时间(ms):4~10;
第二焊点内引线脚焊接力(mN):450~800:
第二焊点焊接功率(%):110~160。
9.根据权利要求1、2、3或6所述装,包括晶圆减薄、划片、上芯、压焊、塑封、后固化、打印、切割分离、检验、包装、入库,其特征在于所述双芯片堆叠封装的减薄、划片,打印,切割与单芯片封装相同,其它步骤的生产方法如下:
上芯、
在胶膜片专用上芯机上,将芯片自动放置到相应L/F内引脚设置位置上,加热后IC芯片6粘在中间排内引脚和其余几个内引脚边缘,完成全部第一次上芯后,在IC芯片6上采用同样方法,将带胶膜片的IC芯片9粘在IC芯片6上,通过烘烤达到牢固性粘贴;
压焊
采用小折弯焊线;
塑封
塑封的注塑过程中,其塑封工艺参数如下:
模具温度(℃):175±10; 合模压力(MPa);40~120;
注塑压强(Ton):0.80~1.33; 注塑时间(sec):10±2;
固化时间(sec):90±30;
后固化:150℃,7h。
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