CN108321151A - 芯片封装组件及其制造方法 - Google Patents

芯片封装组件及其制造方法 Download PDF

Info

Publication number
CN108321151A
CN108321151A CN201810069713.1A CN201810069713A CN108321151A CN 108321151 A CN108321151 A CN 108321151A CN 201810069713 A CN201810069713 A CN 201810069713A CN 108321151 A CN108321151 A CN 108321151A
Authority
CN
China
Prior art keywords
chip
pin
electrode
encapsulation assembly
carrier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201810069713.1A
Other languages
English (en)
Inventor
陈世杰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hangzhou Silergy Semiconductor Technology Ltd
Original Assignee
Hangzhou Silergy Semiconductor Technology Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hangzhou Silergy Semiconductor Technology Ltd filed Critical Hangzhou Silergy Semiconductor Technology Ltd
Priority to CN201810069713.1A priority Critical patent/CN108321151A/zh
Publication of CN108321151A publication Critical patent/CN108321151A/zh
Priority to TW107137518A priority patent/TWI744562B/zh
Priority to US16/248,069 priority patent/US10950528B2/en
Priority to US17/175,018 priority patent/US11605578B2/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/165—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

本发明提供了一种芯片封装组件及其制造方法，通过在位于芯片承载盘周围的引脚上安装芯片，以使诸如二极管这样的器件在封装组件的内部与其它芯片电连接，提高的芯片的集成度，减小了外围电路的体积。

Description

芯片封装组件及其制造方法
技术领域
本发明涉及半导体技术领域，尤其涉及一种芯片封装组件及其制造方法。
背景技术
目前的QFN封装中所采用的引线框架如图1所示，其包括位于中间的承载盘11和位于承载盘11周围的引脚12。为了提高封装组件的集成度，在QFN封装中，通常会封装装多块芯片(裸芯片)，但所封装的芯片只叠层或平铺在引线框架中间的承载盘上，如图2所示，芯片21与芯片22叠层安装在承载盘11上，芯片22上电极通过导线221电连接到芯片21上，芯片21上的电极在通过导线211电连接到引脚12上，或者如图3所示，芯片21与芯片22平铺在承载盘11上，芯片21与芯片22上的电极分别通过导线211与221电连接到引脚12上。
然而，在某些应用上，希望芯片上的I/O能串联二极管等芯片，以用于给外围电路做驱动或保护IC的端口，这时，如图2与图3所述QFN无法将控制芯片或MOS管芯片与二极管芯片集成在同一封装体内，而是只能在封装好的芯片外围电路和独立的二极管器件串联。
发明内容
有鉴于此，本发明提供了一种芯片封装组件及其制造方法，以实现将二极管与其它芯片一起集成在封装体的内部，以实现二极管与其它芯片在封装体内部的串联连接。
一种芯片封装组件，其特在于，包括：
引线框架，具有承载盘和位于所述承载盘周围的多个引脚，
第一芯片，所述第一芯片位于所述承载盘之上，
至少一个第二芯片，所述第二芯片位于所述引脚之上。
优选地，每一个所述第二芯片位于一个所述引脚上。
优选地，所述第二芯片的第一表面上具有第一电极，所述第二芯片的第二表面上具有第二电极，
所述第二芯片第二表面朝向所述引脚的第一表面，所述第二电极与所述引脚的第一表面电连接，
所述第一电极通过第一导线与所述第一芯片电连接，以将所述第二芯片与第一芯片串联连接。
优选地，所述第一芯片的第一表面为有源面，所述第一芯片的第二表面贴在所述承载盘的第一表面上，
所述第一电极通过第一导线与所述有源面上的一个电极电连接，所述有源面上的剩余电极通过第二导线与除用于承载所述第二芯片外的所述引脚的第一表面电连接。
优选地，所述第二芯片为二极管，
所述第一电极为二极管的阳极和阴极中的一个，所述第二电极为二极管的阳极和阴极中的另一个。
优选地，所述二极管为瞬态抑制二极管或肖特基二极管。
优选地，所述的芯片封装组件还包括用于包封所述第一芯片与第二芯片的塑封体，
所述引脚的第二表面和所述承载盘的第二表面裸露在所述塑封体的表面。
优选地，所述芯片封装组件为DFN或QFN封装。
一种芯片封装组件的制造方法，其特在于，包括：
在引线框架的承载盘上安装第一芯片，
在引线框架的引脚上安装第二芯片，所述引脚位于所述承载盘的周围。
优选地，所述的制造方法还包括在安装所述第一芯片与第二芯片之前，根据所述第二芯片的尺寸设计所述引脚的结构与尺寸。
优选地，将所述第二芯片采用导电层贴装在一个所述引脚上。
优选地，对所述第一芯片和第二芯片进行DFN或QFN封装。
由上可见，在本发明提供的芯片封装组件及其制造方法中，利用在位于芯片承载盘周围的引脚上安装芯片，从而可以使诸如二极管这样的器件在封装组件的内部与其它芯片电连接，提高的芯片的集成度，减小了外围电路的体积。
附图说明
通过以下参照附图对本发明实施例的描述，本发明的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1为QFN封装组件中的引线框架的结构示意图；
图2为现有技术实现的一种多芯片集成的QFN封装组件结构示意图；
图3为现有技术实现的另一种多芯片集成的QFN封装组件结构示意图；
图4为依据本发明实施例提供的芯片封装组件的剖面结构示意图；
图5为依据本发明实施例提供的芯片封装组件的俯视图。
具体实施方式
以下将参照附图更详细地描述本发明。在各个附图中，相同的组成部分采用类似的附图标记来表示。为了清楚起见，附图中的各个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本发明的许多特定的细节，例如每个组成部分的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本发明。但正如本领域的技术人员能够理解的那样，可以不按照这些特定的细节来实现本发明。此外，在本申请中，芯片是指半导体裸芯片。
图4为依据本发明实施例提供的芯片封装组件的剖面结构示意图，图5为依据本发明实施例提供的芯片封装组件的俯视图，下面将结合图4与图5来具体阐述本发明。
本发明提供的芯片封装组件主要包括引线框架、至少一个第一芯片、至少一个第二芯片。其中，所述的引线框架由承载盘11和位于承载盘12周围的多个引脚12构成，多个引脚12可以对称的排列在承载盘11的四边的，也可以仅对称的排列早承载盘11相对的两边。
第一芯片21位于第一承载盘的之上，其包括相对的第一表面与第二表面，第一芯片21的第一表面为有源面，第二表面粘贴在承载盘11上。第二芯片31位于引脚12之上，具体的，每一个第一芯片31均位于一个引脚12上，引脚12用于引出第二芯片31的一个电极，以使该电极与外部其它器件或电路电连接，引脚12还用于承载第二芯片31，即引脚12为第二芯片31提供机械支撑。
第二芯片31具有相对的第一表面与第二表面，其第一表面上具有第一电极，第二表面上具有第二电极，第二芯片31以第二表面朝向引脚12的第一表面的方式贴装在引脚12上，使得第二电极与引脚12的第一表面电连接，而第二芯片21的第一电极则通过导线311与第一芯片21的有源面上的电极电连接，第一芯片的有源面上的剩余电极通过导线211与除用于承载第二芯片21外的引脚12的第一表面电连接。在芯片封装结构中，第二芯片31与第二芯片21串联连接。
在本发明实施例提供的芯片封装组件中，第二芯片31为二极管，则所述的第一电极为二极管的阳极和阴极中的一个，所述第二电极为二极管的阳极和阴极中的另一个。第二芯片31可以具体为瞬态抑制二极管或肖特基二极管。第一芯片21可以为MOS管，如功率MOS管，也可以为控制芯片。
此外，所述的芯片封装组件还进一步包括塑封体41，塑封体41用于包封第一芯片21和第二芯片31，且引脚12第二表面和承载盘的第二表面均裸露在塑封体41的表面，以作为所述芯片封装组件与外部电连接的外引脚。
根据引脚12在承载盘11周围的排列情况，所述芯片封装组件可以为DFN或QFN封装。且在所述芯片封装组件中，还可以包括第三芯片(图4和图5中未画出)，所述第三芯片堆叠在第一芯片21之上或者与第一芯片21一起平铺在承载盘11上。若第三芯片堆叠在第一芯片21之上，则所述第三芯片上的电极通过导线先电连接到第一芯片21的第一表面上，然后再通过导线由第一表面引出到引脚12上，若第三芯片平铺在承载盘11上，则第三芯片上的电极直接通过导线与引脚12电连接。在所述芯片封装组件中，还可包括多个第二芯片，每一个第二芯片安装在一个引脚上。
此外，本发明还提供了一种芯片封装组件的制造方法，该方法主要包括在引线框架的承载盘上安装第一芯片，而在引线框架的引脚上安装第二芯片，所述引脚位于承载盘的周围。所述制造方法还进一步包括形成所述引线框架，在形成所述引线框架时，根据所述第二芯片的尺寸设计所述引脚的结构与尺寸，以使得所述引脚与所述第二芯片相匹配。可以采用DFN或QFN封装来对第一芯片和第二芯片进行封装。具体的，在安装第二芯片的过程中，可以使第二芯片通过导电层贴装在所述引脚上，使得所述引脚既用作所述第二芯片与外部电路或器件电连接的触点，又作为所述第二芯片的机械支撑体，以承载所述第二芯片。
由上可见，在本发明提供的芯片封装组件及其制造方法中，利用在位于芯片承载盘周围的引脚上安装芯片，从而可以使诸如二极管这样的器件在封装组件的内部与其它芯片电连接，提高的芯片的集成度，减小了外围电路的体积。
依照本发明的实施例如上文所述，这些实施例并没有详尽叙述所有的细节，也不限制该发明仅为所述的具体实施例。显然，根据以上描述，可作很多的修改和变化。本说明书选取并具体描述这些实施例，是为了更好地解释本发明的原理和实际应用，从而使所属技术领域技术人员能很好地利用本发明以及在本发明基础上的修改使用。本发明仅受权利要求书及其全部范围和等效物的限制。

Claims (12)

1.一种芯片封装组件，其特在于，包括：
引线框架，具有承载盘和位于所述承载盘周围的多个引脚，
第一芯片，所述第一芯片位于所述承载盘之上，
至少一个第二芯片，所述第二芯片位于所述引脚之上。
2.根据权利要求1所述的芯片封装组件，其特征在于，每一个所述第二芯片位于一个所述引脚上。
3.根据权利要求2所述的芯片封装组件，其特征在于，所述第二芯片的第一表面上具有第一电极，所述第二芯片的第二表面上具有第二电极，
所述第二芯片第二表面朝向所述引脚的第一表面，所述第二电极与所述引脚的第一表面电连接，
所述第一电极通过第一导线与所述第一芯片电连接，以将所述第二芯片与第一芯片串联连接。
4.根据权利要求3所述的芯片封装组件，其特征在于，所述第一芯片的第一表面为有源面，所述第一芯片的第二表面贴在所述承载盘的第一表面上，
所述第一电极通过第一导线与所述有源面上的一个电极电连接，所述有源面上的剩余电极通过第二导线与除用于承载所述第二芯片外的所述引脚的第一表面电连接。
5.根据权利要求3所述的芯片封装组件，其特征在于，所述第二芯片为二极管，
所述第一电极为二极管的阳极和阴极中的一个，所述第二电极为二极管的阳极和阴极中的另一个。
6.根据权利要求5所述的芯片封装组件，其特征在于，所述二极管为瞬态抑制二极管或肖特基二极管。
7.根据权利要求4所述的芯片封装组件，其特征在于，还包括用于包封所述第一芯片与第二芯片的塑封体，
所述引脚的第二表面和所述承载盘的第二表面裸露在所述塑封体的表面。
8.根据权利要求1所述的芯片封装组件，其特征在于，所述芯片封装组件为DFN或QFN封装。
9.一种芯片封装组件的制造方法，其特在于，包括：
在引线框架的承载盘上安装第一芯片，
在引线框架的引脚上安装第二芯片，所述引脚位于所述承载盘的周围。
10.根据权利要求9所述的制造方法，其特征在于，还包括在安装所述第一芯片与第二芯片之前，根据所述第二芯片的尺寸设计所述引脚的结构与尺寸。
11.根据权利要求9所述的制造方法，其特征在于，将所述第二芯片采用导电层贴装在一个所述引脚上。
12.根据权利要求9所述的制造方法，其特征在于，对所述第一芯片和第二芯片进行DFN或QFN封装。
CN201810069713.1A 2018-01-24 2018-01-24 芯片封装组件及其制造方法 Pending CN108321151A (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN201810069713.1A CN108321151A (zh) 2018-01-24 2018-01-24 芯片封装组件及其制造方法
TW107137518A TWI744562B (zh) 2018-01-24 2018-10-24 晶片封裝組件及其製造方法
US16/248,069 US10950528B2 (en) 2018-01-24 2019-01-15 Chip package assembly and method for manufacturing the same
US17/175,018 US11605578B2 (en) 2018-01-24 2021-02-12 Chip package assembly and method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201810069713.1A CN108321151A (zh) 2018-01-24 2018-01-24 芯片封装组件及其制造方法

Publications (1)

Publication Number Publication Date
CN108321151A true CN108321151A (zh) 2018-07-24

Family

ID=62887690

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810069713.1A Pending CN108321151A (zh) 2018-01-24 2018-01-24 芯片封装组件及其制造方法

Country Status (3)

Country Link
US (2) US10950528B2 (zh)
CN (1) CN108321151A (zh)
TW (1) TWI744562B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023019518A1 (zh) * 2021-08-19 2023-02-23 华为技术有限公司 多芯片系统及其制备方法、光接收机和终端

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11380631B2 (en) * 2019-11-27 2022-07-05 Texas Instruments Incorporated Lead frame for multi-chip modules with integrated surge protection

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1461051A (zh) * 2002-05-22 2003-12-10 松下电器产业株式会社 半导体装置
CN201681864U (zh) * 2010-04-26 2010-12-22 江苏长电科技股份有限公司 埋入型单基岛多圈引脚无源器件封装结构
CN102074541A (zh) * 2010-11-26 2011-05-25 天水华天科技股份有限公司 一种无载体无引脚栅格阵列ic芯片封装件及其生产方法
US20110221059A1 (en) * 2010-03-12 2011-09-15 Siliconware Precision Industries Co., Ltd. Quad flat non-leaded semiconductor package and method of fabricating the same
CN204289446U (zh) * 2014-12-17 2015-04-22 东莞市欧思科光电科技有限公司 具有发光功能的led驱动ic封装结构

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4614586B2 (ja) * 2001-06-28 2011-01-19 三洋電機株式会社 混成集積回路装置の製造方法
JP4007798B2 (ja) * 2001-11-15 2007-11-14 三洋電機株式会社 板状体の製造方法およびそれを用いた回路装置の製造方法
JP4413054B2 (ja) * 2004-03-29 2010-02-10 三洋電機株式会社 混成集積回路装置の製造方法
DE102006012781B4 (de) * 2006-03-17 2016-06-16 Infineon Technologies Ag Multichip-Modul mit verbessertem Systemträger und Verfahren zu seiner Herstellung
JP5390064B2 (ja) * 2006-08-30 2014-01-15 ルネサスエレクトロニクス株式会社 半導体装置
US9397017B2 (en) * 2014-11-06 2016-07-19 Semiconductor Components Industries, Llc Substrate structures and methods of manufacture
US20190214332A1 (en) * 2018-01-10 2019-07-11 Sirectifier Electronic Co., Ltd. Serially-connected transistor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1461051A (zh) * 2002-05-22 2003-12-10 松下电器产业株式会社 半导体装置
US20110221059A1 (en) * 2010-03-12 2011-09-15 Siliconware Precision Industries Co., Ltd. Quad flat non-leaded semiconductor package and method of fabricating the same
CN201681864U (zh) * 2010-04-26 2010-12-22 江苏长电科技股份有限公司 埋入型单基岛多圈引脚无源器件封装结构
CN102074541A (zh) * 2010-11-26 2011-05-25 天水华天科技股份有限公司 一种无载体无引脚栅格阵列ic芯片封装件及其生产方法
CN204289446U (zh) * 2014-12-17 2015-04-22 东莞市欧思科光电科技有限公司 具有发光功能的led驱动ic封装结构

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023019518A1 (zh) * 2021-08-19 2023-02-23 华为技术有限公司 多芯片系统及其制备方法、光接收机和终端

Also Published As

Publication number Publication date
US10950528B2 (en) 2021-03-16
US11605578B2 (en) 2023-03-14
US20210166999A1 (en) 2021-06-03
TWI744562B (zh) 2021-11-01
US20190229043A1 (en) 2019-07-25
TW201939712A (zh) 2019-10-01

Similar Documents

Publication Publication Date Title
TWI697086B (zh) 晶片封裝結構及其製造方法
US9129947B2 (en) Multi-chip packaging structure and method
JP5522561B2 (ja) マイクロ電子デバイスパッケージ、積重ね型マイクロ電子デバイスパッケージ、およびマイクロ電子デバイスを製造する方法
EP2033220A2 (en) Stack die packages
CN105118818B (zh) 一种方形扁平无引脚封装结构的功率模块
CN108321151A (zh) 芯片封装组件及其制造方法
CN110323199A (zh) 一种多基岛引线框架及电源转换模块的qfn封装结构
KR20050074145A (ko) 멀티칩 패키지
CN105489578B (zh) 叠层芯片封装结构
CN104064612B (zh) 太阳能供电的ic芯片
CN104916599A (zh) 芯片封装方法和芯片封装结构
CN115832147A (zh) 一种堆叠类封装体结构、工艺及发光芯片器件
KR101219086B1 (ko) 패키지 모듈
CN213150769U (zh) 大功率集成电路芯片封装装置
CN212113705U (zh) 一种功率半导体模块
US8778704B1 (en) Solar powered IC chip
CN107482108A (zh) 一种新型smd灯珠
CN209896055U (zh) 一种多基岛引线框架及电源转换模块的qfn封装结构
CN218299797U (zh) 一种多芯片合封的半导体封装结构
CN202796920U (zh) 多芯片qfn封装结构
CN209544350U (zh) 高可靠性传感器芯片和调理电路芯片一体化封装
CN108231721A (zh) 多基岛引线框架、引线框架阵列及封装体
TWI469326B (zh) 無基板之快閃記憶卡及其製造方法
CN102820278B (zh) 多芯片qfn封装结构
CN206250175U (zh) 一种双向esd防护二极管的dfn封装结构

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
CB02 Change of applicant information
CB02 Change of applicant information

Address after: 310051 No. 6 Lianhui Street, Xixing Street, Binjiang District, Hangzhou City, Zhejiang Province

Applicant after: Silergy Semiconductor Technology (Hangzhou ) Co., Ltd.

Address before: Room A1501, Science and Technology Building, East Software Park, No. 90 Wensan Road, Hangzhou City, Zhejiang Province

Applicant before: Silergy Semiconductor Technology (Hangzhou ) Co., Ltd.