TWI697086B - 晶片封裝結構及其製造方法 - Google Patents

晶片封裝結構及其製造方法 Download PDF

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TWI697086B
TWI697086B TW105101561A TW105101561A TWI697086B TW I697086 B TWI697086 B TW I697086B TW 105101561 A TW105101561 A TW 105101561A TW 105101561 A TW105101561 A TW 105101561A TW I697086 B TWI697086 B TW I697086B
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Taiwan
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pin
chip
conductive
carrier plate
electrical connector
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TW105101561A
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TW201644024A (zh
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譚小春
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大陸商矽力杰半導體技術（杭州）有限公司
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Abstract

本發明提供一種晶片封裝結構及其製造方法，在所述晶片封裝結構包括第一引腳、位於第一引腳之上的第一導電柱，位於第二導電柱之上且與所述第二導電柱以及晶片有源面上的第一電連接體均電連接的第二引腳，所述晶片有源面上的電極焊盤透過由第一電連接體、第二引腳、第一導電柱以及第一引腳構成導電路徑引出，最終由第一引腳實現晶片與外部電路之間的電連接。這種引出電極的方式，可有效的降低封裝電阻，且無需採用焊料焊接，可避免虛焊現象，提高晶片封裝的可靠性以及有效的降低了晶片的封裝厚度。

Description

晶片封裝結構及其製造方法
本發明涉及晶片封裝技術領域，尤其涉及一種晶片的封裝結構及其製造方法。
在傳統的晶片正裝封裝結構中，晶片的非有源面黏附於引線框架的晶片承載盤上，晶片的有源面上的電極透過金屬引線電連接到承載盤周圍的引腳上，從而將晶片有源面上的電極引出與外部電路連接。
這種傳統的引線鍵合的封裝方式，雖然製程技術較成熟，產量大，但是由於其需要用細長的金屬引線來引出晶片表面上的電極，必然會導致較大封裝電阻，此外，金屬引線與晶片的焊盤之間容易出現虛焊的現象，不利於保障晶片封裝的可靠性。近年來，隨著電子裝置朝著薄型化的趨勢發展，傳統的引線鍵合封裝方式，由於封裝厚度較厚，已經越來越不能滿足人們的要求。
有鑑於此，本發明的目的是提供了一種晶片封裝結構 及其製造方法，以提高封裝可靠性、降低封裝電阻以及減小封裝厚度。
一種晶片封裝結構，包括：引線框架，具有承載盤和位於所述承載盤周圍的第一引腳；位於所述第一引腳上且與所述第一引腳電連接的第一導電柱；第一晶片，具有有源面和與所述有源面相對的背表面，所述背表面貼裝於所述承載盤上，所述有源面的電極焊盤上設置有第一電連接體；第一塑封體，用於包封所述第一晶片和囊封所述引線框架，且具有第一表面和與所述第一表面相對的第二表面，其中，所述第一表面裸露出所述第一導電柱和所述第一電連接體，所述第二表面裸露出所述第一引腳，位於所述第一表面上的第二引腳，用於將所述第一電連接體和所述第一導電柱電連接。
較佳的，所述晶片封裝結構，還包括用於包封所述第二引腳的第二塑封體。
較佳的，所述第二表面上還裸露出所述承載盤。
較佳的，所述背表面具有背面電極焊盤，所述背面電極焊盤透過焊料或導電膠貼裝於所述承載盤上。
較佳的，所述承載盤與一個所述第一引腳電連接。
較佳的，所述第一引腳、第一導電柱、第一電連接體、第二引腳的形成材料相同。
較佳的，所述引線框架還具有位於所述承載盤周圍的第三引腳，所述晶片封裝結構還包括：位於所述第三引腳上且與所述第三引腳電連接的第二導電柱，所述第一表面還裸露出所述第二導電柱；位於所述第一表面上且與所述第二導電柱電連接的第四引腳；位於所述第一表面上方，且有源面上的電極焊盤透過第二電連接體電連接到所述第四引腳上的第二晶片；所述第二塑封體還用於包括所述第四引腳、第二晶片；所述第二表面上還裸露出所述第三引腳。
較佳的，所述第二晶片的有源面上的電極焊盤透過第二電連接體與所述第二引腳電連接。
較佳的，所述第二電連接體為導電凸塊、焊料、金屬引線中的一種。
一種晶片封裝結構的製造方法，包括：提供具有承載盤和第一引腳的引線框架，所述第一引腳位於所述承載盤周圍，在所述第一引腳上形成與所述第一引腳電連接的第一導電柱；將第一晶片的背表面貼裝於所述承載盤上，所述背表面為與所述第一晶片的有源面相對的一面，所述有源面的電極焊盤上設置有第一電連接體；進行第一次塑封製程，以形成包封第一晶片和囊封所述引線框架的第一塑封體，且使所述第一塑封體的第一表 面裸露出所述第一導電柱和第一電連接體，第二表面裸露出所述第一引腳，所述第二表面為與所述第一表面相對的一面；在所述第一表面上形成將所述第一導電柱和第一電連接體電連接的第二引腳。
較佳的，所述製造方法還包括進行第二次塑封製程，以形成包封所述第二引腳的第二塑封體。
較佳的，在所述第一引腳上形成與所述第一引腳電連接的第一導電柱之前，還包括在封裝基板上形成所述引線框架。
較佳的，在封裝基板上形成所述引線框架的步驟包括：在所述封裝基板上形成第一導電層；圖案化所述第一導電層，以形成所述引線框架。
較佳的，形成所述引線框架時，使所述承載盤與一個所述第一引腳一體成型，以實現所述承載盤和第一引腳直接的電連接。
較佳的，進行第二次塑封製程之後還包括去除所述封裝基板的步驟，以使所述第二表面裸露出所述第一引腳和所述承載盤。
較佳的，採用電鍍製程，在所述第一引腳上形成所述第一導電柱。
較佳的，形成所述第二引腳的步驟包括：在所述第一表面上形成第二導電層； 圖案化所述第二導電層，以形成所述第二引腳。
較佳的，所述製造方法還包括在所述第一晶片的有源面的電極焊盤上形成金屬層或導電凸塊作為所述第一電連體。
較佳的，所述背表面上具有背面電極焊盤，所述背面電極焊盤透過焊料或導電膠貼裝於所述承載盤上。
較佳的，在所述封裝基板上形成的所述引線框架還包括位於所述承載盤周圍的第三引腳，所述製造方法還包括：在將第一晶片的背表面貼裝於所述承載盤上之前，在所述第三引腳上形成第二導電柱，在形成所述第一塑封體時，使所述第一表面裸露出所述第二導電柱；在形成所述第一塑封體之後，在所述第一表面上形成與所述第二導電柱電連接的第四引腳；將第二晶片的有源面上的電極焊盤透過第二電連接體電連接到所述第四引腳上；在形成所述第二塑封體時，使所述第二塑封體還包封所述第四引腳、第二晶片；在形成所述第一塑封體時，使所述第二表面還裸露出所述第三引腳。
較佳的，在將所述第二晶片的有源面上的電極焊盤透過所述第二電連接體電連接到所述第四引腳上時，還使所述第二晶片上的有源面上的電極焊盤透過第二電連接體與所述第二引腳電連接。
由上可見，在本發明提供的晶片封裝結構中，晶片有源面上的電極焊盤透過由第一電連接體、第二引腳、第一導電柱以及第一引腳構成導電路徑引出，最終由第一引腳實現晶片與外部電路之間的電連接。這種引出電極的方式，由於第二引腳和第一導電柱的截面(與電流流向垂直方向的截面)面積與導電路徑的長度之比遠大於引線鍵合的截面與導電路徑的長度之比。因此，本發明的這種引出電極的方式，相比引線鍵合的方式，可有效的降低封裝電阻，且由於本發明的這種方式無需採用焊料焊接，可避免虛焊現象，可提高晶片封裝的可靠性。此外，由於第二引腳的厚度可以做得比較薄，使得晶片的封裝厚度更加接近裸晶片的厚度，可更好的迎合人們對裝置薄型化的需求。
00‧‧‧封裝基板
01‧‧‧引線框架
011‧‧‧承載盤
012‧‧‧第一引腳
013‧‧‧第三引腳
02‧‧‧第一導電柱
03‧‧‧第一晶片
04‧‧‧第一電連接體
05‧‧‧第一塑封體
06‧‧‧第二引腳
07‧‧‧第二塑封體
08‧‧‧第二導電柱
09‧‧‧第四引腳
10‧‧‧第二晶片
11‧‧‧第二電連接體
透過以下參照圖式對本發明實施例的描述，本發明的上述以及其他目的、特徵和優點將更為清楚，在圖式中：圖1為根據本發明實施例提供的一種晶片封裝結構的剖面結構示意圖；圖2為根據本發明實施例提供的另一種晶片封裝結構的剖面結構示意圖。
圖3a-圖3f為根據本發明實施例的一種晶片封裝結構的製造工藝流程中各個製程步驟形成結構的剖面示意圖。
以下將參照圖式更詳細地描述本發明。在各個圖式中，相同的組成部分採用類似的圖式元件符號來表示。為了清楚起見，圖式中的各個部分沒有按比例繪製。此外，可能未說明某些習知的部分。為了簡明起見，可以在一幅圖中描述經過數個步驟後獲得的結構。在下文中描述了本發明的許多特定的細節，例如每個組成部分的結構、材料、尺寸、處理製程和技術，以便更清楚地理解本發明。但正如本領域的具有通常知識者能夠理解的那樣，可以不按照這些特定的細節來實現本發明。
圖1為根據本發明實施例提供的一種晶片封裝結構的剖面結構示意圖。
如圖1所示，在本實施例中，所述晶片封裝結構包括引線框架01、第一導電柱02、第一晶片03、第一電連接體04、第一塑封體05、第二引腳06、第二塑封體07。
在本實施例中，引線框架01包括承載盤011和位於承載盤周圍的第一引腳012，第一引腳012的個數可以為一個也可以為多個，其可根據第一晶片03的有源面上電極焊盤的個數以及第一晶片03的有源面上的電路來設定。形成引線框架01的材料可以為銅等導電材料，則第一引腳和承載盤均可導電，當然，在形成所述引線框架時，若晶片與所述承載盤相接觸的一面上沒有電極，則承載盤不要求一定為導電材質，只要第一引腳確保為導電材料即可。
第一導電柱02位於第一引腳012上，且與第一引腳 012電連接，其形成材料可以與所述第一引腳的材料相同，例如二者可均為銅材料。第一導電柱02具有一定的高度，該高度一般只要確保第一導電柱02與第一引腳012的疊加高度，後續安裝與承載盤011上的晶片和承載盤011的疊加厚度即可。
第一晶片03具有有源面和與有源面相對的背表面，所述背表面貼裝於承載盤011上。所述背表面也可以設置有電極焊盤，可稱為背表面電極焊盤。若第一晶片03的背表面上具有背表面電極焊盤時，該背表面電極焊盤可透過焊料或導電膠貼裝於承載盤011上，則透過承載盤011引出背表面電極。當然第一晶片03的背表面貼裝於承載盤011上的方式不限定於此。此外，在一些應用中，若希望承載盤011所引出的電極與一個第一引腳012引出的電極電連接，可以透過使承載盤011與一個第一引腳012電連接來實現，例如使承載盤011與第一引腳012相連接，或者使承載盤011具有一個延伸部分，且該延伸部分作為一個第一引腳012，以與第一晶片03的有源面上電極焊盤電連接。在第一晶片03的有源面的電極焊盤上設置有第一電連接體04，其形成材料可以與所述第一導電柱02的相同，例如也可以為銅，其用於將第一晶片03有源面上的電極焊盤與外部元件(例如引腳)電連接。
第一塑封體05，用於包封(全部封住)第一晶片03和囊封(不完全封住)所述引線框架01，以防止外部水汽或其它污染物損壞第一晶片03中的有源裝置。通常情 況下，引線框架01、第一導電柱02以及第一電連接體4也會被第一塑封體05囊封(不完全包封)，但是，第一導電柱02和第一電連接體04必須得裸露在第一塑封體05的第一表面，以與其它元件(如引腳)電連接，而第一引腳012必須的裸露於第一塑封體05的第二表面，以與其它元件電連接。其中，第一塑封體05的第一表面為其第二表面相對一面。若承載盤011不與晶片03的電極焊盤電連接，其可不裸露於所述第二表面，否則，也需要裸露於所述第二表面，以與其它元件電連接。
第二引腳06位於第一塑封體05的第一表面上，且將第一導電柱02和第一電連接體04電連接。第二引腳06的個數可以為一個或多個，一般根據第一引腳012的數目來確定，其形成材料可與第一導電柱02以及第一電連接體04均相同，例如也可以為銅。每一個第二引腳06將一個第一電連接體04與一個第二導電柱02電連接。
繼續參考圖1所示，本實施例提供的晶片封裝結構，還包括第二塑封體07，其位於第一塑封體05的第一表面之上，以用於包封所述第二引腳06。第一塑封體05與第二塑封體07的形成材料可相同，例如二者均可為環氧樹脂模塑膠、環氧塑封料等。
由上可見，在本發明提供的晶片封裝結構中，晶片有源面上的電極焊盤透過由第一電連接體、第二引腳、第一導電柱以及第一引腳構成導電路徑引出，最終由第一引腳實現晶片與外部電路之間的電連接。這種引出電極的方 式，由於第二引腳和第一導電柱的截面(與電流流向垂直方向的截面)面積與導電路徑的長度之比遠大於引線鍵合的截面與導電路徑的長度之比。因此，本發明的這種引出電極的方式，相比引線鍵合的方式，可有效的降低封裝電阻，且由於本發明的這種方式無需採用焊料焊接，可避免虛焊現象，可提高晶片封裝的可靠性。此外，由於第二引腳的厚度可以做得比較薄，使得晶片的封裝厚度更加接近裸晶片的厚度，可更好的迎合人們對裝置薄型化的需求。
圖2為根據本發明實施例提供的另一種晶片封裝結構的剖面結構示意圖。
請參考圖2，本實施例所提供的晶片封裝結構相對於圖1所示的晶片封裝結構來說，引線框架01還包括同樣位於承載盤011周圍的第三引腳013，其形成材料可與第一引腳012相同，所述晶片封裝結構還包括第二導電柱08、第四引腳09、第二晶片10、第二電連接體11。
第二導電柱08形成於第三引腳013之上，且與第三引腳電連接，其形成材料可於第三引腳013相同，例如金屬銅。同樣第二導電柱08也具有一定的高度，其可以與第一導電柱02的高度相同，且第二導電柱08也位於第一塑封體05之中，且其裸露於第一塑封體05的第一表面上。
第四引腳09位於第一塑封體05的第一表面上，且與第二導電柱08電連接，其與第三引腳處於同一平面，且二者可採用相同的材料形成，例如金屬銅。第四引腳09 的個數可以為一個或多個，一般由第二晶片10的有源面上的電極或電路來決定。
第二晶片10的有源面朝向第一塑封體05的第一表面，且位於該有源面的電極焊盤透過第二電連接體11與第四引腳09電連接，第二晶片10的有源面的電極焊盤也可透過第二電連接體11與第二引腳06電連接，第二電連接體11可以為導電凸塊或者焊料。在其它實施例中，第二晶片10的有源面也可背向第一塑封體05的第一表面，即第二晶片10與其有源面相對的一面(背表面)放置於所述第一表面之上，第二晶片10的有源面上的電極焊盤透過第二電連接體11電連接到所述第四引腳09或第二引腳06上，第二電連接體可以為金屬引線。
此外，第四引腳09和第二晶片10也被所述第二塑封體07包封，由此可見，在本實施例的晶片封裝結構中，第二晶片上電極可透過第二電連接體、第四引腳以及第三引腳組成的路徑引出，最終透過第三引腳實現與第二晶片與外部電路之間的電連接，此外，第二晶片上的電極還可先透過第二電連接體、第二引腳、第一電連接體組成的導電路徑與第一晶片的電極電連接後，再透過第一電連接體、第二引腳、第一導電柱以及第一引腳組成的導電路徑引出，最終透過第一引腳實現與外部電路的電連接。因此，本發明所提供的晶片封裝結構還可實現多晶片的疊層封裝，且在多晶片的封裝元件中，由於導電路徑的電流處理能力較強， 且無需使用引線鍵合，可有效的提高了晶片封裝的可靠性，降低了封裝電阻和厚度。
本發明還提供了一種晶片封裝結構的製造方法，下面將以具體實施例來進一步詳細的闡述本發明提供的晶片封裝結構的製造方法。
圖3a-圖3f為根據本發明實施例的一種晶片封裝結構的製造工藝流程中各個製程步驟形成結構的剖面示意圖。
參考圖3a所示，在封裝基板00上形成具有承載盤011和第一引腳012的引線框架01，第一引腳012位於承載盤011周圍。形成引線框架01的方法可具體包括：先在封裝基板00上形成一層第一導電層，例如銅層，然後圖案化(利用掩模進行蝕刻製程來實現)第一導電層，使得第一導電層形成具有位於中間的承載盤和位於周圍的第一引腳的引線框架10。當然，具有這樣特徵的引線框架10也可以直接提供，或者透過其它方式來製備。此外，在形成引線框架01時，也可使形成的承載盤011具有一個延伸部分，且使該延伸部分作為一個第一引腳012，以實現承載盤011與一個第一引腳012的電連接，即在製作所述引線框架01時，使承載盤011和一個第一引腳012一體成型。
參考圖3b所示，在第一引腳012上形成第一導電柱02，第一導電柱02與第一引腳012電連接，且具有一定的高度，該高度根據後續需要封裝的晶片的厚度來決定。可以採用電鍍的方式在第一引腳012上形成第一導電柱 02，第電鍍材料可以選用與第一引腳012相同的材料，例如金屬銅。
參考圖3c所示，將第一晶片03的背表面貼裝於承載盤011上，所述背表面為與第一晶片03的有源面相對的一面，第一晶片03的有源面的電極焊盤上設置有第一電連接體04，可透過在第一晶片03的有源面的電極焊盤上形成金屬層或導電凸塊形成第一電連接體04。若所述背表面上具有背表面電極，則可使背表面電極透過焊料或導電膠貼裝於承載盤011上，以與承載盤011電連接。若承載盤011的延伸部分作為一個第一引腳012，則實現了該第一引腳所引出的電極與承載盤011所引出電極電連接。
參考圖3d所示，採用塑封料，進行第一塑封製程，使塑封料覆蓋於封裝基板之上，用於包封(包封指全部封住，即第一晶片沒有被第一塑封體裸露在外的部分)第一晶片03和囊封(囊封指不完全封住，即引線框架還有一部分裸露在第一塑封體之外)所述引線框架01，以形成具有第一表面和與第一表面相對的第二表面的第一塑封體05，其中，使第一導電柱02和第一電連接體04均裸露於所述第一表面上。為實現具有這樣特性的第一塑封體05，在完成第一次塑封製程後，塑封料可能會覆蓋在第一導電柱02和第一電連接體04之上，因此，還需要研磨塑封體05的第一表面，直到所述第一表面裸露出所述第一導電柱02和第一電連接體04為止。
參考圖3e所示，在第一塑封體05的第一表面上形成 將所述第一導電柱02和第一電連接體04實現電連接的第二引腳06。形成第二引腳06的具體方法可以包括：在所述第一表面上形成第二導電層，圖案化第二導電層，以形成第二引腳。第二引腳的數量可以為一個或多個，其由第一晶片03的有源面上的電極或電路來決定。每一個第二引腳06將一個第一導電柱02和之上一個第一電連接體04電連接。
繼續參考圖3f所示，進一步的，還可在所述第一表面上利用塑封料，進行第二次塑封製程，使塑封料包封第二引腳06，以形成第二塑封體07。在形成第二塑封體07後，去除封裝基板00，使所述第一引腳012和承載盤011均裸露於所述第一塑封體05的第二表面上，便可獲得如圖1所示的晶片封裝結構，所述第二表面為與所述第一表面相對的一面。
由上可見，在本發明提供的晶片封裝結構的製造方法中，使晶片有源面上的電極焊盤透過由第一電連接體、第二引腳、第一導電柱以及第一引腳構成導電路徑引出，最終由第一引腳實現晶片與外部電路之間的電連接。這種引出電極的方式，第二引腳和第一導電柱的截面(與電流流向垂直方向的截面)面積與導電路徑的長度之比遠大於引線鍵合的截面與導電路徑的長度之比。因此，本發明的這種引出電極的方式，相比引線鍵合的方式，可有效的降低封裝電阻，且由於本發明的這種方式無需採用焊料焊接，可避免虛焊現象，可提高晶片封裝的可靠性。此外，由於 第二引腳的厚度可以做得比較薄，使得晶片的封裝厚度更加接近裸晶片的厚度，可更好的迎合人們對裝置薄型化的需求。
進一步的，在上述製程過程中，還可加入下列過程，在所述封裝基板上形成述引線框架01時，還可使形成的引線框架01還包括同樣位於所述承載盤011周圍的第三引腳013。
在將第一晶片03的背表面貼裝於所述承載盤011上之前，在所述第三引腳上形成第二導電柱08，在形成所述第一塑封體05時，使所述第一表面裸露還出所述第二導電柱08。第二導電柱08的形成方法與在第一引腳012上形成第一導電柱02的方法可相同，二者可在同一個製程步驟中形成。
在形成所述第一塑封體05之後，在所述第一表面上形成與所述第二導電柱08電連接的第四引腳09，第四引腳09可與第三引腳06在同一個製程步驟中形成。
將第二晶片10的有源面朝向第一塑封體05的第一表面，將其上的電極焊盤透過第二電連接體11電連接到所述第四引腳上，以使第二晶片10上電極透過與第四引腳09電連接的第三引腳08引出，以與外部電路電連接，其中第二電連接體11可以為導電凸塊或者焊料。此外，在其它實施例中，還可使第二晶片10的有源面背向第一塑封體05的第一表面，即將第二晶片10的背表面放置於第一塑封體05的第一表面之上，再將有源面的電極焊盤透 過第二電連接體11與第四引腳09或第二引腳06電連接。其中，第二晶片10的背表面為與有源面相對的一面，第二電連接體11可以為金屬引線。
更進一步的，在進行該步驟的同時，還可使第二晶片10的有源面上的電極焊盤透過第二電連接體11電連接到所述第二引腳06上，以先實現第二晶片10與第一芯03片之間的電連接，然後再將二者連接的節點引出與外部電路連接。
在形成第二塑封體07時，使所述第二塑封體07還包封所述第四引腳09、第二晶片10。此外，在在形成第一塑封體05時，使所述第二表面還裸露出所述第三引腳08，以使第三引腳可與外部電路電連接。
由此可見，本發明提供的晶片封裝結構的製造方法還可實現多晶片層的封裝，使第二晶片上電極可透過第二電連接體、第四引腳以及第三引腳組成的路徑引出，最終透過第三引腳實現與第二晶片與外部電路之間的電連接，此外，第二晶片上的電極還可先透過第二電連接體、第二引腳、第一電連接體組成的導電路徑與第一晶片的電極電連接後，再透過第一電連接體、第二引腳、第一導電柱以及第一引腳組成的導電路徑引出，最終透過第一引腳實現與外部電路的電連接。因此，透過本發明所提供的晶片封裝結構的製造方法形成的晶片封裝結構由於導電路徑的電流處理能力較強，且無需使用引線鍵合，可有效的提高了晶片封裝的可靠性，降低了封裝電阻和厚度。
依照本發明的實施例如上文所述，這些實施例並沒有詳盡敘述所有的細節，也不限制該發明僅為所述的具體實施例。顯然，根據以上描述，可做很多的修改和變化。本說明書選取並具體描述這些實施例，是為了更好地解釋本發明的原理和實際應用，從而使所屬技術領域具有通常知識者能很好地利用本發明以及在本發明基礎上的修改使用。本發明僅受申請專利範圍及其全部範圍和均等物的限制。
01‧‧‧引線框架
02‧‧‧第一導電柱
03‧‧‧第一晶片
04‧‧‧第一電連接體
05‧‧‧第一塑封體
06‧‧‧第二引腳
07‧‧‧第二塑封體
011‧‧‧承載盤
012‧‧‧第一引腳

Claims (14)

  1. 一種晶片封裝結構的製造方法，包括：在封裝基板上形成第一導電層；圖案化該第一導電層，以形成具有承載盤和第一引腳的引線框架，該第一引腳位於該承載盤周圍；採用電鍍製程，在該第一引腳上形成與該第一引腳電連接的第一導電柱；將第一晶片的背表面貼裝於該承載盤上，該背表面為與該第一晶片的有源面相對的一面；在該第一晶片的有源面的電極焊盤上形成金屬層或導電凸塊作為第一電連接體；進行第一次塑封製程，以形成包封該第一晶片和囊封該引線框架的第一塑封體，且使該第一塑封體的第一表面裸露出該第一導電柱和該第一電連接體；在該第一表面上形成第二導電層；圖案化該第二導電層，以形成該第二引腳；進行第二次塑封製程，以形成包封該第二引腳的第二塑封體；去除該封裝基板，以使第二表面裸露出該第一引腳和該承載盤，該第二表面為與該第一表面相對的一面。
  2. 一種根據申請專利範圍第1項所述的製造方法形成的晶片封裝結構，包括：引線框架，具有承載盤和位於該承載盤周圍的第一引腳； 位於該第一引腳上且與該第一引腳電連接的第一導電柱；第一晶片，具有有源面和與該有源面相對的背表面，該背表面貼裝於該承載盤上，該有源面的電極焊盤上設置有第一電連接體；第一塑封體，用於包封該第一晶片和囊封該引線框架，且具有第一表面和與該第一表面相對的第二表面，其中，該第一表面裸露出該第一導電柱和該第一電連接體，該第二表面裸露出該第一引腳；位於該第一表面上的第二引腳，用於將該第一電連接體和該第一導電柱電連接，其中，該第一導電柱和該第一引腳的疊加高度等於該第一晶片、該承載盤、該電極焊盤和該第一電連接體的疊加高度；用於包封該第二引腳的第二塑封體。
  3. 根據申請專利範圍第2項所述的晶片封裝結構，其中，還包括用於包封該第二引腳的第二塑封體。
  4. 根據申請專利範圍第3項所述的晶片封裝結構，其中，該第二表面上還裸露出該承載盤。
  5. 根據申請專利範圍第4項所述的晶片封裝結構，其中，該背表面具有背面電極焊盤，該背面電極焊盤透過焊料或導電膠貼裝於該承載盤上。
  6. 根據申請專利範圍第5項所述的晶片封裝結構，其中，該承載盤與一個該第一引腳電連接。
  7. 根據申請專利範圍第4項所述的晶片封裝結構，其中，該第一引腳、第一導電柱、第一電連接體、第二引腳的形成材料相同。
  8. 根據申請專利範圍第3項所述的晶片封裝結構，其中，該引線框架還具有位於該承載盤周圍的第三引腳，該晶片封裝結構還包括：位於該第三引腳上且與該第三引腳電連接的第二導電柱，該第一表面還裸露出該第二導電柱；位於該第一表面上且與該第二導電柱電連接的第四引腳；位於該第一表面上方，且有源面上的電極焊盤透過第二電連接體電連接到該第四引腳上的第二晶片；該第二塑封體還用於包括該第四引腳、第二晶片；該第二表面上還裸露出該第三引腳。
  9. 根據申請專利範圍第8項所述的晶片封裝結構，其中，該第二晶片的有源面上的電極焊盤透過第二電連接體與該第二引腳電連接。
  10. 根據申請專利範圍第9項所述的晶片封裝結構，其中，該第二電連接體為導電凸塊、焊料、金屬引線中的一種。
  11. 根據申請專利範圍第1項所述的製造方法，其中，形成該引線框架時，使該承載盤與一個該第一引腳一體成型，以實現該承載盤和該第一引腳直接的電連接。
  12. 根據申請專利範圍第1項所述的製造方法，其 中，該背表面具有背面電極焊盤，該背面電極焊盤透過焊料或導電膠貼裝於該承載盤上。
  13. 根據申請專利範圍第1項所述的製造方法，其中，在該封裝基板上形成的該引線框架還包括位於該承載盤周圍的第三引腳，該製造方法還包括：在將第一晶片的背表面貼裝於該承載盤上之前，在該第三引腳上形成第二導電柱，在形成該第一塑封體時，使該第一表面裸露出該第二導電柱；在形成該第一塑封體之後，在該第一表面上形成與該第二導電柱電連接的第四引腳；將第二晶片的有源面上的電極焊盤透過第二電連接體電連接到該第四引腳上；在形成該第二塑封體時，使該第二塑封體還包封該第四引腳、第二晶片；在形成該第一塑封體時，使該第二表面還裸露出該第三引腳。
  14. 根據申請專利範圍第13項所述的製造方法，其中，在將該第二晶片的有源面上的電極焊盤透過該第二電連接體電連接到該第四引腳上時，還使該第二晶片上的有源面上的電極焊盤透過第二電連接體與該第二引腳電連接。
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