CN105720021B - 集成电路封装件及其制造方法 - Google Patents

集成电路封装件及其制造方法 Download PDF

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CN105720021B
CN105720021B CN201610049032.XA CN201610049032A CN105720021B CN 105720021 B CN105720021 B CN 105720021B CN 201610049032 A CN201610049032 A CN 201610049032A CN 105720021 B CN105720021 B CN 105720021B
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CN105720021A (zh
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汪虞
王政尧
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Riyuexin Semiconductor Suzhou Co ltd
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苏州日月新半导体有限公司
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Abstract

本发明是关于集成电路封装件及其制造方法。根据本发明的一实施例的集成电路封装件包含：承载元件，具有相对的第一承载面及第二承载面；至少一第一集成电路元件，设置于该第一承载面；第一注塑壳体，设置于该第一承载面且塑封该第一集成电路元件；至少一第二集成电路元件，设置于该第二承载面；若干导通柱，设置于该第二承载面且经配置以与该第一集成电路元件及该第二集成电路元件电连接；及第二注塑壳体，设置于该第二承载面且塑封该第二集成电路元件与该若干导通柱，其中该导通柱远离该第二承载面的底部暴露于该第二注塑壳体外。本发明可满足电子产品日趋功能强大而尺寸缩小的需求。

Description

集成电路封装件及其制造方法
技术领域
本发明涉及半导体领域技术，特别涉及半导体领域中的集成电路封装件及其制造方法。
背景技术
通常，集成电路封装件所封装的集成电路元件，如裸片等都设置在封装基板或导线框架条等承载元件的一侧，而承载元件的另一侧则集中提供输入/输出(I/O)引脚。即，这些集成电路封装件采用的是单面封装的方式。依照这种传统的封装方式，随着所要封装的集成电路元件数量越来越多，该集成电路封装件的体积也相应增大。虽然可提供选择采用肩并肩或堆叠方式在集成电路封装件的平面尺寸或高度上取得折中或期待材料等相关技术的进一步发展，然面对市场对电子产品尺寸日益严苛的要求，如何在现有的技术条件下尽可能降低集成电路封装件的尺寸是业界一直关切的问题。
发明内容
本发明的目的之一在于提供一集成电路封装件及其制造方法，其可充分利用现有的封装条件而进一步降低集成电路封装件的尺寸。
根据本发明的一实施例，一集成电路封装件包含：承载元件，其选自封装基板与导线框架中一者，该承载元件具有相对的第一承载面及第二承载面；至少一第一集成电路元件，设置于该承载元件的第一承载面；第一注塑壳体，设置于该承载元件的第一承载面且塑封该第一集成电路元件；至少一第二集成电路元件，设置于该承载元件的第二承载面；若干导通柱，设置于该承载元件的第二承载面且经配置以与该第一集成电路元件及该第二集成电路元件电连接；及第二注塑壳体，设置于该承载元件的第二承载面且塑封该第二集成电路元件与该若干导通柱，其中该导通柱远离该第二承载面的底部暴露于该第二注塑壳体外。
在本发明的一实施例中，所暴露的该导通柱的底部是经电镀或化学镀金处理。集成电路封装件进一步包含溅镀于其外表面的信号屏蔽层。该导通柱的最小平面尺寸为250um*250um，最小高度为170um。集成电路封装件的厚度可小于1mm，甚至控制为小于等于0.8mm。
本发明的另一实施例还提供了一制造集成电路封装件的方法，其可制造上述集成电路封装件，具体包含：提供一承载元件，其选自封装基板与导线框架中一者，该承载元件具有相对的第一承载面及第二承载面，且该第二承载面上设有若干导通柱；将多个第二集成电路元件封装于该承载元件的第二承载面，其包含注塑形成塑封该第二集成电路元件与该导通柱的第二注塑壳体；将多个第一集成电路元件封装于该承载元件的第一承载面，其包含注塑形成塑封该第一集成电路元件的第一注塑壳体；研磨该第二注塑壳体的底面以暴露该导通柱远离该第二承载面的底部；以及对所暴露的该导通柱的底部作抗氧化处理。在一实施例中，该制造集成电路封装件的方法进一步包含在将多个第二集成电路元件封装于承载元件的第二承载面后将所封装的中间品分为多个区块，每一区块包含多个封装单元；将多个区块放置并固持于承载基板框架的相应承载位置；及在将多个第一集成电路元件封装于承载元件的第一承载面后将多个区块自承载基板框架释放。其中将多个区块固持于承载基板框架的相应承载位置包含在第二注塑壳体所在侧使用黏胶带将多个区块与承载基板框架固定为一体。
本发明实施例提供的集成电路封装件及其制造方法，可在承载元件的两面均设置封装结构，从而在实现功能多样的复杂集成电路封装件时亦可有效的控制产品的尺寸，满足电子产品日趋功能强大而尺寸缩小的需求。
附图说明
图1所示是根据本发明一实施例的集成电路封装件的剖面侧视图
图2a-2e所示是根据本发明一实施例的制造一集成电路封装件的方法的主要步骤流程示意图，各图示出了相应步骤得到的产品结构的剖面侧视图
图3a-3e所示是根据本发明一实施例的制造集成电路封装件的方法中进行分区作业的流程示意图
具体实施方式
为更好的理解本发明的精神，以下结合本发明的部分优选实施例对其作进一步说明。
图1所示是根据本发明一实施例的集成电路封装件10的剖面侧视图。与现有的单面封装技术不同，本发明采用的是双面封装技术。
具体的，如图1所示，该集成电路封装件10包含一承载待封装元件的承载元件12，其具有相对的第一承载面120及第二承载面122。该承载元件12可选自封装基板与导线框架中一者，本实施例中采用的是封装基板。
该集成电路封装件10进一步包含至少一第一集成电路元件14、至少一第二集成电路元件16，及若干导通柱18。第一集成电路元件14与第二集成电路元件16等
Figure BDA0000914063700000031
封装元件的具体类型和数目可视产品需求决定，如在本实施例中，第一集成电路元件14为两个，而第二集成电路元件16仅一个。该第一集成电路元件14可以惯常的封装方式设置于该承载元件12的第一承载面120，并由设置于该承载元件12的第一承载面120的第一注塑壳体13塑封。类似的，该第二集成电路元件16可以惯常的封装方式设置于该承载元件12的第二承载面122，并由设置于该承载元件12的第二承载面120的第二注塑壳体15塑封。对于一些高频率工作或易受电磁干扰的该集成电路封装件10，还可在该集成电路封装件10的外表面，包含第一注塑壳体13外表面、第二注塑壳体15外表面及承载元件12外侧面等上溅镀一屏蔽层17以进一步提高抗电磁干扰能力。若干导通柱18，可采用常见的铜柱设置于该承载元件12的第二承载面122且经配置以与该第一集成电路元件14及该第二集成电路元件16电连接。具体的，该承载元件12上设有若干电连接结构(未示出)，如迹线(trace)或导通孔(via)等可提供第一集成电路14于第一承载面120上的引脚及第二集成电路16于第二承载面122上的引脚至相应导通柱18的电连接。该导通柱18远离第二承载面122的底部180暴露于第二注塑壳体15外，并经电镀或化学镀金处理以达到抗氧化的作用。
在将该集成电路封装件10连接至外部电路结构(未示出)，如一印刷电路上时，该导通柱18作为集成电路封装件10的外部引脚藉由焊锡等方式安装固定于该外部电路结构上并可实现相应的电连接。
图2a-2e所示是根据本发明一实施例的制造一集成电路封装件10的方法的主要步骤流程示意图，其中各图示出了相应步骤得到的产品结构的剖面侧视图。该方法可制造前述的集成电路封装件10。简单起见，图2a-2e仅示出了对应该一集成电路封装件10的一个封装单元；而在实际生产中如本领域技术人员所了解的是多个封装单元同时进行的。
如图2a所示，首先提供一承载元件12，其选自封装基板与导线框架中一者，该承载元件12具有相对的第一承载面120及第二承载面122，且该第二承载面122上设有若干导通柱18，例如铜柱。该导通柱18可藉由蚀刻，如光蚀刻的方式在该第二承载面122上生成。此外，该承载元件12上设有若干电连接结构(未示出)，如迹线(trace)或导 通孔(via)等可提供第一承载面120上端子与第二承载面122上端子与相应导通柱18间的电连接。
如图2b所示，将多个第二集成电路元件16(每个封装单元为至少一个)封装于该承载元件12的第二承载面122，其包含注塑形成塑封该第二集成电路元件16与该导通柱18的第二注塑壳体15。具体的封装形式有多种，可采用本领域人员所熟知的一些常用封装形式。封装后该第二集成电路元件16的引脚(未示出)可通过锡球或凸块30等与第二承载面122上的相应端子电连接，并藉由电连接结构进一步与相应导通柱18电连接。当然依第二集成电路元件16的类型不同，所采用的电连接形式也有不同，如锡球或凸块30之外还可使用引线32、导电胶34等等。
类似的，如图2c所示，将多个第一集成电路元件14(每个封装单元为至少一个)封装于该承载元件12的第一承载面120，其包含注塑形成塑封该第一集成电路元件14的第一注塑壳体13。具体的封装形式有多种，可采用本领域人员所熟知的常用封装形式。封装后该第一集成电路元件14的引脚(未示出)可通过引线32或锡膏34等与第一承载面120上的相应端子电连接，并藉由电连接结构进一步与相应导通柱18电连接。
如图2d所示，在完成承载元件12两面的初步封装后，研磨该第二注塑壳体15的底面150以暴露该导通柱18远离该第二承载面122的底部180。
接着在图2e中，对所暴露的该导通柱18的底部180以电镀或化学镀金等方式作抗氧化处理。如此，该导通柱18即可用作该集成电路封装件10的外部引脚而与其它外部电路结构电连接。
此外，还可对该集成电路封装件10依性能要求作其它的处理，如在该集成电路封装件10的外表面，包括第一注塑壳体13的外表面、第二注塑壳体15的外表面和承载元件12的外侧面上进一步溅镀一屏蔽层17以进一步提高该集成电路封装件10的抗电磁干扰能力，即可得到图1所示的集成电路封装件10。
此外，根据上述描述，本发明实施例的制造集成电路封装件10的方法需进行两次注塑处理，而且实际生产中是整条承载元件框架条同时进行。为避免第一次注塑处理可能造成的承载元件框架条翘曲对第二次注塑处理的影响，本发明的另一实施例还对上述制造集成电路封装件10的方法作了优化改进，该优化主要体现在完成第一次注塑处理后对所封装的中间品进行分区作业。例如，在将多个第二集成电路元件16封装于承载元件12的第二承载面122后将所封装的中间品分为多个区块，多个区块中每一者包含多个封装单元；将多个区块放置并固持于承载基板框架的相应承载位置；及在将多个第一集成电路元件14封装于承载元件12的第一承载面120后将多个区块自承载基板框架 释放。具体步骤可参照后续描述。
图3a-3e所示是根据本发明一实施例的制造集成电路封装件10的方法中进行分区作业的流程示意图。
图3a所示是将多个第二集成电路元件16封装于承载元件12的第二承载面122后，待封装的承载元件12的第一承载面120的俯视示意图。图中为一整条承载元件框架条20，其中的每一小方格所代表的是每一封装单元200，每一封装单元200对应封装后的一集成电路封装件10。可进一步按设计要求将各封装单元200的第一集成电路元件14及其相关电连接布置于承载元件12的第一承载面120，清楚简便起见，本图及后续图中并未示出第一集成电路元件14、第二集成电路元件16及相关电路。
图3b所示是将封装单元200进行分区后将得到的承载元件区块202安装至承载基板框架(dummy substrate)50的俯视示意图。如图3b所示，将整条承载元件框架条20中的封装单元200进行分区，分区可由本领域技术人员依据具体生产中的模具和制程要求等综合考虑，例如分为两个、三个或四个分区。本实施例中是分为三个承载元件区块202，每一承载元件区块202中仍包含多个封装单元200。承载基板框架50可采用类似于封装基板或导线框架条材质，并定义多个相互间隔的承载位置500(可为收纳承载元件区块202的开口)以将各承载元件区块202放置并固持于其上。
具体的固持方式可有多种，如图3c所示本实施例中是采用黏胶带40粘结的方式实现。即，可在待塑封的相对侧，即第二注塑壳体15所在侧使用黏胶带40将多个承载元件区块202与承载基板框架50固定为一体。简单起见，图中仅示出一个承载元件区块202的固定情形为例。
如图3d所示，在使用黏胶带40将承载元件区块202与承载基板框架50固定为一体的情况下，注塑形成塑封第一集成电路元件14的第一注塑壳体13，遮蔽第一承载面120上的第一集成电路元件14及相应电路，如此即可完成承载元件12两面的初步封装。
然后，如本领域技术人员所理解的，再经过常规的切单制程等，初步分割每一承载元件区块202中的不同封装单元200，然不同封装单元200间仍由黏胶带40连接。接着，如图3e所示，将黏胶带40撕除，即可完成单颗集成电路封装件10的制作。
综上，根据本发明的实施例可提供一种新颖的堆叠封装结构，且其适用于现有的注塑方式，工艺简单，制造成本低。本发明实施例所提供的集成电路封装件10的导通柱18的平面尺寸最小可以做到250um*250um,高度为170um；相较传统3D封装厚度最小约为1mm，根据本发明实施例的集成电路封装件10的整体厚度可以远小于1mm，最小可控制在0.8mm以内。因而本发明实施例提供的集成电路封装件10更轻薄、集成度更高。 同时本发明实施例提供的集成电路封装件10及其制造方法可视需要在集成电路封装件10的外表面上溅镀屏蔽层17，对噪声敏感的封装元件而言，其性能可进一步提升。
本发明的技术内容及技术特点已揭示如上，然而熟悉本领域的技术人员仍可能基于本发明的教示及揭示而作种种不背离本发明精神的替换及修饰。因此，本发明的保护范围应不限于实施例所揭示的内容，而应包括各种不背离本发明的替换及修饰，并为本专利申请权利要求书所涵盖。

Claims (6)

1.一种制造集成电路封装件的方法，其包含：
提供一承载元件，其选自封装基板与导线框架中一者，所述承载元件具有相对的第一承载面及第二承载面，且所述第二承载面上设有若干导通柱；
将多个第二集成电路元件封装于所述承载元件的第二承载面，其包含注塑形成塑封所述第二集成电路元件与所述导通柱的第二注塑壳体；
将多个第一集成电路元件封装于所述承载元件的第一承载面，其包含注塑形成塑封所述第一集成电路元件的第一注塑壳体；
研磨所述第二注塑壳体的底面以暴露所述导通柱远离所述第二承载面的底部；以及
对所暴露的所述导通柱的底部作抗氧化处理；
其中在将所述多个第二集成电路元件封装于所述承载元件的第二承载面后将所封装的中间品分为多个区块，所述多个区块中每一者包含多个封装单元；
将所述多个区块放置并固持于承载基板框架的相应承载位置；及
在将所述多个第一集成电路元件封装于所述承载元件的第一承载面后将所述多个区块自所述承载基板框架释放。
2.如权利要求1所述的制造集成电路封装件的方法，其中对所暴露的所述导通柱的底部作抗氧化处理是电镀或化学镀金所暴露的所述导通柱的底部。
3.如权利要求1所述的制造集成电路封装件的方法，其进一步包含于所述第一注塑壳体与所述第二注塑壳体外与所述承载元件的侧面溅镀信号屏蔽层。
4.如权利要求1所述的制造集成电路封装件的方法，其中所述导通柱的最小平面尺寸为250um*250um，最小高度为170um。
5.如权利要求1所述的制造集成电路封装件的方法，其中所述提供一承载元件进一步包含藉由光蚀刻方式在所述第二承载面上生成所述导通柱。
6.如权利要求1所述的制造集成电路封装件的方法，其中将所述多个区块固持于承载所述基板框架的相应承载位置包含在所述第二注塑壳体所在侧使用黏胶带将所述多个区块与所述承载基板框架固定为一体。
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