TW201318138A - 晶圓等級應用上的射頻遮蔽件 - Google Patents

晶圓等級應用上的射頻遮蔽件 Download PDF

Info

Publication number
TW201318138A
TW201318138A TW101137769A TW101137769A TW201318138A TW 201318138 A TW201318138 A TW 201318138A TW 101137769 A TW101137769 A TW 101137769A TW 101137769 A TW101137769 A TW 101137769A TW 201318138 A TW201318138 A TW 201318138A
Authority
TW
Taiwan
Prior art keywords
wafer
metal layer
integrated circuit
back side
shield
Prior art date
Application number
TW101137769A
Other languages
English (en)
Inventor
David Clark
Theodore G Tessier
Original Assignee
Flipchip Int Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Flipchip Int Llc filed Critical Flipchip Int Llc
Publication of TW201318138A publication Critical patent/TW201318138A/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/552Protection against radiation, e.g. light or electromagnetic waves
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15192Resurf arrangement of the internal vias
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

根據本揭露案,揭示一種在積體電路晶片上形成晶片上RF屏蔽之方法的實施例,包括以下步驟:提供晶圓級積體電路元件晶圓,該晶圓級積體電路元件晶圓在分割之前具有前側及背側;在晶圓的背側施加樹脂金屬層;及接著將晶圓分開成分立的RF屏蔽元件。在分割成為分立的RF屏蔽元件(亦即,晶圓的分開)之後,是背側上的此樹脂金屬層能夠有效地作用為RF屏蔽。

Description

晶圓等級應用上的射頻遮蔽件 【相關申請案的交叉參考】
本申請案主張於2011年10月13日之美國臨時專利申請案,案號為61/546,862,標題為「Wafer Level Applied RF Shields」之益處,所揭示之內容在此處整體併入作為參考。
本揭露案大致關於半導體晶片的形成,且更具體而言,係關於製造晶片上RF屏蔽對植入式晶粒封裝體用於主動、被動或分立元件的結構及方法。
在某些電子封裝應用中,保護裝置及系統電路遠離電磁干擾(EMI)的來源係必要的。確保所述的裝置或系統電路不傳送EMI輻射至其外部的系統亦為重要的。藉此,確保此等系統的能力為意圖操作於特定電磁環境之中。
EMI的亂真來源可導致整體系統或積體電路的性能降級,舉例而言,透過雜訊、串擾及降低訊號對雜訊的比率。EMI在混合的訊號電路中特別具有困擾。
EMI爭議典型地藉由射頻(RF)屏蔽解決,其中有問題的電路藉由專屬的金屬RF屏蔽遮蓋。在EMI訊號來 源及系統電路之間導電且接地的屏蔽(亦稱作法拉第屏蔽)將消除此雜訊,方法為藉由佈線引導EMI感應的位移電流直接至接地。
此RF屏蔽通常藉由表面安裝技術(SMT)安裝至系統印刷配線板(PWB)上,且可包覆單一或多重元件,例如主動、被動或分立的裝置。
在植入式晶粒封裝應用中,RF屏蔽特別具有挑戰性。使用傳統表面安裝的RF屏蔽可能強加PWB佈線設計的限制,且可能在靠近EMI敏感元件或在EMI敏感元件上方強加淨空區域。
在植入式晶粒應用中,直接在植入式元件上方的PWB外部表面區域能夠用於進一步元件密度及整合將為高度合意的。將此高價值的表面區域占地面積以低價值添加RF屏蔽元件來消費係非所欲的。
在某些PWB設計中,整體PWB層可專用於提供數位或類比接地平面,因此對元件提供進一步的EMI保護。將整體的PWB層專用於EMI保護可為昂貴的解決方案,且此層進一步禁止佈線放置於EMI保護的區域中。
表面安裝的PWB或其他RF屏蔽係典型地透過存在的PWB電路連接至系統電氣接地平面。
表面安裝的RF屏蔽典型地在PWB表面上形成最高點。因此,RF屏蔽可能常常限制總體封裝或產品的厚度。
表面安裝的RF屏蔽完全包覆敏感元件,而在屏蔽的周圍四周作成對PWB的接觸,且因此趨向增加元件或系統 的底面積(footprint)。此外,表面安裝RF屏蔽可產生整體晶片封裝形狀的翹曲。
根據本揭露案的方法解決上述之缺陷。根據本揭露案,一種在積體電路晶片上形成晶片上RF屏蔽的方法之實施例包括以下步驟:在分割之前提供晶圓級積體電路元件晶圓,該晶圓級積體電路元件晶圓具有前側及背側;在晶圓的背側上施加樹脂金屬層;及接著將晶圓分開成分立的RF屏蔽元件。正是在背側上的此樹脂金屬層能夠有效地對晶圓上的元件作用為RF屏蔽。樹脂金屬層較佳地包括金屬箔,且亦可在層的外部表面具有平面銅箔。
根據本揭露案的另一實施例係一種從晶圓級積體電路元件晶圓切割的積體電路晶片,該晶圓級積體電路元件晶圓具有前側及背側,及形成於晶圓的至少背側上的樹脂金屬層。晶圓亦可具有在晶圓的前側上覆蓋元件的樹脂金屬層。樹脂金屬層較佳地包括金屬箔。此金屬箔較佳地為在其外部表面上的銅箔。在晶片上的金屬層可為樹脂銅箔(RCF)層。在此實施例中,RCF層係施加在晶圓的背側上的導電膏狀物,該導電膏狀物覆蓋晶圓上的至少一個元件。此導電膏狀物亦可施加在晶圓的前側上,覆蓋晶圓上的另一元件。
本揭露案提供一種低成本的方法用於RF屏蔽的晶圓級應用,以在多重電子封裝形式及應用中使用。此方法特別實用於植入式晶粒封裝應用,以提供高產能晶圓級所施加的RF屏蔽。
1圖圖示在印刷配線板(PWB)上的典型EMI屏蔽系統。單一或多重主動及/或被動元件100與表面安裝的分立元件110一起可用於形成電子系統。元件係安裝在典型的印刷電路或配線板120上。在元件之間的導電性係使用標準的PWB貫孔130及重新分配軌跡140而作成。典型的SMT板所安裝的RF屏蔽150覆蓋系統元件,且透過PWB電路連接至電氣接地160。RF屏蔽典型地在元件170的周圍短路或者膠合至PWB。
2a圖根據本揭露案,圖示在晶圓級製程之後及分割之前(亦即,在分開成分立的元件之前)的可植入電子積體電路元件晶圓200。元件晶圓200包括複數個積體電路元件,且亦含有前側210的積體電路,該前側210具有定義的面板220,用於導電至印刷配線板。具有銅箔240的樹脂層230(稱為RCF層)係於晶圓級施加,因而在裝置分割之前形成晶片上預備RF屏蔽。
根據本揭露案的製程包括以下的操作步驟:(1)在分割之前從晶圓代工廠提供晶圓級元件晶圓;(2)施加樹 脂金屬箔層至晶圓的至少背側,因而形成屏蔽晶圓;(3)接著將屏蔽晶圓分開成分立的元件。箔層係較佳地為銅。然而,可替代地使用其他導電性金屬,例如金、銀、含銀合金、或含銅合金。
2b圖圖示在晶圓級晶片尺度封裝形式中的電子元件200,該電子元件200具有如第2a圖中在元件背側上所形成的晶圓級施加的RF屏蔽。在所顯示的晶片尺度封裝(CSP)形式中,銅膏狀物所填充的貫孔250提供RF屏蔽層及主體半導體基板之間的電氣接地連接。
3圖圖示併入如第2圖中所顯示而產生的EMI屏蔽元件300之植入式晶粒包裝配置250。所顯示的主動、被動或分立元件300係植入於PWB基板310之中。封裝體250亦具有表面安裝的主動或被動ICs 320,且伴隨著分立元件330。在植入式元件300及表面安裝的元件320330之間的導電性係使用傳統的貫孔340及重新分配線路350作成。植入式元件300包括形成晶片上RF屏蔽的背側RCF層360。晶片上RF屏蔽係透過存在的PWB電路連接至系統接地平面370
根據本揭露案的晶圓級RF屏蔽可用於各種晶圓級RF屏蔽解決方案、設計、厚度及幾何形狀,而無須顯著地添加處理複雜度或成本。
在某些應用中,EMI保護樹脂銅箔(RCF)層亦可施加至晶圓級晶圓的前側,以便全然地包覆元件。RCF層可利用亦為導電性的銅以外的其他金屬合金,以便提供 RF屏蔽。因此,根據本揭露案,在分割之後的個別元件含有專屬的RF屏蔽特徵,而可用於局部的EMI保護。樹脂銅箔層係用於將來自EMI來源的感應的雜訊電流引導至系統電氣接地。
根據本揭露案建構的RF屏蔽元件係特別可應用但非限於各種最終元件封裝形式,包括倒裝晶片封裝、系統中封裝、植入式晶粒封裝及其他多晶粒、多重分立3D封裝。此方法特別合意用於植入式晶粒封裝體。
此處所述的方法改善植入式晶粒封裝體之中的元件附著力,且改善植入式晶粒封裝體之中積體電路層的逸氣。RCF EMI屏蔽層可為適合用於特定RF頻率過濾需求的保形層或圖案層。樹脂層可選擇具有高k的材料特性,以幫助降低電容耦合的EMI來源。
此方法相較於本領域最新技術的電鍍的晶片上替代物提供更低成本的解決方案,且此方法亦可幫助熱消散。此外,根據本揭露案的晶片上RF屏蔽可消除在外部施加RF屏蔽之使用將可能發生的潛在整體封裝的翹曲。再者,晶片上RF屏蔽可用於表面安裝配置中,其中接地訊號係藉由附加背側接線之方式提供。可作成的所有此等替代物及特徵舉例說明了在定義及本揭露案的廣義範疇之中的修改,且為在以下的申請專利範圍中的範例。
100‧‧‧主動及/或被動元件
110‧‧‧分立元件
120‧‧‧配線板
130‧‧‧PWB貫孔
140‧‧‧重新分配軌跡
150‧‧‧RF屏蔽
160‧‧‧電氣接地
170‧‧‧元件
200‧‧‧可植入電子積體電路元件晶圓
210‧‧‧前側
220‧‧‧面板
230‧‧‧樹脂層
240‧‧‧銅箔
250‧‧‧貫孔
300‧‧‧EMI屏蔽元件
310‧‧‧PWB基板
320‧‧‧主動或被動ICs
330‧‧‧分立元件
340‧‧‧貫孔
350‧‧‧重新分配線路
360‧‧‧背側RCF層
370‧‧‧系統接地平面
為了更加完整地瞭解本揭露案,現參考以下圖式,其中:第1圖係典型的EMI保護的印刷配線板(PWB)之概要截面視圖。
2a圖係根據本揭露案的可植入電子積體電路元件之概要截面視圖。
2b圖係根據本揭露案,在晶圓級晶片尺度封裝形式中第2a圖中所顯示的電子元件之概要截面視圖。
3圖係根據本揭露案透過植入式晶片封裝配置之概要截面視圖。
300‧‧‧EMI屏蔽元件
310‧‧‧PWB基板
320‧‧‧主動或被動ICs
330‧‧‧分立元件
340‧‧‧貫孔
350‧‧‧重新分配線路
360‧‧‧背側RCF層
370‧‧‧系統接地平面

Claims (10)

  1. 一種在一積體電路晶片上形成一晶片上RF屏蔽的方法,包含以下步驟:提供一晶圓級積體電路元件晶圓,該晶圓級積體電路元件晶圓具有一前側及一背側;在該晶圓的至少一背側上施加一樹脂金屬層;及將該晶圓分開成分立的RF屏蔽元件。
  2. 如請求項第1項所述之方法,其中該樹脂金屬層包括在其上的一金屬箔。
  3. 如請求項第1項所述之方法,其中該樹脂金屬層包括在其一外部表面上的一平面銅箔。
  4. 如請求項第1項所述之方法,其中該樹脂金屬層係選自以下構成之群組:銅、金、銀、含金合金、及含銅合金。
  5. 如請求項第1項所述之方法,其中該樹脂金屬層係施加為一膏狀物。
  6. 一種積體電路晶片,包含:一晶圓級積體電路元件晶圓,該晶圓級積體電路元件 晶圓具有一前側及一背側;及一樹脂金屬層,該樹脂金屬層形成於該晶圓的至少該背側上。
  7. 如請求項第6項所述之晶片,其中該樹脂金屬層包括一金屬箔。
  8. 如請求項第7項所述之晶片,其中該金屬箔具有在其一外部表面上的一銅箔。
  9. 如請求項第6項所述之晶片,其中該金屬層係一樹脂銅箔(RCF)層。
  10. 如請求項第9項所述之晶片,其中該RCF層係在該晶圓的該背側上的一膏狀物,該膏狀物係覆蓋該晶圓上的至少一個元件。
TW101137769A 2011-10-13 2012-10-12 晶圓等級應用上的射頻遮蔽件 TW201318138A (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US201161546862P 2011-10-13 2011-10-13

Publications (1)

Publication Number Publication Date
TW201318138A true TW201318138A (zh) 2013-05-01

Family

ID=48082348

Family Applications (1)

Application Number Title Priority Date Filing Date
TW101137769A TW201318138A (zh) 2011-10-13 2012-10-12 晶圓等級應用上的射頻遮蔽件

Country Status (6)

Country Link
US (1) US20130093067A1 (zh)
KR (1) KR20140081859A (zh)
CN (1) CN103858227A (zh)
DE (1) DE112012004285T5 (zh)
TW (1) TW201318138A (zh)
WO (1) WO2013055700A1 (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140091440A1 (en) * 2012-09-29 2014-04-03 Vijay K. Nair System in package with embedded rf die in coreless substrate
US9484313B2 (en) 2013-02-27 2016-11-01 Advanced Semiconductor Engineering, Inc. Semiconductor packages with thermal-enhanced conformal shielding and related methods
CN103415136B (zh) * 2013-07-19 2016-12-28 广东威创视讯科技股份有限公司 一种抗电磁干扰的电路板
US11195787B2 (en) 2016-02-17 2021-12-07 Infineon Technologies Ag Semiconductor device including an antenna
US10229887B2 (en) 2016-03-31 2019-03-12 Intel Corporation Systems and methods for electromagnetic interference shielding
US10068854B2 (en) * 2016-10-24 2018-09-04 Advanced Semiconductor Engineering, Inc. Semiconductor package device and method of manufacturing the same
US11183460B2 (en) 2018-09-17 2021-11-23 Texas Instruments Incorporated Embedded die packaging with integrated ceramic substrate
US11031332B2 (en) 2019-01-31 2021-06-08 Texas Instruments Incorporated Package panel processing with integrated ceramic isolation

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2554040Y2 (ja) * 1991-11-07 1997-11-12 株式会社ミツバ 電子部品取付構造
JP3082905B2 (ja) * 1997-01-28 2000-09-04 富士通電装株式会社 チップ・オン・ボード遮蔽構造およびその製造方法
JP2006059839A (ja) * 2004-08-17 2006-03-02 Oki Electric Ind Co Ltd 半導体装置およびその製造方法
CN100514616C (zh) * 2006-08-29 2009-07-15 欣兴电子股份有限公司 内埋式芯片封装制程及具有内埋芯片的电路基板
US7701040B2 (en) * 2007-09-24 2010-04-20 Stats Chippac, Ltd. Semiconductor package and method of reducing electromagnetic interference between devices
US7772046B2 (en) * 2008-06-04 2010-08-10 Stats Chippac, Ltd. Semiconductor device having electrical devices mounted to IPD structure and method for shielding electromagnetic interference
JP2010219210A (ja) * 2009-03-16 2010-09-30 Renesas Electronics Corp 半導体装置およびその製造方法

Also Published As

Publication number Publication date
WO2013055700A1 (en) 2013-04-18
US20130093067A1 (en) 2013-04-18
CN103858227A (zh) 2014-06-11
KR20140081859A (ko) 2014-07-01
DE112012004285T5 (de) 2014-07-31

Similar Documents

Publication Publication Date Title
US9899335B2 (en) Method for fabricating package structure
TW201318138A (zh) 晶圓等級應用上的射頻遮蔽件
US10103106B2 (en) Wafer level fan-out with electromagnetic shielding
US10276401B2 (en) 3D shielding case and methods for forming the same
CN107564891B (zh) 具有集成天线的屏蔽封装
US9362234B2 (en) Shielded device packages having antennas and related fabrication methods
TWI471985B (zh) 晶片封裝體及其製作方法
TWI387070B (zh) 晶片封裝體及其製作方法
US7648858B2 (en) Methods and apparatus for EMI shielding in multi-chip modules
TWI452665B (zh) 具防靜電破壞及防電磁波干擾之封裝件及其製法
WO2017014949A1 (en) System in package (sip) module with emi shield
US20190019764A1 (en) Semiconductor package with electromagnetic interference shielding using metal layers and vias
TWI781735B (zh) 半導體封裝及其製造方法
US20120052630A1 (en) Method for manufacturing chip package
US20170057808A1 (en) Mems chip package and method for manufacturing the same
TWI491009B (zh) 晶片級電磁干擾屏蔽結構及製造方法
TWI853713B (zh) 半導體封裝及其製造方法
US20130134565A1 (en) System-in-package module and method of fabricating the same
KR101535174B1 (ko) 반도체 패키지 및 방법
US20130207246A1 (en) Packaging an Integrated Circuit Die