TWI387070B - 晶片封裝體及其製作方法 - Google Patents

晶片封裝體及其製作方法 Download PDF

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TWI387070B
TWI387070B TW098124438A TW98124438A TWI387070B TW I387070 B TWI387070 B TW I387070B TW 098124438 A TW098124438 A TW 098124438A TW 98124438 A TW98124438 A TW 98124438A TW I387070 B TWI387070 B TW I387070B
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wafer
chip package
substrate
electrical conductors
conductors
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TW201017835A (en
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Dongkyun Ko
Jung Lee
Jaesun An
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Advanced Semiconductor Eng
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Description

晶片封裝體及其製作方法
本發明是有關於一種半導體裝置，且特別是有關於一種晶片封裝體。
電磁干擾(electro-magnetic interference)對於大多數的電子產品或系統而言是一嚴肅且富有挑戰性的問題。由於電磁干擾常中斷、阻礙、降低或限制電子裝置或整體電路系統的效能表現，因此需要有效的電磁干擾屏蔽，以確保電子裝置或系統的效率與安全操作。
電磁干擾屏蔽的效能對於小尺寸、高密度的封裝體或應用於高頻率的敏感電子儀器非常重要。一般而言，大都是藉由增加金屬板與/或導電性的墊圈來提升電磁干擾屏蔽的效能，但此方式會提高製造成本。
本發明提供一種晶片封裝體的製造方法，可提供較佳的設計靈活性。
本發明提供一種具有提升電磁干擾屏蔽效能的晶片封裝體。
本發明提出一種晶片封裝體，其包括一積層基板、至少一配置於積層基板上的晶片、多個導電體、一封裝膠體以及一遮蔽層。導電體配置於積層基板上且環繞晶片。封 裝膠體至少包覆晶片、部分積層基板與導電體，但部分地暴露出這些導電體的多個上表面。遮蔽層配置於封裝膠體上，且覆蓋封裝膠體與部分地覆蓋每一導電體暴露於封裝膠體的上表面。
在本發明之一實施例中，上述之這些導電體可由焊料或部分的導線架或部分的印刷電路板所組成。
在本發明之一實施例中，上述之這些導電體可排列於積層基板的邊界線，且暴露出每一導電體的至少一側壁。
在本發明之一實施例中，上述之這些導電體可沿著積層基板的邊界線排列，且未暴露出每一導電體的多個側壁。
在本發明之一實施例中，上述之晶片透過多個凸塊電性連接至晶片封裝體的積層基板。
本發明提供一種晶片封裝體的製作方法。首先，提供一陣列基板。陣列基板具有多個基板單元，其中每一基板單元是由多條切割線所定義，且每一基板單元上具有一晶片貼附區域。接著，形成多個導電體於每一基板單元上，且這些導電體環繞晶片貼附區域配置。配置至少一晶片於每一基板單元的晶片貼附區域上，其中晶片電性連接至基板單元，且晶片與這些導電體相互分離。形成一封裝膠體於陣列基板上，以包覆晶片、部分這些基板單元與這些導電體。進行一標記製程以移除部分封裝膠體至暴露出每一導電體的一上表面。然後，形成一遮蔽層於封裝膠體上，以覆蓋封裝膠體與每一導電體被暴露出的上表面。最後，進行一單體化製程，以形成多個晶片封裝體。
在本發明之一實施例中，上述之這些導電體排列於陣列基板的這些切割線上與每一基板單元的多條邊界線上，或相距一間隔距離而環繞每一基板單元的這些邊界線配置。
在本發明之一實施例中，上述之這些導電體是由一金屬材料所形成，且這些導電體形成方式包括噴塗法(spraying process)、濺鍍法(sputtering process)或電鍍法(plating process)，或者，這些導電體是由一焊料所形成，且這些導電體形成方式包括噴塗法或印刷法。
在本發明之一實施例中，上述之標記製程包括一雷射挖空製程(laser digging process)或一雷射鑽孔製程(laser drilling process)。
基於上述，遮蔽層與其所連接的導電體配置於基板上的作用可視為晶片封裝體周圍防電磁干擾輻射的電磁干擾屏蔽。在本發明之中，透過遮蔽層與具有彈性且多種設計型態的導電體，即可達成一完整之電磁干擾屏蔽的效果。因此，遮蔽層與導電體可提高晶片封裝體的電磁干擾屏蔽效果，使晶片封裝體具有較佳的電磁干擾屏蔽效能。
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
本發明所述之晶片封裝體的製作方法可用來製作多種封裝結構，其中以製作堆疊式封裝體、多層封裝體或具 有高頻率裝置的封裝體(包括具有射頻裝置的封裝體)最為適合。此外，本發明之晶片封裝體的製作方法與利用積層基板的製造方法或陣列基板的製作方法的封裝製程相互符合。
圖1A至圖1G繪示本發明之一實施例之一種晶片封裝體的製作方法。在此必須說明的是，為了方便說明起見，圖1A、圖1B、圖1B’與圖1C繪示立體示意圖，而1D至圖1G繪示剖面示意圖。
請先參考圖1A，提供一陣列基板100。陣列基板100具有多個基板單元102(是由後續繪示為虛線的切割線所定義)，其中每一基板單元102上包括多個接點104。這些接點104排列於每一基板單元102的晶片貼附區域103內。這些接點104的作用如同覆晶接合技術中的凸塊焊墊。陣列基板100可為一積層基板，其例如是一印刷電路板(Printed Circuit Board,PCB)。
接著，請參考圖1B，多個導電體110形成於每一基板單元102的上表面102a上，且位於晶片貼附區域103外。較佳地，導電體110環繞每一基板單元102的邊界或周長配置。請參考圖1B，這些個別獨立的導電體110排列於基板單元102之邊界線(虛線)上。在本實施例中，後續之切割製程會沿著這些切割線而切穿這些導電體110。
此外，請參考圖1B'，這些個別獨立的導電體110也可沿著基板單元102的邊界線排列，但不位於基板單元102的邊界線(虛線)上。這些導電體110可排列接近於基板 單元102的邊界線，且這些導電體110與基板單元102的邊界線相距一小間隔距離d，而間隔距離d可依據產品的需求而自由調整。因此，後續的切割製程雖然會沿著這些切割線但不會切穿這些導電體110。
導電體110例如是由一焊料所製成。當然，於其他實施例中，導電體110亦可以是一導電承載器的一部分，其中導電承載器例如是一導線架或一積層印刷電路板。導電體110的形狀可為多邊形的塊狀體(請參考圖1B或圖1B’之矩形塊狀體)。當然，導電體110的形狀亦可以是塊狀、條狀或甚至是一彼此相互連接的環狀結構。一般來說，導電體110的形狀或尺寸可依照屏蔽的需要、封裝體電性的特性，或甚至是依據製程的參數而自由調整。
如果是利用一多層基板，例如是一多層印刷電路板，則可藉由積層基板的製作過程中來形成所需之導電體110。也就是說，於形成基板上之走線(trace)的過程中，亦同時形成導電體110，其中導電體110是除了走線之外的圖案化金屬塊。
接著，請參考圖1C，至少一晶片120配置於每一基板單元102的晶片貼附區域103內。雖然在此是提供晶片120配置於晶片貼附區域103內，但其他實施例中，亦可以是提供多個表面黏著型元件貼附於晶片貼附區域103內，此仍屬於本發明可採用的技術方案，不脫離本發明所欲保護的範圍。晶片120透過多個凸塊106(請參考圖1D)電性連接至基板單元102的這些接點104，其中這些凸塊 106介於晶片120與這些接點104之間。雖然在此是以覆晶接合技術作為說明，但於其他實施例中，亦包括利用打線接合技術來電性連接晶片120與這些接點104，仍屬於本發明可採用的技術方案，不脫離本發明所欲保護的範圍。晶片120與這些導電體110彼此完全分離。
接著，請參考圖1D，透過一封膠製程而形成一封裝膠體130於陣列基板100上，以包覆這些導電體110、晶片120、這些凸塊106與至少一部分的基板單元102。封膠製程例如為一陣列封膠製程(over-molding process)。雖然在此所描述之導電體110的高度高於晶片120加凸塊106的整體高度，但於其他實施例中，亦可自由選擇導電體110的高度小於或大於晶片120加凸塊106的整體高度。
接著，請參考圖1E，進行一標記製程以移除部分位於這些導電體110上的封裝膠體130，以至少部分地暴露每一導電體110的上表面110a。這些導電體110的上表面110a可以是部分地或完全地被暴露。標記製程例如是一雷射挖空製程或一雷射鑽孔製程。以導電體110環繞每一基板單元102的邊界配置為例，標記製程可移除部分封裝膠體130，藉以形成一環狀溝渠(ring-like trench)於封裝膠體130內且於導電體110上，並環繞每一基板單元102的邊界。
接著，請參考圖1F，形成一遮蔽層140於封裝膠體130上，以覆蓋封裝膠體130與導電體110被暴露出的上表面110a。遮蔽層140的形成方式包括噴塗法、電鍍法或 濺鍍法。
最後，請參考圖1G，進行一單體化製程，以形成多個獨立的晶片封裝體10。單體化製程例如是一刀片切割製程。
圖2為本發明之一實施例之一種晶片封裝體的剖面示意圖。請參考圖2，在本實施例中，晶片封裝體20包括一基板單元102、多個凸塊106、多個導電體110、至少一晶片120、一封裝膠體130與一遮蔽層140。基板單元102可為一積層基板，其例如是一兩層或一四層積層的印刷電路板基板。晶片120可為一半導體晶片，其例如是一射頻(RF)晶片。遮蔽層140的材質可為銅、鋁、銅鋁合金或是一焊料。晶片120透過凸塊106電性連接至基板單元102。封裝膠體130包覆部分基板單元102、導電體110與晶片120。此外，遮蔽層140配置於封裝膠體130上，且覆蓋封裝膠體130的上表面與這些導電體110被暴露出的上表面110a。遮蔽層140透過這些導電體110電性連接至基板單元102。
舉例來說，導電體110可由一積層印刷電路板或一導線架所組成(例如是一積層印刷電路板或一導線架的一大部分或一小部分)。如果導電體110為一積層印刷電路板的一小部分，遮蔽層140可透過貫穿孔(through vias)或導電體110的電鍍貫穿孔(plated through-holes)而電性連接至基板單元102。如果導電體110為一導線架的一部分，遮蔽層140可透過導電體110而電性連接至基板單元 102，且導電體110可透過導電黏著層固接於基板單元102上，其中導電黏著層例如是一異方性導電膠膜(Anisotropic Conductive Film,ACF)。當然，導電體110亦可由焊料所組成，其例如是焊料塊、焊料條或焊料環狀結構。
此外，導電體110連接至基板單元102的一接地孔108，且遮蔽層140透過導電體110與接地孔108而接地。因此，可利用基板表面的金屬線路或走線作為一接地平面，使本實施例之遮蔽層140可藉由基板的接地平面而接地於封裝結構內。在此必須說明的是，每一導電體110的至少一側壁110b與遮蔽層140的邊緣對齊，而此邊緣即為切割製程時切穿導電體110所排列的切割線。換言之，每一導電體110的側壁110b暴露於外。
請參考圖3，於其他實施例中，封裝膠體130覆蓋每一導電體110的這些側壁110b，意即每一導電體110的側壁110b未暴露於外。換言之，導電體110除了被暴露的上表面110a外，其餘的部分完全包覆於封裝膠體130內。封裝膠體130的側壁130b透過單體化製程的切割與遮蔽層140的邊緣對齊。基本上，封裝結構30是依據圖1B’(而不是圖1B)的製作方法所形成，且切割製程雖是沿著切割線的方向來進行，但並沒有切穿封裝體110。
在本實施例之晶片封裝體的結構中，遮蔽層與導電體配置於基板上的作用可視為一電磁干擾屏蔽，用以保護晶片封裝體免於周圍輻射源的電磁干擾輻射。
此外，當遮蔽層形成於整個陣列基板與封裝膠體上且 於單體化製程之前，不需要半切割製程，可增加製程裕度與可靠度。
綜上所述，由於遮蔽層與導電體可有效地遮蔽外界電磁干擾輻射，因此可提高本發明之晶片封裝體的電磁干擾屏蔽的效能。本發明之晶片封裝體的製作方法，是於封裝結構內設立一接地路徑，而不是利用一額外的金屬板來作為接地平面。因此，這樣的設計適合具有高頻裝置的封裝，特別是一射頻裝置。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10、20‧‧‧晶片封裝體
30‧‧‧封裝結構
100‧‧‧陣列基板
102‧‧‧基板單元
102a‧‧‧上表面
103‧‧‧晶片貼附區域
104‧‧‧接點
106‧‧‧凸塊
108‧‧‧接地孔
110‧‧‧導電體
110a‧‧‧上表面
110b‧‧‧側壁
120‧‧‧晶片
130‧‧‧封裝膠體
130b‧‧‧側壁
140‧‧‧遮蔽層
d‧‧‧間隔距離
圖1A至圖1G繪示本發明之一實施例之一種晶片封裝體的製作方法。
圖2為本發明之一實施例之一種晶片封裝體的剖面示意圖。
圖3為本發明之另一實施例之一種晶片封裝體的剖面示意圖。
20‧‧‧晶片封裝體
100‧‧‧陣列基板
102‧‧‧基板單元
106‧‧‧凸塊
108‧‧‧接地孔
110‧‧‧導電體
110a‧‧‧上表面
110b‧‧‧側壁
120‧‧‧晶片
130‧‧‧封裝膠體
140‧‧‧遮蔽層

Claims (14)

  1. 一種晶片封裝體，包括：一積層基板，具有一接地孔；至少一晶片，配置於該積層基板上；多個導電體，配置於該積層基板上且環繞該晶片；一封裝膠體，包覆該晶片、部分該積層基板與該些導電體；以及一遮蔽層，配置於該封裝膠體上，且覆蓋該封裝膠體與至少部分地覆蓋每一該導電體暴露於該封裝膠體的一上表面，該遮蔽層透過該多個導電體電性連接至該積層基板的該接地孔；其中至少暴露每一該導電體的一側壁，且該側壁與該遮蔽層的邊緣對齊。
  2. 如申請專利範圍第1項所述之晶片封裝體，其中該封裝膠體覆蓋該些導電體的多個側壁，且該封裝膠體的邊緣與該遮蔽層的邊緣對齊。
  3. 如申請專利範圍第1項所述之晶片封裝體，其中該晶片透過多個排列於該晶片底部的凸塊電性連接至該積層基板的多個接點。
  4. 如申請專利範圍第1項所述之晶片封裝體，其中該些導電體環繞該晶片配置且呈環狀排列，且該晶片與該些導電體相互分離。
  5. 如申請專利範圍第1項所述之晶片封裝體，其中該晶片為一射頻晶片。
  6. 如申請專利範圍第1項所述之晶片封裝體，其中該導電體是由一焊料所製成，且該導電體為一焊料塊。
  7. 如申請專利範圍第1項所述之晶片封裝體，其中該導電體為一印刷電路板的一部分。
  8. 如申請專利範圍第1項所述之晶片封裝體，其中該導電體為一導線架的一部分。
  9. 如申請專利範圍第1項所述之晶片封裝體，其中該遮蔽層的材料為一金屬材料。
  10. 一種晶片封裝體的製作方法，包括：提供一陣列基板，該陣列基板具有多個基板單元，其中每一該基板單元是由多條切割線所定義，且每一該基板單元上具有一晶片貼附區域；形成多個導電體於每一該基板單元上，且該些導電體環繞該晶片貼附區域配置，其中該些導電體排列於該陣列基板的該些切割線上；配置至少一晶片於每一該基板單元的該晶片貼附區域上，其中該晶片電性連接至該基板單元，且該晶片與該些導電體相互分離；形成一封裝膠體於該陣列基板上，以包覆該晶片、部分該些基板單元與該些導電體；進行一標記製程以移除部分該封裝膠體至暴露出每一該導電體的一上表面；形成一遮蔽層於該封裝膠體上，以覆蓋該封裝膠體與每一該導電體被暴露出的該上表面；以及 進行一單體化製程，沿著該些切割線切穿該些導電體，以形成多個晶片封裝體。
  11. 如申請專利範圍第10項所述之晶片封裝體的製作方法，其中該些導電體的材料包括一金屬材料，且該些導電體的形成方式包括噴塗法、濺鍍法或電鍍法。
  12. 如申請專利範圍第10項所述之晶片封裝體的製作方法，其中該些導電體的材料包括一焊料，且該些導電體的形成方式包括噴塗法或印刷法。
  13. 如申請專利範圍第10項所述之晶片封裝體的製作方法，其中該標記製程包括一雷射挖空製程或一雷射鑽孔製程。
  14. 如申請專利範圍第10項所述之晶片封裝體的製作方法，其中該晶片透過覆晶接合而電性連接至該基板單元。
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