TWI411086B - 晶片封裝結構及其製作方法 - Google Patents

晶片封裝結構及其製作方法 Download PDF

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TWI411086B
TWI411086B TW098128058A TW98128058A TWI411086B TW I411086 B TWI411086 B TW I411086B TW 098128058 A TW098128058 A TW 098128058A TW 98128058 A TW98128058 A TW 98128058A TW I411086 B TWI411086 B TW I411086B
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substrate
structures
chip package
package structure
encapsulant
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TW201017857A (en
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Dongkyun Ko
Jung Lee
Jaesun An
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Advanced Semiconductor Eng
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Description

晶片封裝結構及其製作方法
本發明是有關於一種半導體裝置，且特別是有關於一種晶片封裝。
電磁干擾(electro-magnetic interference)對於大多數的電子產品或系統而言是一嚴肅且富有挑戰性的問題。由於電磁干擾常中斷、阻礙、降低或限制電子裝置或整體電路系統的效能表現，因此需要有效的電磁干擾屏蔽，以確保電子裝置或系統的效率與安全操作。
電磁干擾屏蔽的效能對於小尺寸、高密度的封裝體或應用於高頻率的敏感電子儀器非常重要。一般而言，大都是藉由增加金屬板與/或導電性的墊圈來提升電磁干擾屏蔽的效能，但此方式會提高製造成本。
本發明提供一種晶片封裝結構的製作方法，可提供較佳的設計靈活性。
發明提供一種具有提升電磁干擾屏蔽效能的晶片封裝結構。
本發明提出一種晶片封裝結構，其包括一基板、至少一晶片配置於基板上、一封裝膠體以及一具有多個導電連接結構的遮蔽層。配置於基板上的導電連接結構排列於封 裝膠體內且環繞晶片配置。遮蔽層配置於封裝膠體上，以覆蓋封裝膠體的上表面。遮蔽層透過導電連接結構電性連接至基板。
在本發明之一實施例中，上述之導電連接結構可為間柱(stud)或鍍通孔結構(plated via structure)，暴露出封裝膠體的側壁或不暴露出封裝膠體的側壁。
在本發明之一實施例中，上述之晶片透過多個凸塊與晶片封裝結構的積層基板電性連接。
在本發明之一實施例中，上述之封裝膠體的側壁為傾斜面。
本發明提出一種晶片封裝結構的製作方法。首先，至少一晶片配置於一陣列基板的一基板單元上，且晶片電性連接至基板單元。接著，形成一封裝膠體於陣列基板上，以覆蓋晶片與部分基板單元。接著，進行一標記製程以移除部分封裝膠體至暴露出每一基板單元的一上表面，而形成多個通孔。之後，形成一遮蔽層於封裝膠體上以覆蓋封裝膠體，同時形成多個導電連接結構於通孔內，以覆蓋每一基板單元被暴露出的上表面。進行一單體化製程，以形成多個晶片封裝。
在本發明之一實施例中，上述之導電連接結構可排列於陣列基板的切割線上與每一基板單元的多條邊界線上，因此單體化製程時會切穿導電連接結構與陣列基板。當然，導電連接結構亦可排列環繞每一基板單元的邊界線且與邊界線保持一間隔距離，因此單體化製程時不會切穿導 電連接結構。
在本發明之一實施例中，上述之遮蔽層與導電連接結構的形成方式是由一金屬材料且利用包括噴塗法(spraying process)、濺鍍法(sputtering process)或電鍍法(plating process)所形成。
在本發明之一實施例中，可依據完全填滿或部份地填充通孔，於形成遮蔽層的同時亦形成多個間柱或多個鍍通孔結構。
在本發明之一實施例中，上述之標記製程包括一雷射挖空製程(laser digging process)或一雷射鑽孔製程(laser drilling process)。
基於上述，遮蔽層與間柱配置於基板上的作用可視為晶片封裝結構的電磁干擾屏蔽。在本發明之中，透過具有彈性且多種設計型態的遮蔽層與間柱，可改善製程的空間。
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
本發明所述之晶片封裝結構的製作方法可用來製作多種封裝結構，其中以製作堆疊式封裝體、多層封裝體或具有高頻率裝置的封裝體(包括具有射頻裝置的封裝體)最為適合。此外，本發明之晶片封裝結構的製作方法與利用積層基板的製作方法或陣列基板的製作方法的封裝製程相互符合。
圖1A至圖1F’繪示本發明之一實施例之一種晶片封裝結構的製作方法的示意圖。在此必須說明的是，為了方便說明起見，圖1D’與圖1D”繪示立體示意圖，圖1A至圖1D、圖1E至圖1F與圖1E’至圖1F’繪示剖面示意圖。
請先參考圖1A，提供一陣列基板100。陣列基板100具有多個基板單元102(是由後續繪示為虛線的切割線所定義)，其中每一基板單元102上包括多個接點104。這些接點104的作用如同覆晶接合技術中的凸塊焊墊。陣列基板100可為一積層基板，其例如是一印刷電路板(Printed Circuit Board,PCB)。
接著，請參考圖1B，至少一晶片120配置於每一基板單元102的上表面102a上。雖然在此是提供晶片120配置於每一基板單元102的上表面102a上，但其他實施例中，亦可以是提供多個表面黏著型元件貼附於每一基板單元102的上表面102a上，此仍屬於本發明可採用的技術方案，不脫離本發明所欲保護的範圍。晶片120透過多個凸塊106電性連接至基板單元102的這些接點104，其中這些凸塊106介於晶片120與這些接點104之間。雖然在此是以覆晶接合技術作為說明，但於其他實施例中，亦包括利用打線接合技術來電性連接晶片120與這些接點104，仍屬於本發明可採用的技術方案，不脫離本發明所欲保護的範圍。較佳地，晶片120配置於基板單元102的中心部。
接著，請參考圖1C，透過一封膠製程而形成一封裝膠體130於陣列基板100上，以包覆晶片120、這些接點 104、這些凸塊106與至少一部分的基板單元102。封膠製程例如為一陣列封膠製程(over-molding process)。封裝膠體130的材料例如是環氧樹脂(epoxy resins)或矽氧樹脂(silicon resins)。
接著，請參考圖1D，進行一標記製程以移除部分封裝膠體130至暴露出基板單元102的上表面102a，而形成多個通孔135。這些通孔135環繞晶片120排列。較佳地，這些通孔135排列於晶片120與每一基板單元102的邊界或周圍之間。圖1D’繪示為圖1D之結構的立體示意圖。請同時參考圖1D與圖1D'，這些個別獨立的通孔135排列於基板單元102之邊界線(虛線)上。在本實施例中，後續之切割製程會沿著這些切割線(繪示為虛線)而切穿這些通孔135。標記製程例如是一雷射挖空製程或一雷射鑽孔製程。此外，藉由上述之雷射製程所形成的這些通孔135具有高準確度的直徑與可控制的漸縮部(taper)。較佳地，這些通孔135的漸縮部具有一傾斜角θ(介於通孔135的側壁135a與基板單元102的上表面102a之間)，且此傾斜角θ的範圍介於60度至90度之間。以這些通孔135c環繞排列於每一基板單元102的邊界為例，標記製程可藉由鑽多個彼此相互分離的孔而移除部份的封裝膠體130，其中這些孔於封裝膠體130內呈環狀排列，且位於每一基板單元102的邊界線上。
於其他實施例中，這些通孔135亦可排列靠近且位於基板單元102的這些邊界線(虛線)內，但不位於基板單 元102的這些邊界線上，請參考圖1D”。這些通孔135可環繞晶片120配置且靠近基板單元102的這些邊界線。舉例而言，這些通孔135可排列成環形框狀圖案(ring-shaped pattern)且與基板單元102的邊界線相距一小間隔距離d，且間隔距離d可依據產品的需求而自由調整。此外，後續的切割製程雖然會沿著這些切割線但不會切穿這些通孔135。一般而言，這些通孔135的尺寸或形狀可依照屏蔽的需要、封裝體電性的特性，或甚至是依據製程的參數而自由調整。
接者，請參考圖1E，形成一遮蔽層140於封裝膠體130上，以覆蓋封裝膠體130的上表面130a與基板單元102的上表面102a(意指基板單元102被這些通孔135所暴露出的上表面102a)，以及填滿這些通孔135。遮蔽層140的形成方式是利用噴塗法、電鍍法或濺鍍法，使一金屬材料(未繪示)覆蓋封裝膠體130及填滿這些通孔135。遮蔽層140的材料例如是鋁、銅、鉻、金、銀、鎳、焊料或上述材料之化合物。間柱142可於形成遮蔽層140的過程經由填滿這些通孔135而形成。
最後，請參考圖1F，進行一單體化製程，以形成多個獨立的晶片封裝結構10。單體化製程例如是一刀片切割製程。請同時參考圖1E與圖1F，單體化製程切穿這些間柱142與陣列基板100，以形成多個個別獨立且分別具有多個半間柱(semi-studs)142a的晶片封裝結構10。
當然，於其他實施例中，請參考圖1E'，遮蔽層140 亦可形成於封裝膠體130上，以覆蓋封裝膠體130的上表面130a且共形地(conformally)覆蓋這些通孔135的側壁135a，並暴露出基板單元102的上表面102a，而形成多個鍍通孔結構(plated via structure)144。在此實施例中，遮蔽層140的形成方式是利用噴塗法、電鍍法或濺鍍法，使一金屬材料(未繪示)覆蓋封裝膠體130而不填滿這些通孔135。依據通孔135的形狀與尺寸，鍍通孔結構144的形狀可為一杯狀或一倒置帽子形狀(inverted cap)。接著，請參考圖1F’，進行一單體化製程以切穿陣列基板100與這些鍍通孔結構144，而形成多個個別獨立且分別具有多個半鍍通孔結構(semi-plated vias structure)144a的晶片封裝結構10。單體化製程例如是一刀片切割製程。
圖2為本發明之一實施例之一種晶片封裝結構的剖面示意圖。請參考圖2，在本實施例中，晶片封裝結構20包括一基板單元102、多個接點104、多個凸塊106、至少一晶片120、一封裝膠體130與一遮蔽層140。基板單元102可為一積層基板，其例如是一兩層或一四層積層的印刷電路板基板。晶片120可為一半導體晶片，其例如是一射頻(RF)晶片。遮蔽層140的材質可為銅、鉻、金、銀、鎳、鋁或上述材料之合金，甚至是一焊料。晶片120透過接點(凸塊焊墊)104與凸塊106電性連接至基板單元102。封裝膠體130包覆部分基板單元102、凸塊106與晶片120。遮蔽層140包括多個半間柱142a。在此所述之半間柱142a是指圖1F所繪示之切割後的間柱，但於上下文中可將其 視為間柱。這些間柱142的形狀或結構與這些通孔135的位置排列有關，如這些間柱142是由填滿這些通孔135所形成，請參考圖1E。請再參考圖2，遮蔽層140配置於封裝膠體130上，以覆蓋封裝膠體130的上表面130a，其中半間柱142a覆蓋基板單元102被暴露出的上表面102a。單體化製程會切穿這些間柱142與封裝膠體130(切穿這些切割線)，請參考圖1F，部分封裝膠體130與這些半間柱142a暴露於晶片封裝結構20的側表面20b。遮蔽層140透過這些半間柱142a與至少一基板單元102的接地孔108而電性連接至基板單元102，而遮蔽層140透過這些半間柱142a與接地孔108而接地。因此，可利用基板表面的金屬線路或走線作為一接地平面，使本實施例之遮蔽層140可藉由基板的接地平面而接地於封裝結構內。
圖3為本發明之另一實施例之一種晶片封裝結構的剖面示意圖。請參考圖3，遮蔽層140配置於封裝膠體130上且覆蓋封裝膠體130的上表面130a。遮蔽層140亦包括多個間柱142，其中這些間柱142配置於基板單元102上且位於封裝膠體130內，並覆蓋基板單元102被暴露出的上表面102a。基本上，晶片封裝結構30是依據圖1D”(而不是圖1D)的製作方法所形成，且切割製程雖是沿著切割線的方向來進行，但並沒有切穿這些間柱142。事實上，這些間柱142可視為多個填充的通孔結構，且圖3之這些間柱142是環繞晶片120排列且位於晶片120與基板單元102的這些邊界線之間。因此，暴露出封裝膠體130的這 些側壁130b，但這些間柱142未暴露於晶片封裝結構30的側表面外。
圖4為本發明之另一實施例之一種晶片封裝結構的剖面示意圖。請參考圖4，在本實施例中，晶片封裝結構40是依據圖1D、圖1E’與圖1F’的製作方法所形成，且遮蔽層140’包括多個半鍍通孔結構144a。在此所述之半鍍通孔結構144a是指圖1F’所繪示之切割後的鍍通孔結構，但於上下文中可將其視為鍍通孔結構。這些半鍍通孔結構144a的形狀或結構與這些通孔135的位置排列有關，如這些半鍍通孔結構144形成作為這些通孔135的共形塗層(conformal coatings)，請參考圖1E'。請再參考圖4，遮蔽層140’覆蓋封裝膠體130的上表面130a，且半鍍通孔結構144a覆蓋基板單元102被暴露出的上表面102a。單體化製程會切穿這些這些鍍通孔結構144與封裝膠體130(切穿這些切割線)，請參考圖1F’，部分封裝膠體130與這些半鍍通孔結構144a暴露於晶片封裝結構40的側表面40b外。遮蔽層140’透過這些半鍍通孔結構144a與至少一基板單元102的接地孔108而電性連接至基板單元102，而遮蔽層140’透過這些半鍍通孔結構144a與接地孔108而接地。
圖5為本發明之另一實施例之一種晶片封裝結構的剖面示意圖。請參考圖5，在本實施例中，晶片封裝結構50是依據圖1D”與圖1E’的製作方法所形成，且遮蔽層140’包括多個鍍通孔結構144。當切割製程沒切穿排列鄰近於 切割線的這些鍍通孔結構144時，暴露出封裝膠體130的側壁130b，但鍍通孔結構144未暴露於晶片封裝結構50的側表面外。
簡言之，間柱(半間柱或未切割的間柱)或鍍通孔結構(切割的鍍通孔結構或未切割的鍍通孔結構)可視為上遮蔽層之金屬連接結構。遮蔽層是透過間柱(半間柱或未切割的間柱)或鍍通孔結構(切割的鍍通孔結構或未切割的鍍通孔結構)而物理性與/或電性連接至下方的基板。
圖1A至圖1F’之晶片封裝結構的製作方法在符合本發明的情況下，可以更進一步地被修改與描述於以下之具體實施例中。
接著圖1A至圖1C的步驟後，請參考圖6A，進行一標記製程以移除部分封裝膠體630至暴露出基板單元602的上表面602a，而形成多個溝渠(trench)635。這些溝渠635環繞晶片620排列。較佳地，每一溝渠635為一環狀溝渠且排列於晶片620與每一基板單元602的邊界或周圍之間。圖6A’為圖6A之結構的立體示意圖。請參考圖6A與圖6A’，這些個別獨立的溝渠635排列於基板單元602之邊界線(虛線)上。在某方面而言，藉由標記製程所形成之這些溝渠635可視為一格子(grid)或格子狀(latticed)的圖案。在本實施例中，後續之切割製程會沿著這些切割線(繪示為虛線)而切穿這些溝渠635。標記製程例如是一雷射挖空製程或一雷射鑽孔製程。此外，藉由上述之雷射製程所形成的這些溝渠635具有高準確度的直徑與可控 制的漸縮部(taper)。較佳地，這些溝渠635的漸縮部具有一傾斜角θ(介於側壁635a與基板表面602a之間)，且此傾斜角θ的範圍介於60度至90度之間。以這些溝渠635環繞排列於每一基板單元602的邊界為例，標記製程可藉由鑽多個環狀溝渠而移除部份的封裝膠體630，其中這些環狀溝渠位於封裝膠體630內，且位於每一基板單元602的邊界線上。
於其他實施例中，這些溝渠635亦可排列靠近於基板602的這些邊界線(虛線)內，但不位於基板602的這些邊界線上，請參考圖6A”。這些溝渠635配置鄰近基板602的這些邊界線。此外，後續的切割製程雖然會沿著這些切割線但不會切穿這些溝渠635。一般而言，這些溝渠635的尺寸或形狀可依照屏蔽的需要、封裝體電性的特性，或甚至是依據製程的參數而自由調整。
類似圖1E的步驟，一遮蔽層640形成於封裝膠體630上，以覆蓋封裝膠體630的上表面630a且填滿這些溝渠635，並覆蓋基板602被暴露出的上表面602a(被這些溝渠635所暴露出之基板602的上表面602a)，而形成填充的環形結構642，請參考圖6B。於其他實施例中，類似圖1E’的步驟，遮蔽層640’亦可形成於封裝膠體630上，以覆蓋封裝膠體630的上表面630a以及共形地覆蓋這些溝渠635的側壁635a與基板602被暴露出的上表面602a，而形成多個中空環狀結構644，請參考圖6B’。
最後，接續著圖1F或圖1F’的步驟，進行單體化製程， 以形成多個獨立的晶片封裝結構。
圖7為本發明之另一實施例之一種晶片封裝結構的立體示意圖。請參考圖7，在本實施例中，晶片封裝結構70是依據圖1A至圖1C、圖6A與圖6B’的製作方法所形成，且遮蔽層640’包括多個切割的中空環結構644a。請參考圖6B’與圖7，遮蔽層640’覆蓋封裝膠體630的上表面630a，同時，切割的(或半)中空環狀結構644a覆蓋封裝膠體630的側壁635a。當進行切割製程切穿中空環結構644(切穿切割線)時，只有切割的環狀結構644a被暴露於晶片封裝結構70的側表面外。遮蔽層640’透過切割的中空環狀結構644a與至少一基板602的接地孔608而電性連接至基板602，而遮蔽層640’透過這些半鍍環狀結構644a與接地孔608而接地。
圖8為本發明之另一實施例之一種晶片封裝結構的立體示意圖。請參考圖8，在本實施例中，晶片封裝結構80是依據圖1A至圖1C、圖6A”與圖6B的製作方法所形成。遮蔽層640覆蓋封裝膠體630的上表面630a且包括多個填充的環狀結構642。當切割製程沒切穿排列鄰近於切割線的這些填充的環狀結構642時，暴露出封裝膠體630的側壁630b，但填充的環狀結構642未暴露於晶片封裝結構80的側表面外。
簡言之，實心的環狀結構(切割的環狀結構或未切割的環狀結構)或中空環狀結構(切割的中空環狀結構或未切割的中空環狀結構)可視為上遮蔽層的金屬連接結構。 遮蔽層是透過實心的環狀結構(切割的環狀結構或未切割的環狀結構)或中空環狀結構(切割的中空環狀結構或未切割的中空環狀結構)而物理性與/或電性連接至下方的基板。
在本實施例之晶片封裝結構中，遮蔽層與導電連接結構配置於基板上的作用可視為一電磁干擾屏蔽，用以保護晶片封裝結構免於周圍輻射源的電磁干擾輻射。
在本發明中，由於通孔的形狀與位置可藉由標記製程而精準地控制，因此晶片封裝結構的電磁干擾屏蔽設計可依照產品的需要而自由調整。此外，當遮蔽層包括排列於封裝膠體內的導電連接結構時，可提高電磁干擾屏蔽的效能。
綜上所述，由於遮蔽層與導電連接結構可有效地遮蔽外界電磁干擾輻射，因此可提高本發明之晶片封裝結構的電磁干擾屏蔽的效能。此外，本發明之晶片封裝結構的製作方法，是於封裝結構內設立一接地路徑，而不是利用一額外的金屬板來作為接地平面。因此，這樣的設計適合具有高頻裝置的封裝，特別是一射頻裝置。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10、20、30、40、50、70、80‧‧‧晶片封裝結構
20b、40b‧‧‧側表面
100、600‧‧‧陣列基板
102、602‧‧‧基板單元
102a、602a‧‧‧上表面
104‧‧‧接點
106‧‧‧凸塊
108‧‧‧接地孔
120、620‧‧‧晶片
130、630‧‧‧封裝膠體
130a、630a‧‧‧上表面
130b、630b‧‧‧側壁
135‧‧‧通孔
135a‧‧‧側壁
140、140’、640、640’‧‧‧遮蔽層
142‧‧‧間柱
142a‧‧‧半間柱
144‧‧‧鍍通孔結構
144a‧‧‧半鍍通孔結構
635‧‧‧溝渠
635a‧‧‧側壁
642‧‧‧環狀填充結構
644‧‧‧中空環狀結構
644a‧‧‧半中空環狀結構
θ‧‧‧傾斜角
d‧‧‧間隔距離
圖1A至圖1F’繪示本發明之一實施例之一種晶片封裝結構的製作方法的示意圖。
圖2為本發明之一實施例之一種晶片封裝結構的剖面示意圖。
圖3為本發明之另一實施例之一種晶片封裝結構的剖面示意圖。
圖4為本發明之另一實施例之一種晶片封裝結構的剖面示意圖。
圖5為本發明之另一實施例之一種晶片封裝結構的剖面示意圖。
圖6A至圖6B’繪示本發明之一較佳實施例之一種晶片封裝結構的製作方法之部分步驟的示意圖。
圖7為本發明之另一實施例之一種晶片封裝結構的立體示意圖。
圖8為本發明之另一實施例之一種晶片封裝結構的立體示意圖。
20‧‧‧晶片封裝結構
20b‧‧‧側表面
102‧‧‧基板單元
102a‧‧‧上表面
104‧‧‧接點
106‧‧‧凸塊
108‧‧‧接地孔
120‧‧‧晶片
130‧‧‧封裝膠體
130a‧‧‧上表面
140‧‧‧遮蔽層
142a‧‧‧半間柱

Claims (21)

  1. 一種晶片封裝結構，包括：一基板單元，具有一上表面；至少一晶片，配置於該基板單元上且電性連接至該基板單元；一封裝膠體，配置於該基板單元的該上表面上，且具有一上表面與一側壁，其中該封裝膠體至少包覆該晶片與部分該基板單元的該上表面，且該側壁與該基板的該上表面之間形成一傾斜角；一遮蔽層，配置於該封裝膠體的該上表面上；以及多個導電連接結構，配置於該封裝膠體的該側壁上，其中該些導電連接結構以環狀方式環繞該晶片配置於該基板單元的該上表面，且該晶片與該些導電連接結構相互分離；其中，該遮蔽層透過該些導電連接結構電性連接至該基板單元。
  2. 如申請專利範圍第1項所述之晶片封裝結構，其中該些導電連接結構為多個彼此相互分離的金屬間柱，且暴露於該封裝膠體的該側壁外。
  3. 如申請專利範圍第1項所述之晶片封裝結構，其中該些導電連接結構為多個彼此相互分離的金屬間柱，位於該封裝膠體內。
  4. 如申請專利範圍第1項所述之晶片封裝結構，其中該些導電連接結構為多個彼此相互分離的鍍通孔結構，且 暴露於該封裝膠體的該側壁外。
  5. 如申請專利範圍第1項所述之晶片封裝結構，其中該些導電連接結構為多個彼此相互分離的鍍通孔結構，位於該封裝膠體內。
  6. 如申請專利範圍第1項所述之晶片封裝結構，其中該些導電連接結構為多個實心的環狀結構且位於該封裝膠體內。
  7. 如申請專利範圍第1項所述之晶片封裝結構，其中該些導電連接結構為多個中空環狀結構且位於該封裝膠體內。
  8. 如申請專利範圍第1項所述之晶片封裝結構，其中該遮蔽層透過該些導電連接結構與該基板單元的至少一接地孔電性連接。
  9. 一種晶片封裝結構的製作方法，包括：提供一陣列基板，該陣列基板具有多個基板單元，其中每一該基板單元是由多條切割線所定義；配置至少一晶片於每一該基板單元上，其中該晶片電性連接至該基板單元；形成一封裝膠體於該陣列基板上，以包覆該晶片；進行一標記製程以移除部分該封裝膠體至暴露出每一該基板單元的一上表面，以形成多個通孔或多個溝渠於該封裝膠體內；形成一遮蔽層於該封裝膠體上以覆蓋該封裝膠體，同時形成多個導電連接結構，以覆蓋該些通孔或該些溝渠且 覆蓋每一該基板單元被暴露出的該上表面；以及進行一單體化製程，以形成多個晶片封裝結構。
  10. 如申請專利範圍第9項所述之晶片封裝結構的製作方法，其中該些導電連接結構為填滿該些通孔所形成的多個間柱。
  11. 如申請專利範圍第10項所述之晶片封裝結構的製作方法，其中該些間柱排列於該陣列基板的該些切割線上與每一該基板單元的多條邊界線上，且該單體化製程切穿該些間柱與該陣列基板。
  12. 如申請專利範圍第10項所述之晶片封裝結構的製作方法，其中該些間柱配置於每一該基板單元的該些邊界線與該晶片之間，且該單體化製程切穿該陣列基板但未切穿該些間柱。
  13. 如申請專利範圍第9項所述之晶片封裝結構的製作方法，其中該些導電連接結構為部分地填充該些通孔所形成的多個鍍通孔結構。
  14. 如申請專利範圍第13項所述之晶片封裝結構的製作方法，其中該些鍍通孔結構排列於該陣列基板的該些切割線上與每一該基板單元的多條邊界線上，且該單體化製程切穿該些鍍通孔結構與該陣列基板。
  15. 如申請專利範圍第13項所述之晶片封裝結構的製作方法，其中該些鍍通孔結構配置於該晶片與每一該基板單元的該些邊界線之間，且該單體化製程切穿該陣列基板但未切穿該些鍍通孔結構。
  16. 如申請專利範圍第9項所述之晶片封裝結構的製作方法，其中該些導電連接結構為填滿該些溝渠所形成之多個環狀結構。
  17. 如申請專利範圍第16項所述之晶片封裝結構的製作方法，其中該些環狀結構排列於該陣列基板的該些切割線上與每一該基板單元的多條邊界線上，且該單體化製程切穿該些環狀結構與該陣列基板。
  18. 如申請專利範圍第16項所述之晶片封裝結構的製作方法，其中該些環狀結構配置於該晶片與每一該基板單元的該些邊界線之間，且該單體化製程切穿該陣列基板但未切穿該些環狀結構。
  19. 如申請專利範圍第9項所述之晶片封裝結構的製作方法，其中該些導電連接結構為部分地填充該些溝渠所形成的多個中空環狀結構。
  20. 如申請專利範圍第19項所述之晶片封裝結構的製作方法，其中該些中空環狀結構排列於該陣列基板的該些切割線上與每一該基板單元的多條邊界線上，且該單體化製程切穿該些中空環狀結構與該陣列基板。
  21. 如申請專利範圍第19項所述之晶片封裝結構的製作方法，其中該些中空環狀結構配置於該晶片與每一該基板單元的該些邊界線之間，且該單體化製程切穿該陣列基板但未切穿該些中空環狀結構。
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US20100110656A1 (en) 2010-05-06
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US20100109132A1 (en) 2010-05-06
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US8592958B2 (en) 2013-11-26
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