TWI491018B - 半導體封裝件及其製造方法 - Google Patents

半導體封裝件及其製造方法 Download PDF

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TWI491018B
TWI491018B TW102126548A TW102126548A TWI491018B TW I491018 B TWI491018 B TW I491018B TW 102126548 A TW102126548 A TW 102126548A TW 102126548 A TW102126548 A TW 102126548A TW I491018 B TWI491018 B TW I491018B
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substrate
package
layer
wafer
semiconductor package
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TW102126548A
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TW201407745A (zh
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I Chia Lin
Sheng Jian Jou
Han Chee Yen
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Advanced Semiconductor Eng
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Description

半導體封裝件及其製造方法
本發明是有關於一種半導體封裝件及其製造方法,且特別是有關於一種具有天線之半導體封裝件及其製造方法。
無線通訊裝置例如是手機(cell phone),需要天線以傳送及接收訊號。傳統上,無線通訊裝置包括天線及通訊模組(例如是具有無線射頻(RF)通訊能力之一半導體封裝件),其各設於電路板的不同部位。在傳統方式中,天線及通訊模組係分別製造且設置在電路板後進行電性連接,因此導致高製造成本且難以完成輕薄短小的設計。此外,天線與通訊模組之間的RF訊號傳輸路徑較長,天線與通訊模組之間的訊號傳輸品質因而降低。
根據本發明之一實施例,提出一種半導體封裝件。半導體封裝件包括一第一基板、一中介層、一第一晶片、一第二基板、一第二晶片、一第三晶片、一感應器、一封裝體及一金屬層。第一基板包含一接地層。中介層設於第一基板的一上表面且 具有至少一開口。第一晶片設於至少一開口並耦接於第一基板。第二基板耦接於中介層,且設於第一基板上方且具有一面積,第二基板之面積小於第一基板之一面積。第二晶片設於第二基板之一下表面。第三晶片內埋於第二基板。感應器設於第二基板的一上表面,其中感應器電性連接於第二基板及第三晶片。封裝體包覆第一基板之數個部分、中介層、第二基板、第一晶片與第二晶片,封裝體具有一側面及一上表面。金屬層設於封裝體的側面與上表面,其中金屬層電性連接第一基板且具有數個孔覆蓋在感應器上。
根據本發明之另一實施例,提出一種半導體封裝件。半導體封裝件包括一第一基板、一中介層、一第一晶片、一第二基板、一第二晶片、一感應器、一封裝體及一金屬層。第一基板包含一接地層。中介層設於第一基板的一上表面。第一晶片設於由中介層所定義之一空間且耦接於第一基板。第二基板設於第一基板上方且耦接於中介層。第二晶片設於第二基板之一下表面。感應器設於第二基板的一上表面且耦接於第二晶片。封裝體包覆第一基板之數個部分、中介層、第二基板、第一晶片與第二晶片,封裝體具有一側面及一上表面。金屬層設於封裝體的側面與上表面,其中金屬層電性連接第一基板且具有數個孔覆蓋在感應器上。
根據本發明之另一實施例,提出一種半導體封裝件之製造方法。製造方法包括以下步驟。提供一第一基板,第一基 板包含一接地件;提供一第二基板,第二基板包含設於其上之一半導體晶片;設置一中介層基板於第一基板與第二基板之間,其中中介層基板電性連接於第一基板及第二基板;形成一封裝體包覆第二基板之數個部分、半導體晶片與中介層基板;形成一第一切割道經過封裝體,使封裝體形成一側面;形成一第一天線層於側面及封裝體之一上表面,其中第一天線層電性連接於第一基板之接地件;以及,形成一第二切割道經過第一基板。
為了對本發明之上述及其他方面有更佳的瞭解,下文特舉較佳實施例,並配合所附圖式,作詳細說明如下:
100、200、300、400、500、600、700‧‧‧半導體封裝件
110‧‧‧第一基板
110b‧‧‧下表面
110u、150u、160u、385u‧‧‧上表面
110s、111s、130s、150s、160s、270s、385s‧‧‧側面
111‧‧‧接地件
112‧‧‧半導體晶片
113、142‧‧‧焊球
120‧‧‧中介層基板
122‧‧‧導電元件
123‧‧‧黏結物
130、390‧‧‧第二基板
131‧‧‧微帶線
132‧‧‧相位位移器
133‧‧‧圖案化導電層
134‧‧‧饋入網
135‧‧‧導電孔
136‧‧‧屏蔽層
140‧‧‧半導體晶片
141‧‧‧接合線
143‧‧‧被動元件
150‧‧‧封裝體
150s1‧‧‧第一側面
150s2‧‧‧第二側面
160、560、760‧‧‧第一天線層
160’‧‧‧天線材料
160a、760a‧‧‧開槽
161‧‧‧接地層
162‧‧‧幅射層
185‧‧‧載板
270‧‧‧導電架
271‧‧‧焊料
280‧‧‧接點
385、730‧‧‧介電層
390‧‧‧第二天線層
391‧‧‧子天線
720‧‧‧封模穿孔
T1‧‧‧切割道
T2‧‧‧第一切割道
T3‧‧‧第二切割道
第1A圖繪示依照本發明一實施例之半導體封裝件的剖視圖。
第1B圖繪示第1A圖之俯視圖。
第2圖繪示依照本發明另一實施例之半導體封裝件200的剖視圖。
第3A圖繪示依照本發明另一實施例之半導體封裝件300的剖視圖。
第3B圖繪示第3A圖之俯視圖。
第4圖繪示依照本發明另一實施例之半導體封裝件400的剖視圖。
第5圖繪示依照本發明另一實施例之半導體封裝件500的剖視圖。
第6圖繪示依照本發明另一實施例之半導體封裝件600的剖視圖。
第7圖繪示依照本發明另一實施例之半導體封裝件700的剖視圖。
第8A至8H圖繪示第1A圖半導體封裝件之製造過程圖。
第9A至9I圖繪示第2圖半導體封裝件之製造過程圖。
第10A至10C圖繪示第3A圖半導體封裝件之製造過程圖。
第11A至11F圖繪示第4圖半導體封裝件之製造過程圖。
第12A至12B圖繪示第5圖半導體封裝件之製造過程圖。
第13A至13D圖繪示第6圖半導體封裝件之製造過程圖。
請參照第1A圖,其繪示依照本發明一實施例之半導體封裝件100的剖視圖。半導體封裝件100包括一第一基板110、一中介層基板120、一第二基板130、數個半導體晶片140、一封裝體150及一第一天線層160。
第一基板110具有相對之一上表面110u與一下表面110b,且包括一接地件111。第一基板110例如是一多層有機基板或一陶瓷基板。此外,至少一半導體晶片112及至少一被動元件143更設於第一基板110的上表面110u且電性連接於第一基板110。例如,設於第一基板110的半導體晶片112可以是一基頻晶片(baseband chip)。
本例中,接地件111係一導電柱(conductive pillar),其從第一基板110的上表面110u延伸至第一基板110的下表面110b(即,接地件111貫穿第一基板110)。此外,接地件111可不貫穿第一基板110。接地件111可由導電材料製成,例如是銅。
中介層基板120設於第一基板110與第二基板130之間,讓半導體晶片140及被動元件143容置於第一基板110與第二基板130之間的空間。此外,中介層基板120可採用支撐第二基板130的一邊緣部及一中間部的方式配置,以降低第二基板130的任何翹曲。
中介層基板120包括數個導電元件122,其電性連接於第一基板110及第二基板130,使一訊號可透過中介層基板120傳輸於第一基板110與第二基板130之間。此外,一黏結物123可形成於第二基板130與中介層基板120之間的轉角,以免當第二基板130倒置時中介層基板120掉落。
第二基板130例如是多層有機基板或一陶瓷基板。第二基板130包括一微帶線131、一內埋之相位位移器132、一圖案化導電層133、一饋入網134及數個導電孔135。微帶線131設於第二基板130的表面且因封裝體150而與第一天線層160隔離。結果,一電流透過電磁感應產生於第一天線層160或微帶線131。
內埋相位位移器132內埋於第二基板130且透過導電孔135及圖案化導電層133電性連接於微帶線131與饋入網134。此外,相位位移器132透過導電孔135及圖案化導電層133電性連接饋入網134。相位位移器132,例如是二極體,可調整由第一天線層160發射或接收之一無線射頻(radio frequency)訊號的一相位。另一例中,內埋相位位移器132可以是一功率放大器,以調變無線射頻訊號的振幅。饋入網134可傳輸訊號從半導體晶片140至第一天線層160。
半導體晶片140設於第二基板130上且位於第一基板110與第二基板130之間。例如,設於第二基板130上之半導體晶片140可以是一高頻晶片。當數個半導體晶片140之一透過數個接合線(bond wire)141電性連接於第二基板130,此些半導體晶片140的一主動面面向第一基板110。當數個半導體晶片140之一透過一焊球(solder ball)142電性連接 於第二基板130,此些半導體晶片140的一主動面面向第二基板130。
本例中,封裝體150包覆第二基板130、半導體晶片140及中介層基板120,且具有一側面150s及一上表面150u。當封裝體150的側面150s及接地件111的側面111s於同一製程形成,封裝體150之側面150s實質上與接地件111之一側面111s齊平或共面。
封裝體150由包含一介電材料的材料製成,使一電場可產生於第一天線層160與微帶線131之間。一例中,封裝體150可包括酚醛基樹脂(Novolac-based resin)、環氧基樹脂(epoxy-based resin)、矽基樹脂(silicone-based resin)或其他適當之包覆劑。封裝體150亦可包括適當之填充劑,例如是粉狀之二氧化矽。可利用數種封裝技術形成封裝體150,例如是壓縮成型(compression molding)、液態封裝型(liquid encapsulation)、注射成型(injection molding)或轉注成型(transfer molding)。
第一天線層160形成於封裝體150的側面150s及上表面150u,且延伸至接地件111的側面111s而電性連接於接地件111。第一天線層160可減少來自於半導體封裝件100的電磁干擾(electromagnetic interference,EMI)且避免外源(external sources)的無線射頻干擾半導體封裝件100的操作。
第一天線層160可包括鋁、銅、鉻、錫、金、銀、鎳、不銹鋼或上述材料之組合所製成。第一天線層160可以是單層或多層材料。一例中,第一天線層160係三層結構,其內層係不銹鋼層、中間層係銅層,而外層係不銹鋼層。另一例中,第一天線層160係雙層結構,其內層係銅層,而其外層係不銹鋼層。
第一天線層160包括一接地層161及連接於接地層161之一幅射層162。接地層161形成於封裝體150的側面150s及接地件111的側面111s。輻射層162形成於封裝體150的上表面150u且具有數個開槽160a露出封裝體150之一部分。當第一天線層160受到一驅動頻率的驅動,開槽160a輻射產生電磁波。因此,開槽160a的外形、尺寸以及驅動頻率決定無線分佈型態(radiation distribution pattern)。
如第1A圖所示,無線射頻訊號可透過一傳輸路徑傳輸至半導體晶片140,傳輸路徑包含開槽160a、微帶線131、導電孔135、圖案化導電層133、相位位移器132及饋入網134。由於傳輸路徑縮短,本實施例之無線射頻訊號的失真因此降低。
請參照第1B圖,其繪示第1A圖之俯視圖。本例中,數個開槽160a排列成矩陣形。另一例中,數個開槽160a可排列成任意形狀且開槽160a的數量可以是單個。實務上,開槽160a的形式及數量視第一天線層160的阻抗匹配而定。
如第1B圖所示,因為第一基板110的側面110s及接地件111的側面111s於同一製程形成,接地件111的側面111s實質上與第一基板110的側面110s齊平或共面。此外,中介層基板120係封閉環形基板。另一例中,中介層基板120係開放環形基板。
請參照第2圖,其繪示依照本發明另一實施例之半導體封裝件200的剖視圖。半導體封裝件200包括一第一基板110、一中介層基板120、一第二基板130、數個半導體晶片140、一封裝體150、一第一天線層160、一導電架270及數個接點280。
第一基板110包括接地件111,其例如是一圖案化導電層,其中接地件111電性連接於對應之電性接點280。另一例中,接地件111可以是走線、焊料或導電柱。本例中,接地件111未從第一基板110之側面110s露出,但此非用以限制本發明實施例。由於第一基板110之側面110s與封裝體150之第一側面150s1於同一製程中形成,故第一基板110之側面110s與封裝體150之第一側面150s1實質上對齊或共面。
本例中,封裝體150包覆第二基板130、半導體晶片140及中介層基板120。封裝體150具有第二側面150s2及上表面150u,其中,由於封裝體150之第二側面150s2與導電架270之外側面270s於同一製程中形成,故封裝體150之第二側面150s2與導電架270之外側面270s實質上對齊或共面。
導電架270電性連接於接地件111,且從封裝體150之第一側面150s1露出,使第一天線層160可形成於露出之導電架270,且透過導電架270電性連接於接地件111。
請參照第3A圖,其繪示依照本發明另一實施例之半導體封裝件300的剖視圖。半導體封裝件300包括一第一基板110、一中介層基板120、一第二基板130、數個半導體晶片140、一封裝體150、一第一天線層160、一介電層385及一第二天線層390。
介電層385覆蓋第一天線層160之上表面160u及側面160s,即,介電層385覆蓋第一天線層160之接地層161及幅射層162。介電層385可以由例如是封裝體、介電材料(例如是環氧樹脂(epoxy))或預浸漬層(prepreg lamination)的材料形成。
第二天線層390形成於介電層385之上表面385u,且與第一天線層160隔離,即,第二天線層390未電性連接於接地件111。另一例中,第二天線層390係一縫隙耦合天線(aperture coupled antenna)。第二天線層390的區域對應第一天線層160之開槽160a,以縮短第二天線層390與第一天線層160之間的傳輸路徑。
請參照第3B圖,其繪示第3A圖之俯視圖。第二天線層390包括數個子天線391。本例中,子天線391彼此隔離,且排列成陣列狀,以增加天線增益(antenna gain)及頻寬(frequency band)。另一例中,視設計需求而定,子天線391可排列成不同形狀。
請參照第4圖,其繪示依照本發明另一實施例之半導體封裝件400的剖視圖。半導體封裝件400包括一第一基板110、一中介層基板120、一第二基板130、數個半導體晶片140、一封裝體150、一第一天線層160、一導電架270、數個電性接點280、一介電層385及一第二天線層390。
第一基板110包括一接地件111,其例如是一圖案化導電層,其中接地件111電性連接於對應之電性接點280。另一例中,接地件111可以是走線、焊料或導電柱。本例中,接地件111未從第一基板110之側面110s露出,但此非用以限制本發明實施例。
由於第一基板110之側面110s與封裝體150之第一側面150s1於同一製程中形成,故第一基板110之側面110s與封裝體150之第一側面150s1實質上對齊或共面。
封裝體150包覆第二基板130、數個半導體晶片140及中介層基板120,且具有一第二側面150s2及一上表面150u。由於封裝體150的 第二側面150s2及導電架270的側面270s於相同製程形成,故封裝體150之側面150s與導電架270的側面270s實質上齊平或共面。
第一基板110形成於封裝體150之第二側面150s2、上表面150u上及露出之導電架270。第一天線層160透過導電架270電性連接於接地件111,並提供電磁干擾防護功能。
導電架270電性連接於接地件111,且從封裝體150之第二側面150s2露出,使第一天線層160可形成於露出之導電架270,且透過導電架270電性連接於接地件111。
介電層385覆蓋第一天線層160之接地層161及輻射層162。第二天線層390設於介電層385上。
請參照第5圖,其繪示依照本發明另一實施例之半導體封裝件500的剖視圖。半導體封裝件500包括一第一基板110、一中介層基板120、一第二基板130、數個半導體晶片140、一封裝體150及一第一天線層560。
第二基板130具有一側面130s,其與封裝體150之側面150s實質上對齊或共面。第二基板130包括一微帶線131、一內埋之相位位移器132、一圖案化導電層133、一饋入網134、數個導電孔135及一屏蔽層136。圖案化導電層133透過饋入網134及導電孔135接收由半導體晶片140傳輸之一高頻訊號,然後轉換此高頻訊號成一基頻訊號(base frequency signal)。此基頻訊號透過導電孔135傳輸至微帶線131,使輻射層162藉由電磁感應輻射產生一無線訊號。此外,內埋之相位位移器132可改變無線訊號之一幅射功率型態(radiation power pattern)。
屏蔽層136從第二基板130的側面130s露出,以連接於接地層161。第二基板130與接地層161的結合做為一電磁干擾屏蔽,以保護半導體晶片140免受電磁干擾影響到半導體晶片140的操作。
由於第二基板130的側面130s、封裝體150之側面150s與接地件111的側面111s於同一製程形成,故側面130s、150s與111s實質上對齊或共面。
第一天線層560包括彼此隔離之一接地層161及一幅射層162。接地層161形成於封裝體150之側面150s且從接地件111露出,而輻射層162形成於封裝體150之上表面150u。
請參照第6圖,其繪示依照本發明另一實施例之半導體封裝件600的剖視圖。半導體封裝件500包括一第一基板110、一中介層基板120、一第二基板130、數個半導體晶片140、一封裝體150、一第一天線層160、一導電架270及數個電性接點280。
第一基板110包括一接地件111,其例如是一圖案化導電層,其中接地件111電性連接於對應之電性接點280。本例中,接地件111未從第一基板110的側面110s露出,然此非用以限制本發明實施例。
由於第一基板110之側面110s與封裝體150之第一側面150s1於同一製程中形成,故第一基板110之側面110s與封裝體150之第一側面150s1實質上對齊或共面。
封裝體150包覆第二基板130、數個半導體晶片140及中介層基板120,且具有一第二側面150s2及一上表面150u,其中,由於封裝體150之第二側面150s2與導電架270之側面270s於同一製程中形成,故封 裝體150之第二側面150s2與導電架270之側面270s實質上對齊或共面。
第一天線層560包括彼此隔離之一接地層161及一幅射層162,其中接地層161形成於封裝體150之第二側面150s2及露出之接地件111,且輻射層162形成於封裝體150之上表面150u。本例中,輻射層162係一縫隙耦合天線。
請參照第7圖,其繪示依照本發明另一實施例之半導體封裝件700的剖視圖。半導體封裝件700包括一第一基板110、至少一封模穿孔(through mold via,TMV)720、數個介電層730、數個半導體晶片140、一封裝體150及一第一天線層760。
如第7圖所示,第一基板110包括一側面110s及一接地件111,其例如是一圖案化導電層,其中,接地件111電性連接於對應之電性接點280。本例中,接地件111設於第一基板110之上表面110u,然此非用以限制本發明實施例。
封裝體150包覆第一基板110及數個半導體晶片140,且具有一側面150s及一上表面150u,其中,封裝體150之側面150s與第一基板110之側面110s實質上對齊或共面。封模穿孔720形成於封裝體150且以導電材料填滿,並電性連接於接地件111。
數層介電層730形成於封裝體150之上表面150u。另一例中,介電層730可形成於封裝體150之上表面150u、數層介電層730之一側面730s、封裝體150之一側面150s及第一基板110之一側面110s。微帶線131、內埋之相位位移器132、圖案化導電層133、饋入網134及導電孔135形成於介電層730。此外,介電層730可由例如是封裝體、介電材料(例 如是環氧樹脂)或一預浸漬層的材料形成。
第一天線層760具有數個開槽760a,且形成於介電層730之上表面730u,並透過封模穿孔720及導電孔135(未繪示)電性連接於接地件111。此外,第一天線層760的材料相似於第一天線層160,容此不再贅述。
如第7圖所示,無線射頻訊號可透過一傳輸路徑傳輸至半導體晶片140,其中傳輸路徑包含開槽760a、微帶線131、導電孔135、圖案化導電層133、內埋之相位位移器132、饋入網134及封模穿孔720。由於傳輸路徑縮短,本實施例之無線射頻訊號的失真因此而降低。
請參照第8A至8H圖,其繪示第1A圖半導體封裝件之製造過程圖。
如第8A圖所示,提供第一基板110,其包括數個接地件111。接地件111例如是導電柱。至少一半導體晶片112及被動元件143設於第一基板110且電性連接於第一基板110。第一基板110係一長條基板,其具有數個基板區域(package site)。
如第8B圖所示,提供第二基板130,其中數個半導體晶片140設於第二基板130。其中一半導體晶片140以其主動面朝上的方式設於第二基板130,且以數個導電接合線141電性連接於第二基板130。另一半導體晶片140以其主動面朝下的方式設於第二基板130,且以數個焊球142電性連接於第二基板130。
請參照第8C圖,設置中介層基板120於第一基板110上,其中中介層基板120包括數個導電元件122,用以電性連接第一基板110與 第二基板130。即,導電元件122透過例如是焊料(solder material)或導電黏結物(conductive adhesive)電性連接第一基板110的數個接墊(contact pad)與第二基板130。此外,導電黏結物123可形成於中介層基板120之一轉角,以提昇中介層基板120與半導體晶片140之間的結合性。
如第8D圖所示,倒置第二基板130,然後將其設置在中介層基板120上,使中介層基板120位於第一基板110與第二基板130之間。如此,第一基板110透過中介層基板120電性連接於第二基板130。此外,在中介層基板120設於第一基板110前,第一基板110可黏合於載板185上。第二基板130倒置後,透過回焊製程(reflow),半導體晶片112的焊球113可黏接第一基板110與半導體晶片112。
如第8E圖所示,形成封裝體150於第一基板110之上表面110u並包覆第二基板130、半導體晶片112、140與中介層基板120,其中封裝體150具有一上表面150u。
如第8F圖所示,形成數個切割道T1經過封裝體150及接地件111。數個切割道T1可由雷射或其它刀具形成。切割後,形成封裝體150之側面150s及接地件111的側面111s。本例之切割方式稱為全穿切(full-cut),即,數個切割道T1切斷第一基板110、接地件111與封裝體150。
如第8G圖所示,形成一天線材料160’於封裝體150之側面150s及上表面150u及接地件111的側面111s。此外,天線材料160’係一金屬材料,且藉由一材料形成技術形成,其中材料形成技術例如是化學氣相沈積、無電鍍法(electroless plating)、電解電鍍(electrolytic plating)、印刷、 旋塗、噴塗、濺鍍(sputtering)或真空沈積法(vacuum deposition)。
如第8H圖所示,採用圖案化技術,藉由形成開槽160a於天線材料160’(繪示於第8G圖),而形成第一天線層160。形成開槽160a之圖案化技術可包含微影製程(photolithography)、化學蝕刻(chemical etching)、雷射鑽孔(laser drilling)或機械鑽孔(mechanical drilling)。如此,封裝體150之一部分從開槽160a露出。
請參照第9A至9I圖,其繪示第2圖半導體封裝件之製造過程圖。
如第9A圖所示,提供第一基板110,其包括數個接地件111。接地件111例如是圖案化導電層。數個半導體晶片112及被動元件143設於第一基板110。第一基板110例如是長條基板。此外,數個導電架270設於第一基板110且透過一焊料271電性連接於接地件111。
如第9B圖所示,提供第二基板130,其中微帶線131、內埋之相位位移器132、圖案化導電層133、饋入網134及數個導電孔135形成於第二基板130。此外,數個半導體晶片140設於第二基板130,且電性連接於第二基板130。其中一半導體晶片140以其主動面朝上的方式設於第二基板130,且以數個導電焊線140電性連接於第二基板130。另一半導體晶片140以其主動面朝下的方式設於第二基板130,且以數個焊球142電性連接於第二基板130。
如第9C圖所示,設置中介層基板120於第一基板110,其中中介層基板120包括數個導電元件122電性連接第一基板110與第二基板130。黏結物123的設置如上所述。形成黏結物123後,藉由回焊製程, 焊球142可黏接中介層基板120與半導體晶片140。
如第9D圖所示,倒置第二基板130且設於中介層基板120上,使中介層基板120位於第一基板110與第二基板130之間。此外,在中介層基板120設於第一基板110前,第一基板110可黏合於載板185上。
如第9E圖所示,形成封裝體150於第一基板110的上表面110u且包覆第二基板130、半導體晶片112、140及中介層基板120,其中封裝體150具有上表面150u。
如第9F圖所示,形成數個第一切割道T2經過封裝體150及導電架270。數個第一切割道T2可由雷射或其它刀具形成。切割後,形成封裝體150之第二側面150s2及導電架270的側面270s。本例之切割方式稱為半穿切(half-cut),即,數個第一切割道T2未切斷第一基板110。
如第9G圖所示,形成一天線材料160’於封裝體150之第二側面150s2及上表面150u及導電架270的側面270s。此外,天線材料160’係一金屬材料,金屬材料包含鋁、不銹鋼或銅,且由圖案化箔(patterned foil)、電鍍、濺鍍或其它塗佈製程(coating processes)形成。
如第9H圖所示,採用圖案化技術,藉由形成開槽160a於第一天線材料160’(繪示於第8G圖),而形成第一天線層160。其中封裝體150之一部分從開槽160a露出。形成開槽160a之圖案化技術可包含微影製程、化學蝕刻、雷射鑽孔或機械鑽孔。
如第9I圖所示,形成數個第二切割道T3經過第一基板110。數個第二切割道T3可由雷射或其它刀具形成。切割後,形成第一基板110之側面110s及封裝體150的第一側面150s1。此外,於形成第二切割道T3 之前或之後,電性接點280可鄰近第一基板110之下表面110b形成,以形成如第2圖所示之半導體封裝件200。
請參照第10A至10C圖,其繪示第3A圖半導體封裝件之製造過程圖。
如第10A圖所示,形成介電層385覆蓋第一天線層160之側面160s及上表面160u。介電層385可使用任何已知封裝技術(packaging technology)或層壓技術(laminate technology)形成。
如第10B圖所示,第二基板390包括形成於介電層385之上表面385u的數個子天線391。第二天線層390之形成方法相似於第3A圖之第一天線層160的形成方法,容此不再贅述。
如第10C圖所示,形成數個切割道經過介電層385,以形成如第3A圖所示之半導體封裝件300。
請參照第11A至11F圖,其繪示第4圖半導體封裝件之製造過程圖。
如第11A圖所示,形成數個第一切割道T2經過封裝體150及導電架270。數個第一切割道T2可由雷射或其它刀具形成。切割後,形成封裝體150之第二側面150s2及導電架270的側面270s。本例之切割方式稱為半穿切,即,數個第一切割道T2未切斷第一基板110。
如第11B圖所示,形成一天線材料160’於封裝體150之第二側面150s2及上表面150u及導電架270的側面270s。此外,天線材料160’係一金屬層,金屬層包含鋁、不銹鋼或銅,且由圖案化技術、電鍍、濺鍍或其它相似製程形成。
如第11C圖所示,採用圖案化技術,藉由形成數個開槽160a於天線材料160’(繪示於第11B圖),而形成第一天線層160,其中封裝體150之一部分從開槽160a露出。形成開槽160a之圖案化技術可包含微影製程、化學蝕刻、雷射鑽孔或機械鑽孔。
如第11D圖所示,形成介電層385覆蓋第一天線層160之接地層161及輻射層162。介電層385可使用任何已知封裝技術或層壓技術形成。
如第11E圖所示,形成第二天線層390於介電層385上,其中第二天線層390與第一天線層160隔離。本例中,第二天線層390係縫隙耦合天線。
如第11F圖所示,形成數個第二切割道T3經過第一基板110及介電層385。數個第二切割道T3可由雷射或其它刀具形成。切割後,形成第一基板110之側面110s及介電層385之側面385s。此外,於形成第二切割道T3之前或之後,電性接點280(繪示於第4圖)可鄰近第一基板110之下表面110b形成,以形成如第4圖所示之半導體封裝件400。
請參照第12A至12B圖,其繪示第5圖半導體封裝件之製造過程圖。
如第12A圖所示,形成一天線材料160’於封裝體150之側面150s及上表面150u、第二基板130之側面130s及接地件111的側面111s。當形成天線材料160’時,半導體封裝件可設於一載板185上。
如第12B圖所示,採用圖案化技術,藉由形成開槽160a於天線材料160’,而形成第一天線層560,其中,封裝體150之一部分從開槽 160a露出。形成開槽160a之圖案化技術可包含微影製程、化學蝕刻、雷射鑽孔或機械鑽孔。
如第12B圖所示,第一天線層560包括彼此隔離之接地層161及輻射層162,其中接地層161形成於封裝體150之側面150s及露出之接地件111上,且輻射層162形成於封裝體150之上表面150u上。
請參照第13A至13D圖,其繪示第6圖半導體封裝件之製造過程圖。
如第13A圖所示,形成數個第一切割道T2經過封裝體150、第二基板130及導電架270。數個第一切割道T2可由雷射或其它刀具形成。切割後,形成封裝體150之第二側面150s2、第二基板130之側面130s及導電架270的側面270s。本例之切割方式稱為半穿切,即,數個第一切割道T2未切斷第一基板110。
如第13B圖所示,形成一天線材料160’於封裝體150之第二側面150s2及上表面150u、第二基板130之側面130s及導電架270的側面270s。此外,天線材料160’係一金屬層,金屬層包含鋁、不銹鋼或銅,且由圖案化技術、電鍍、濺鍍或其它相似製程形成。
如第13C圖所示,採用圖案化技術,藉由形成數個開槽160a於天線材料160’,而形成第一天線層560,其中,封裝體150之一部分從開槽160a露出。形成開槽160a之圖案化技術可包含微影製程、化學蝕刻、雷射鑽孔或機械鑽孔。
如第13C圖所示,第一天線層560包括彼此隔離之接地層161及輻射層162,其中接地層161形成於封裝體150之第二側面150s2及 露出之接地件111上,且輻射層162形成於封裝體150之上表面150u上。
如第13D圖所示,形成數個第二切割道T3經過第一基板110。數個第二切割道T3可由雷射或其它刀具形成。切割後,形成第一基板110之側面110s。此外,於形成第二切割道T3之前或之後,電性接點280(繪示於第6圖)可鄰近第一基板110之下表面110b形成,以形成如第6圖所示之半導體封裝件200。
綜上所述,雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾。因此,本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100‧‧‧半導體封裝件
110‧‧‧第一基板
110b‧‧‧下表面
110u、150u‧‧‧上表面
111s、150s‧‧‧側面
111‧‧‧接地件
142‧‧‧焊球
120‧‧‧中介層基板
122‧‧‧導電元件
123‧‧‧黏結物
130‧‧‧第二基板
131‧‧‧微帶線
132‧‧‧相位位移器
133‧‧‧圖案化導電層
134‧‧‧饋入網
135‧‧‧導電孔
140‧‧‧半導體晶片
141‧‧‧接合線
143‧‧‧被動元件
150‧‧‧封裝體
160‧‧‧第一天線層
160a‧‧‧開槽
161‧‧‧接地層
162‧‧‧幅射層

Claims (20)

  1. 一種半導體封裝件,包括:一第一基板,包含一接地層;一中介層,設於該第一基板的一上表面且具有至少一開口;一第一晶片,設於該至少一開口並耦接於該第一基板;一第二基板,耦接於該中介層,且設於該第一基板上方且具有一面積,該第二基板之該面積小於該第一基板之一面積;一第二晶片,設於該第二基板之一下表面;一第三晶片,內埋於該第二基板;一感應器,設於該第二基板的一上表面,其中該感應器電性連接於該第二基板及該第三晶片;一封裝體,包覆該第一基板之數個部分、該中介層、該第二基板、該第一晶片與該第二晶片,該封裝體具有一側面及一上表面;以及一金屬層,設於該封裝體的該側面與該上表面,其中該金屬層電性連接該第一基板且具有數個孔正對於該感應器。
  2. 如申請專利範圍第1項所述之半導體封裝件,其中內埋之該第三晶片具有一主動面朝向該第一基板。
  3. 如申請專利範圍第1項所述之半導體封裝件,其中內埋之該第三晶片具有一主動面,該主動面包含數個從該第二基板露出 的結合墊(bond pad)。
  4. 如申請專利範圍第3項所述之半導體封裝件,更包括一電性路徑連接露出之該些接合墊與該感應器。
  5. 如申請專利範圍第1項所述之半導體封裝件,更包括一導電架,該導電架電性連接於該接地層及該金屬層。
  6. 如申請專利範圍第1項所述之半導體封裝件,其中該感應器隔著該封裝體與該金屬層隔離。
  7. 如申請專利範圍第1項所述之半導體封裝件,其中該些孔決定一輻射分佈型態(radiation distribution pattern)。
  8. 如申請專利範圍第1項所述之半導體封裝件,更包括:一介電層,覆蓋該金屬層的該上表面;以及一圖案化金屬層,形成於該介電層。
  9. 一種半導體封裝件,包括:一第一基板,包含一接地層;一中介層,設於該第一基板的一上表面;一第一晶片,設於由該中介層所定義之一空間且耦接於該第 一基板;一第二基板,設於該第一基板上方且耦接於該中介層;一第二晶片,設於該第二基板之一下表面;一感應器,設於該第二基板的一上表面且耦接於該第二晶片;一封裝體,包覆該第一基板之數個部分、該中介層、該第二基板、該第一晶片與該第二晶片,該封裝體具有一側面及一上表面;以及一金屬層,設於該封裝體的該側面與該上表面,其中該金屬層電性連接該第一基板且具有數個孔正對於該感應器。
  10. 如申請專利範圍第9項所述之半導體封裝件,其中該第二基板具有一面積,該第二基板之該面積小於該第一基板之一面積。
  11. 如申請專利範圍第9項所述之半導體封裝件,更包括一第三晶片,該第三晶片內埋於該第二基板且電性連接於該感應器及該第二晶片。
  12. 如申請專利範圍第11項所述之半導體封裝件,其中內埋之該第三晶片具有一主動面朝向該第一基板。
  13. 如申請專利範圍第11項所述之半導體封裝件,其中內埋之該第三晶片具有一主動面,該主動面包含數個從該第二基板露出的結合墊。
  14. 如申請專利範圍第13項所述之半導體封裝件,更包括一電性路徑連接露出之該些接合墊與該感應器。
  15. 如申請專利範圍第9項所述之半導體封裝件,更包括一導電架,該導電架電性連接於該接地層及該金屬層。
  16. 如申請專利範圍第9項所述之半導體封裝件,其中該感應器隔著該封裝體與該金屬層隔離。
  17. 如申請專利範圍第9項所述之半導體封裝件,其中該些孔決定一輻射分佈型態。
  18. 一種半導體封裝件的製造方法,包括:提供一第一基板,該第一基板包含一接地件;提供一第二基板,該第二基板包含設於其上之一半導體晶片;設置一中介層基板於該第一基板與該第二基板之間,其中該中介層基板電性連接於該第一基板及該第二基板; 形成一封裝體包覆該第二基板之數個部分、該半導體晶片與該中介層基板;形成一第一切割道經過該封裝體,使該封裝體形成一側面;形成一第一天線層於該封裝體之該側面及一上表面,其中該第一天線層電性連接於該第一基板之該接地件;以及形成一第二切割道經過該第一基板。
  19. 如申請專利範圍第18項所述之製造方法,更包括:設置一導電架於該第一基板之該接地件;以及更形成該第一切割道經過該導電架。
  20. 如申請專利範圍第18項所述之製造方法,其中該接地件從該第一基板之一上表面露出,該製造方法更包括:設置一導電架於該第一基板之該接地件上;更形成該第一切割道經過該導電架;形成一天線材料於該第二基板之該側面、該封裝體之該側面與露出之該接地件;以及圖案化該天線材料而形成該第一天線層,其中該第一天線層包括一接地層及一幅射層,該接地層形成於該第二基板之該側面、該封裝體之該側面與露出之該接地件,而該輻射層形成於該封裝體之該上表面且與該接地件隔離。
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