TWI387084B - 具有穿導孔之基板及具有穿導孔之基板之封裝結構 - Google Patents

具有穿導孔之基板及具有穿導孔之基板之封裝結構 Download PDF

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TWI387084B
TWI387084B TW098103034A TW98103034A TWI387084B TW I387084 B TWI387084 B TW I387084B TW 098103034 A TW098103034 A TW 098103034A TW 98103034 A TW98103034 A TW 98103034A TW I387084 B TWI387084 B TW I387084B
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substrate
holes
metal heat
heat dissipation
package structure
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TW201029140A (en
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Kuo Hua Chen
Kuo Pin Yang
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Advanced Semiconductor Eng
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Description

具有穿導孔之基板及具有穿導孔之基板之封裝結構
本發明係關於一種基板及具有基板之封裝結構，詳言之，係關於一種具有穿導孔之基板及具有穿導孔之基板之封裝結構。
參考圖1，顯示習知具有穿導孔之基板之俯視示意圖。該基板1包括一基板本體11及複數個穿導孔12。該基板本體11具有一表面111。該等穿導孔12貫穿該基板本體11，每一穿導孔12內具有一導電材料121，且該導電材料121係填滿該等穿導孔12。
該習知具有穿導孔之基板1之缺點如下。該基板1之穿導孔12之導電材料121之材質通常為金屬，金屬係為良好熱導體，然而該基板1之穿導孔12之導電材料121係填滿該等穿導孔12，但顯露於該基板1之表面111之面積極少，故難以達到良好的散熱效果。
因此，有必要提供一種具有穿導孔之基板及具有穿導孔之基板之封裝結構，以解決上述問題。
本發明提供一種具有穿導孔之基板。該基板包括一基板本體、複數個穿導孔及至少一金屬散熱區。該基板本體具有一表面。該等穿導孔貫穿該基板本體，每一穿導孔內具有一導電材料。該金屬散熱區位於該基板本體之表面，且其涵蓋至少二個穿導孔，位於該金屬散熱區內之該等穿導孔之電性係相同。
本發明另提供一種具有穿導孔之基板之封裝結構。該封裝結構包括一第一基板、至少一第一晶片、一第二基板、至少一第二晶片及複數個銲球。該第一晶片位於該第一基板上，且電性連接至該第一基板。該第二基板位於該第一晶片上方，包括一第二基板本體、複數個第二穿導孔及至少一第二金屬散熱區。該第二基板本體具有一表面。該等第二穿導孔貫穿該第二基板本體，每一第二穿導孔內具有一第二導電材料。該第二金屬散熱區位於該第二基板本體之表面，且其涵蓋至少二個第二穿導孔，位於該第二金屬散熱區內之第二穿導孔之電性係相同。該第二晶片位於該第二基板上，且電性連接至該第二基板。該等銲球電性連接該第二基板之該等第二穿導孔至該第一基板。
藉此，該等穿導孔之熱能傳輸至該金屬散熱區，而該金屬散熱區之面積大，可達到良好的散熱效果。此外，位於該金屬散熱區內之該等穿導孔之電性係相同，可隔絕雜訊，避免訊號干擾。
參考圖2，顯示本發明具有穿導孔之基板之第一實施例之俯視示意圖。該基板2包括一基板本體21、複數個穿導孔22及至少一金屬散熱區23。該基板本體21具有一表面211。在本實施例中，該基板本體21之材質係為矽。該等穿導孔22貫穿該基板本體21，每一穿導孔22內具有一導電材料221。在本實施例中，該導電材料221係填滿該等穿導孔22，然而在其他應用中，該導電材料221係電鍍於該等穿導孔22之內壁。
該金屬散熱區23位於該基板本體21之表面211，該金屬散熱區23之材質較佳者係為銅，且其涵蓋至少二個穿導孔22，位於該金屬散熱區23內之該等穿導孔22之電性係相同。在本實施例中，該金屬散熱區23係為一封閉環狀區域。該金屬散熱區23之寬度係略大於該等穿導孔22之直徑。在本實施例中，該等穿導孔22之電性相同，係為接地或電源。
該基板2之製造方法如下。首先，提供該基板本體21。該基板本體21包括該等穿導孔22。接著，於該基板本體21之表面211形成一重佈層(Redistribution Layer,RDL)時同時形成該金屬散熱區23。
參考圖3，顯示本發明具有穿導孔之基板之第二實施例之俯視示意圖。本實施例之具有穿導孔之基板3與第一實施例之具有穿導孔之基板2(圖2)大致相同。本實施例與第一實施例之不同處在於該等穿導孔32之電性及該金屬散熱區33之分佈。
在本實施例中，該金屬散熱區33係為複數個區塊，該等區塊彼此不連接。該等穿導孔32包括複數個接地穿導孔322及複數個電源穿導孔323。該金屬散熱區33包括至少一接地金屬散熱區331及至少一電源金屬散熱區332，該接地金屬散熱區331涵蓋至少二個接地穿導孔322，該電源金屬散熱區332涵蓋至少二個電源穿導孔323。
參考圖4，顯示本發明具有穿導孔之基板之第三實施例之俯視示意圖。本實施例之具有穿導孔之基板4與第一實施例之具有穿導孔之基板2(圖2)大致相同。本實施例與第一實施例之不同處在於該等穿導孔42之電性及該金屬散熱區43之分佈。
在本實施例中，該金屬散熱區43係為複數個區塊，該等區塊彼此不連接，位於該基板本體41之表面411之四周，且涵蓋至少四個陣列排列之穿導孔42。該等穿導孔42包括複數個接地穿導孔422及複數個電源穿導孔423。該金屬散熱區43包括至少一接地金屬散熱區431及至少一電源金屬散熱區432，該接地金屬散熱區431涵蓋至少二個接地穿導孔422，該電源金屬散熱區432涵蓋至少二個電源穿導孔423。
參考圖5，顯示本發明具有穿導孔之基板之第四實施例之俯視示意圖。本實施例之具有穿導孔之基板5與第一實施例之具有穿導孔之基板2(圖2)大致相同。本實施例與第一實施例之不同處，在於該金屬散熱區53位於該基板本體51之表面511之中心並延伸至四周，且涵蓋至少四個陣列排列之穿導孔52。
藉此，在本發明中，該等穿導孔22,32,42,52之熱能傳輸至該金屬散熱區23,33,43,53，而由於該金屬散熱區23,33,43,53之面積大，可達到良好的散熱效果。此外，位於該金屬散熱區23,33,43,53內之該等穿導孔22,32,42,52之電性係相同，可隔絕雜訊，避免訊號干擾。
參考圖6，顯示本發明具有穿導孔之基板之封裝結構之剖面示意圖。該封裝結構6包括一第一基板7、至少一第一晶片62、一第二基板8、至少一第二晶片64及複數個銲球65。在本實施例中，該封裝結構6更包括一封膠材料66。
該第一基板7可以是一有機基板或一矽基板。該第一基板7之型式可以是一印刷電路板(Printed Circuit Board,PCB)或是圖2至圖5所示之基板，其具有至少一金屬散熱區。在本實施例中，該第一基板7之型式與第一實施例之基板2(圖2)相同，如圖7所示。該第一基板7包括一第一基板本體71、複數個第一穿導孔72及至少一第一金屬散熱區73。該第一基板本體71具有一表面711，該等第一穿導孔72貫穿該第一基板本體71，每一第一穿導孔72內具有一第一導電材料721，該第一金屬散熱區73位於該第一基板本體71之表面711，該第一金屬散熱區73之材質較佳者係為銅，且其涵蓋至少二個第一穿導孔72，位於該第一金屬散熱區73內之第一穿導孔72之電性係相同。再參考圖6，該第一晶片62位於該第一基板7上，且電性連接至該第一基板7。
該第二基板8位於該第一晶片62上方。參考圖8，顯示該第二基板之俯視示意圖，該第二基板8包括一第二基板本體81、複數個第二穿導孔82及至少一第二金屬散熱區83。在本實施例中，該第二基板8係為一矽基板。該第二基板本體81具有一表面811。該等第二穿導孔82貫穿該第二基板本體81，每一第二穿導孔82內具有一第二導電材料821。
該第二金屬散熱區83位於該第二基板本體81之表面811，該第二金屬散熱區83之材質較佳者係為銅，且其涵蓋至少二個第二穿導孔82，位於該第二金屬散熱區83內之第二穿導孔82之電性係相同。在本實施例中，該第二金屬散熱區83之寬度係略大於該等第二穿導孔82之直徑。在本實施例中，該第二金屬散熱區83係為複數個區塊，該等區塊此不連接。
該等第二穿導孔82包括複數個第二接地穿導孔822及複數個第二電源穿導孔823，該第二金屬散熱區83包括至少一第二接地金屬散熱區831及至少一第二電源金屬散熱區832，該第二接地金屬散熱區831涵蓋至少二個第二接地穿導孔822，該第二電源金屬散熱區832涵蓋至少二個第二電源穿導孔823。
在本實施例中，該第二基板8係與第二實施例之基板3(圖3)相同，然而可以理解的是，該第二基板8之型式也可以是圖2、圖4或圖5所示之基板。
請再參考圖6，該第二晶片64位於該第二基板8上，且電性連接至該第二基板8。該等銲球65電性連接該第二基板8之該等第二穿導孔82至該第一基板7。在本實施例中，該封膠材料66包覆該第一基板7、該第一晶片62、該第二基板8、該第二晶片64及該等銲球65。
惟上述實施例僅為說明本發明之原理及其功效，而非用以限制本發明。因此，習於此技術之人士對上述實施例進行修改及變化仍不脫本發明之精神。本發明之權利範圍應如後述之申請專利範圍所列。
1．．．習知具有穿導孔之基板
2．．．本發明具有穿導孔之基板之第一實施例
3．．．本發明具有穿導孔之基板之第二實施例
4．．．本發明具有穿導孔之基板之第三實施例
5．．．本發明具有穿導孔之基板之第四實施例
6．．．本發明具有穿導孔之基板之封裝結構
7．．．第一基板
8．．．第二基板
11．．．基板本體
12．．．穿導孔
21．．．基板本體
22．．．穿導孔
23．．．金屬散熱區
32．．．穿導孔
33．．．金屬散熱區
41．．．基板本體
42．．．穿導孔
43．．．金屬散熱區
51．．．基板本體
52．．．穿導孔
53．．．金屬散熱區
62．．．第一晶片
64．．．第二晶片
65．．．銲球
66．．．封膠材料
71．．．基板本體
72．．．穿導孔
73．．．金屬散熱區
81．．．第二基板本體
82．．．第二穿導孔
83．．．第二金屬散熱區
111．．．表面
121．．．導電材料
211．．．表面
221．．．導電材料
322．．．接地穿導孔
323．．．電源穿導孔
331．．．接地金屬散熱區
332．．．電源金屬散熱區
411．．．表面
422．．．接地穿導孔
423．．．電源穿導孔
431．．．接地金屬散熱區
432．．．電源金屬散熱區
511．．．表面
711．．．表面
721．．．導電材料
811．．．表面
821．．．第二導電材料
822．．．接地穿導孔
823．．．電源穿導孔
831．．．接地金屬散熱區
832．．．電源金屬散熱區
圖1顯示習知具有穿導孔之基板之俯視示意圖；
圖2顯示本發明具有穿導孔之基板之第一實施例之俯視示意圖；
圖3顯示本發明具有穿導孔之基板之第二實施例之俯視示意圖；
圖4顯示本發明具有穿導孔之基板之第三實施例之俯視示意圖；
圖5顯示本發明具有穿導孔之基板之第四實施例之俯視示意圖；
圖6顯示本發明具有穿導孔之基板之封裝結構之剖面示意圖；
圖7顯示圖6之第一基板之俯視示意圖；及
圖8顯示圖6之第二基板之俯視示意圖。
6．．．本發明具有穿導孔之基板之封裝結構
7．．．第一基板
8．．．第二基板
62．．．第一晶片
64．．．第二晶片
65．．．銲球
66．．．封膠材料
81．．．第二基板本體
82．．．第二穿導孔
811．．．表面
821．．．第二導電材料

Claims (17)

  1. 一種具有穿導孔之基板，包括：一基板本體，具有一表面；複數個穿導孔，貫穿該基板本體，每一穿導孔內具有一導電材料；及至少一金屬散熱區，位於該基板本體之表面，且其涵蓋至少二個穿導孔，位於該金屬散熱區內之該等穿導孔之電性係相同，其中該金屬散熱區係為複數個區塊，該等區塊彼此不連接。
  2. 如請求項1之基板，其中該基板本體之材質係為矽。
  3. 如請求項1之基板，其中該導電材料係填滿該等穿導孔。
  4. 如請求項1之基板，其中該導電材料係電鍍於該等穿導孔之內壁。
  5. 如請求項1之基板，其中該金屬散熱區之材質係為銅。
  6. 如請求項1之基板，其中該金屬散熱區之寬度係大於該等穿導孔之直徑。
  7. 如請求項1之基板，其中該金屬散熱區涵蓋至少四個陣列排列之穿導孔。
  8. 如請求項1之基板，其中該等穿導孔包括複數個接地穿導孔及複數個電源穿導孔，該金屬散熱區包括至少一接地金屬散熱區及至少一電源金屬散熱區，該接地金屬散熱區涵蓋至少二個接地穿導孔，該電源金屬散熱區涵蓋至少二個電源穿導孔。
  9. 一種具有穿導孔之基板之封裝結構，包括：一第一基板；至少一第一晶片，位於該第一基板上，且電性連接至該第一基板；一第二基板，位於該第一晶片上方，包括：一第二基板本體，具有一表面；複數個第二穿導孔，貫穿該第二基板本體，每一第二穿導孔內具有一第二導電材料；及至少一第二金屬散熱區，位於該第二基板本體之表面，且其涵蓋至少二個第二穿導孔，位於該第二金屬散熱區內之第二穿導孔之電性係相同，其中該第二金屬散熱區係為複數個區塊，該等區塊彼此不連接；至少一第二晶片，位於該第二基板上，且電性連接至該第二基板；及複數個銲球，電性連接該第二基板之該等第二穿導孔至該第一基板。
  10. 如請求項9之封裝結構，其中封裝結構更包括一封膠材料，其包覆該第一基板、該第一晶片、該第二基板、該第二晶片及該等銲球。
  11. 如請求項9之封裝結構，其中該第一基板包括：一第一基板本體，具有一表面；複數個第一穿導孔，貫穿該第一基板本體，每一第一穿導孔內具有一第一導電材料；及至少一第一金屬散熱區，位於該第一基板本體之表 面，且其涵蓋至少二個第一穿導孔，位於該第一金屬散熱區內之第一穿導孔之電性係相同。
  12. 如請求項9之封裝結構，其中該第一基板係為一矽基板或一有機基板，該第二基板係為一矽基板。
  13. 如請求項9之封裝結構，其中該第二導電材料係填滿該等第二穿導孔。
  14. 如請求項9之封裝結構，其中該第二導電材料係電鍍於該等第二穿導孔之內壁。
  15. 如請求項9之封裝結構，其中該第二金屬散熱區之寬度係大於該等第二穿導孔之直徑。
  16. 如請求項9之封裝結構，其中該第二金屬散熱區涵蓋至少四個陣列排列之第二穿導孔。
  17. 如請求項9之封裝結構，其中該等第二穿導孔包括複數個第二接地穿導孔及複數個第二電源穿導孔，該第二金屬散熱區包括至少一第二接地金屬散熱區及至少一第二電源金屬散熱區，該第二接地金屬散熱區涵蓋至少二個第二接地穿導孔，該第二電源金屬散熱區涵蓋至少二個第二電源穿導孔。
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Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI392069B (zh) * 2009-11-24 2013-04-01 Advanced Semiconductor Eng 封裝結構及其封裝製程
TWI446420B (zh) 2010-08-27 2014-07-21 Advanced Semiconductor Eng 用於半導體製程之載體分離方法
TWI445152B (zh) 2010-08-30 2014-07-11 Advanced Semiconductor Eng 半導體結構及其製作方法
US9007273B2 (en) 2010-09-09 2015-04-14 Advances Semiconductor Engineering, Inc. Semiconductor package integrated with conformal shield and antenna
TWI434387B (zh) 2010-10-11 2014-04-11 Advanced Semiconductor Eng 具有穿導孔之半導體裝置及具有穿導孔之半導體裝置之封裝結構及其製造方法
US9064879B2 (en) 2010-10-14 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures using a die attach film
US8936966B2 (en) 2012-02-08 2015-01-20 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods for semiconductor devices
US8105875B1 (en) 2010-10-14 2012-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Approach for bonding dies onto interposers
TWI527174B (zh) 2010-11-19 2016-03-21 日月光半導體製造股份有限公司 具有半導體元件之封裝結構
TWI445155B (zh) 2011-01-06 2014-07-11 Advanced Semiconductor Eng 堆疊式封裝結構及其製造方法
US8853819B2 (en) 2011-01-07 2014-10-07 Advanced Semiconductor Engineering, Inc. Semiconductor structure with passive element network and manufacturing method thereof
US8541883B2 (en) 2011-11-29 2013-09-24 Advanced Semiconductor Engineering, Inc. Semiconductor device having shielded conductive vias
US8975157B2 (en) 2012-02-08 2015-03-10 Advanced Semiconductor Engineering, Inc. Carrier bonding and detaching processes for a semiconductor wafer
US8963316B2 (en) 2012-02-15 2015-02-24 Advanced Semiconductor Engineering, Inc. Semiconductor device and method for manufacturing the same
US8786060B2 (en) 2012-05-04 2014-07-22 Advanced Semiconductor Engineering, Inc. Semiconductor package integrated with conformal shield and antenna
US9153542B2 (en) 2012-08-01 2015-10-06 Advanced Semiconductor Engineering, Inc. Semiconductor package having an antenna and manufacturing method thereof
US8937387B2 (en) 2012-11-07 2015-01-20 Advanced Semiconductor Engineering, Inc. Semiconductor device with conductive vias
US8952542B2 (en) 2012-11-14 2015-02-10 Advanced Semiconductor Engineering, Inc. Method for dicing a semiconductor wafer having through silicon vias and resultant structures
US9406552B2 (en) 2012-12-20 2016-08-02 Advanced Semiconductor Engineering, Inc. Semiconductor device having conductive via and manufacturing process
US8841751B2 (en) 2013-01-23 2014-09-23 Advanced Semiconductor Engineering, Inc. Through silicon vias for semiconductor devices and manufacturing method thereof
US9978688B2 (en) 2013-02-28 2018-05-22 Advanced Semiconductor Engineering, Inc. Semiconductor package having a waveguide antenna and manufacturing method thereof
US9089268B2 (en) 2013-03-13 2015-07-28 Advanced Semiconductor Engineering, Inc. Neural sensing device and method for making the same
US9173583B2 (en) 2013-03-15 2015-11-03 Advanced Semiconductor Engineering, Inc. Neural sensing device and method for making the same
US8987734B2 (en) 2013-03-15 2015-03-24 Advanced Semiconductor Engineering, Inc. Semiconductor wafer, semiconductor process and semiconductor package
US9312198B2 (en) * 2013-03-15 2016-04-12 Intel Deutschland Gmbh Chip package-in-package and method thereof
KR102105902B1 (ko) * 2013-05-20 2020-05-04 삼성전자주식회사 방열 부재를 갖는 적층 반도체 패키지
KR101676916B1 (ko) * 2014-08-20 2016-11-16 앰코 테크놀로지 코리아 주식회사 반도체 디바이스의 제조 방법 및 이에 따른 반도체 디바이스
CN107924899B (zh) * 2015-08-27 2023-05-02 英特尔公司 多管芯封装
US11276667B2 (en) * 2016-12-31 2022-03-15 Intel Corporation Heat removal between top and bottom die interface
KR102633190B1 (ko) 2019-05-28 2024-02-05 삼성전자주식회사 반도체 패키지 및 그 제조 방법

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6268660B1 (en) * 1999-03-05 2001-07-31 International Business Machines Corporation Silicon packaging with through wafer interconnects
US20020034066A1 (en) * 2000-09-19 2002-03-21 Chien-Ping Huang Heat dissipation ball grid array package
US20030057534A1 (en) * 2001-09-25 2003-03-27 Siliconware Precision Industries Co., Ltd. Semiconductor package
US20070029660A1 (en) * 2005-08-08 2007-02-08 Hyung-Gil Baek Stack package implementing conductive support
US20070117267A1 (en) * 2002-10-08 2007-05-24 Chippac, Inc. Semiconductor Multi-Package Module Having Inverted Land Grid Array (LGA) Package Stacked Over Ball Grid Array (BGA) Package

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7276787B2 (en) * 2003-12-05 2007-10-02 International Business Machines Corporation Silicon chip carrier with conductive through-vias and method for fabricating same
JP4889974B2 (ja) * 2005-08-01 2012-03-07 新光電気工業株式会社 電子部品実装構造体及びその製造方法
JP2009124087A (ja) * 2007-11-19 2009-06-04 Oki Semiconductor Co Ltd 半導体装置の製造方法
JP5000540B2 (ja) * 2008-01-31 2012-08-15 新光電気工業株式会社 スイッチング機能付配線基板
US20090212420A1 (en) * 2008-02-22 2009-08-27 Harry Hedler integrated circuit device and method for fabricating same
CN102037560B (zh) * 2008-03-21 2012-09-26 Rise技术有限责任公司 通过将多孔硅转变成多孔金属或陶瓷来制作微结构的方法
US7821107B2 (en) * 2008-04-22 2010-10-26 Micron Technology, Inc. Die stacking with an annular via having a recessed socket
US8384224B2 (en) * 2008-08-08 2013-02-26 International Business Machines Corporation Through wafer vias and method of making same
US7859099B2 (en) * 2008-12-11 2010-12-28 Stats Chippac Ltd. Integrated circuit packaging system having through silicon via with direct interconnects and method of manufacture thereof
US20100237378A1 (en) * 2009-03-19 2010-09-23 Tzu-Han Lin Light emitting diode package structure and fabrication thereof
US20100244223A1 (en) * 2009-03-25 2010-09-30 Cho Namju Integrated circuit packaging system with an integral-interposer-structure and method of manufacture thereof
US8264091B2 (en) * 2009-09-21 2012-09-11 Stats Chippac Ltd. Integrated circuit packaging system with encapsulated via and method of manufacture thereof
US8362599B2 (en) * 2009-09-24 2013-01-29 Qualcomm Incorporated Forming radio frequency integrated circuits

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6268660B1 (en) * 1999-03-05 2001-07-31 International Business Machines Corporation Silicon packaging with through wafer interconnects
US20020034066A1 (en) * 2000-09-19 2002-03-21 Chien-Ping Huang Heat dissipation ball grid array package
US20030057534A1 (en) * 2001-09-25 2003-03-27 Siliconware Precision Industries Co., Ltd. Semiconductor package
US20070117267A1 (en) * 2002-10-08 2007-05-24 Chippac, Inc. Semiconductor Multi-Package Module Having Inverted Land Grid Array (LGA) Package Stacked Over Ball Grid Array (BGA) Package
US20070029660A1 (en) * 2005-08-08 2007-02-08 Hyung-Gil Baek Stack package implementing conductive support

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