TW201530734A - 半導體封裝 - Google Patents
半導體封裝 Download PDFInfo
- Publication number
- TW201530734A TW201530734A TW103140935A TW103140935A TW201530734A TW 201530734 A TW201530734 A TW 201530734A TW 103140935 A TW103140935 A TW 103140935A TW 103140935 A TW103140935 A TW 103140935A TW 201530734 A TW201530734 A TW 201530734A
- Authority
- TW
- Taiwan
- Prior art keywords
- semiconductor wafer
- pads
- semiconductor
- via plug
- package
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5286—Arrangements of power or ground buses
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Wire Bonding (AREA)
Abstract
本發明提供一種半導體封裝。上述半導體封裝包括一第一半導體晶片,其上具有複數個焊墊;一第一介層孔插塞和一第二介層孔插塞,分別設置於上述第一半導體晶片上,上述第一介層孔插塞連接至上述第一半導體晶片的上述些焊墊的至少兩個。
Description
本發明係關於一種半導體封裝,特別係關於一種半導體封裝的介層孔插塞設計。
對半導體封裝的設計而言,需要因應多功能晶片而增加輸入/輸出(I/O)連接數量。上述的影響會迫使印刷電路板製造商縮小線寬或線距或發展出晶片直接接觸(direct chip attach,DCA)半導體。然而,多功能晶片封裝因增加了輸入/輸出(I/O)連接數量會導致熱電特性問題,舉例來說,散熱問題、串音(crosstalk)、訊號傳輸延遲(signal propagation delay)或射頻(RF)電路的電磁干擾等問題。上述熱電特性問題會影響產品的可靠度和品質。
因此,在此技術領域中,有需要一種高密度的半導體封裝,以改善上述缺點。
有鑑於此,本發明之目的在於提供一種改良式的半導體封裝。
本發明之一實施例係提供一種半導體封裝。該半導體封裝包括一第一半導體晶片,其上具有複數個焊墊;一第一介層孔插塞和一第二介層孔插塞,分別設置於該第一半導體晶片上,其中該第一介層孔插塞連接至該第一半導體晶片的該
些焊墊的至少兩個。
本發明之另一實施例係提供一種半導體封裝。該半導體封裝包括一第一半導體晶片,其上具有一第一焊墊和一第二焊墊,其中該第一焊墊和該第二焊墊皆為電源墊或接地墊;一第一介層孔插塞,設置於該第一半導體晶片上,其中該第一介層孔插塞連接至該第一焊墊和該第二焊墊。
本發明之又一實施例係提供一種半導體封裝。該半導體封裝包括一第一半導體晶片,其上具有複數個焊墊;一第一介層孔插塞,設置於該第一半導體晶片上,其中該第一介層孔插塞連接至該第一半導體晶片的該些焊墊,其中在一俯視圖中,該第一介層孔插塞的形狀為網篩形或環形。
本發明之半導體封裝利用介層孔插塞連接至配置於半導體晶片之焊墊。上述介層孔插塞的設計可用來改善信號完整性。
500‧‧‧半導體封裝
202a~202h‧‧‧焊墊
212a~212c‧‧‧開口
218a~218c、218-P、218-G‧‧‧介層孔插塞
300‧‧‧重佈線層結構
302‧‧‧導線
303‧‧‧表面
304‧‧‧金屬層間介電層
305a~305d‧‧‧重佈線接觸焊墊
306a~306d‧‧‧封裝黏著物
308‧‧‧成型基板
308a‧‧‧成型材料
308b‧‧‧側面
310‧‧‧第一半導體晶片
310a、312a‧‧‧背面
310b、312b‧‧‧頂面
312‧‧‧第二半導體晶片
第1圖顯示本發明一些實施例之一半導體封裝之剖面示意圖。
第2圖顯示本發明一些實施例之一半導體封裝之一第一半導體晶片之俯視方向示意圖,其顯示半導體封裝之第一半導體晶片之介層孔插塞的佈局。
為了讓本發明之目的、特徵、及優點能更明顯易懂,下文特舉實施例,並配合所附圖示,做詳細之說明。本發
明說明書提供不同的實施例來說明本發明不同實施方式的技術特徵。其中,實施例中的各元件之配置係為說明之用,並非用以限制本發明。且實施例中圖式標號之部分重複,係為了簡化說明,並非意指不同實施例之間的關聯性。
第1圖顯示本發明一些實施例之一半導體封裝500之剖面示意圖。在本實施例中,上述半導體封裝500可為一晶片級封裝組件(wafer level package assembly),其使用介層孔插塞將一半導體元件連接至一重佈線層(redistribution layer,RDL)結構。如第1圖所示,在本發明一些實施例中,半導體封裝500包括一重佈線層結構300、一第一半導體晶片310、一第二半導體晶片312以及介層孔插塞218a~218c。然而,注意如第1圖所示的第一半導體晶片310和第二半導體晶片312僅做為實施例,且並未限制用於半導體封裝中的半導體晶片的數量。在本發明一些實施例中,半導體封裝500可包括一單一半導體晶片或包括多於兩個半導體晶片。並且,為了清楚顯示用於半導體晶片之電源焊墊或接地焊墊的介層孔插塞,用於半導體晶片之訊號焊墊(signal pad)的電性連接的介層孔插塞在圖式中(第1、2圖)不予顯示。
如第1圖所示,第一半導體晶片310和第二半導體晶片312係彼此隔開且藉由一黏著層(圖未顯示)貼附至一載板(圖未顯示)。第一半導體晶片310的背面310a和第二半導體晶片312的背面312a係接觸上述載板。第一半導體晶片310的頂面310b和第二半導體晶片312的頂面312b可背向遠離於上述載板。上述載板可用於提供結構剛性或用於沉積後續非剛性層的
一基座。
如第1圖所示,第二半導體晶片312係設置於第一半導體晶片310的旁邊。在本發明一些其他實施例中,第二半導體晶片312可設置於第一半導體晶片310上。第一半導體晶片310和第二半導體晶片312的電路係分別設置接近於其頂面310b和頂面312b。在本發明一些實施例中,焊墊202a~202d和焊墊202g係設置於第一半導體晶片310的頂面310b上,以電性連接至第一半導體晶片310的電路。焊墊202e、202f、202h係設置於第二半導體晶片312的頂面312b上,以電性連接至第二半導體晶片312的電路。在本發明一些實施例中,焊墊202a~202d和焊墊202g係屬於第一半導體晶片310的內連線結構(interconnection structure)(圖未顯示)的一最頂層金屬層。類似地,焊墊202e、202f和202h係屬於第二半導體晶片312的內連線結構(圖未顯示)的一最頂層金屬層。在本發明一些實施例中,焊墊202a~202d和焊墊202g係配置於第一半導體晶片310的中間區域內,用以傳輸第一半導體晶片310的接地信號或電源信號。焊墊202e、202f和202h係配置於第二半導體晶片312的中間區域內,用以傳輸第二半導體晶片312的接地信號或電源信號。因此,焊墊202a~202h可視為接地焊墊或電源焊墊。
如第1圖所示,一成型材料308a,施加於上述載板上,且可圍繞第一半導體晶片310和第二半導體晶片312,並填充位於第一半導體晶片310和第二半導體晶片312周圍的任何間隙,以形成一成型基板308。上述成型基板308也可覆蓋第一半導體晶片310的頂面310b和第二半導體晶片312的頂面
312b。在本發明一些實施例中,成型基板308可由任何非導電材料形成,例如環氧樹脂(epoxy)、樹脂(resin)、可塑型聚合物(moldable polymer)或類似的材料。成型材料308a可於實質上為液體時施加於上述載板上,之後可藉由在例如環氧樹脂或樹脂中的一化學反應將成型材料308a硬化。在本發明一些實施例中,成型材料308a可為紫外光硬化型聚合物(ultraviolet cured polymer)或熱硬化型聚合物,其於施加於上述載板時為一膠狀(gel)或為一可延展的固體(malleable solid),以設置圍繞第一半導體晶片310和第二半導體晶片312。在成型材料308a為紫外光硬化型聚合物或熱硬化型聚合物的實施例中,例如可使用一模型來形成成型基板308,上述模型係相鄰於例如為一晶圓或一封裝之一成型基板形成區域的邊界。
如第1圖所示,可藉由一微影製程,從成型基板308之接近第一半導體晶片310的頂面310b和第二半導體晶片312的頂面312b的一表面形成開口212a~212c,開口212a~212c穿過成型基板308的一部分。在本發明一些實施例中,開口212a~212c分別相應於焊墊202a~202h形成。更詳細來說,開口212a係相應於四個焊墊202a~202c、202g形成。開口212b係相應於焊墊202d。開口212c相應於三個焊墊202e、202f、202h形成。在本發明一些實施例中,開口的面積可設計大於第一半導體晶片310和第二半導體晶片312的任何焊墊的面積。舉例來說,開口212a的面積係設計大於第一半導體晶片310的焊墊202a~202c的面積。開口212c的面積係設計大於第二半導體晶片312的焊墊202e、202f、202h的面積。
如第1圖所示,介層孔插塞218a~218c係分別填充開口212a~212c而形成。因此,介層孔插塞218a~218c可被成型基板308圍繞而形成。在本發明一些實施例中,介層孔插塞218a~218c可由銅、鋁、金、鈀、銀、前述導電材料的合金或其他導電材料形成。
在本發明一些實施例中,介層孔插塞218a係設計電性耦接至設置於第一半導體晶片310上的四個焊墊,例如焊墊202a~202c、202g。介層孔插塞218c係設計連接至設置於第二半導體晶片312上的三個焊墊,例如焊墊202e、202f、202h。如第1圖所示,介層孔插塞218b係設計接觸單一個(single)設置於第一半導體晶片310上的焊墊202d。注意介層孔插塞218b係藉由重佈線層結構300電性連接至介層孔插塞218c。然而,注意如第1圖所示之設計連接至相同介層孔插塞之焊墊數量僅做為實施例,然其並非用以限定本發明。在本發明一些實施例中,介層孔插塞的面積可設計大於第一半導體晶片310和第二半導體晶片312的任何焊墊的面積。舉例來說,介層孔插塞218a的面積係設計大於第一半導體晶片310的焊墊202a~202c的面積。介層孔插塞218c的面積係設計大於第二半導體晶片312的焊墊202e、202f、202h的面積。
注意設計用以連接至相同介層孔插塞之焊墊係具有相同的功能。舉例來說,指定連接至單一介層孔插塞218a之第一半導體晶片310上的焊墊202a~202c、202g可視為接地焊墊202a~202c、202g。在本發明其他實施例中,指定連接至單一介層孔插塞218a之第一半導體晶片310上的焊墊202a~202c、
202g也可視為用以提供相同電壓的電源焊墊202a~202c、202g。類似地,指定連接至介層孔插塞218c的第二半導體晶片312的焊墊202e、202f、202h可視為接地焊墊202e、202f、202h或電源焊墊202e、202f、202h。然而,如第1圖所示之介層孔插塞和導線之間的連接僅做為一實施例,然其並非用以限定本發明。
如第1圖所示,注意半導體封裝500的一些介層孔插塞係設計具有繞線功能。因此,位於第一半導體晶片310或第二半導體晶片312上的一些介層孔插塞可設計連接數個具有相同功能的焊墊。舉例來說,介層孔插塞可設計連接位於第一半導體晶片310或第二半導體晶片312上鄰近的接地焊墊。在本發明其他實施例中,介層孔插塞可設計連接位於第一半導體晶片310或第二半導體晶片312上鄰近且用以提供相同電壓的電源焊墊。因此,介層孔插塞可視為重佈線層圖案或傳輸網路,以連接配置於第一半導體晶片310或第二半導體晶片312的某個區域的相鄰的接地焊墊/電源焊墊。在本發明一些實施例中,在一俯視圖中,由介層孔插塞構成的重佈線層圖案的形狀係配置具有為網篩形(mesh-shape)或環形。
如第1圖所示,重佈線層結構300係設置於成型基板308之接近於焊墊202a~202h的一側面308b上。重佈線層結構300可接觸成型基板308以及第一半導體晶片310和第二半導體晶片312的焊墊202a~202h。在本發明一些實施例中,重佈線層結構300可具有一個或多個導線302,設置於金屬層間介電層(intermetal dielectric layer)304中。導線302係分別電性連接至
重佈線接觸焊墊305a~305d。然而,注意設計連接至如第1圖所示之相同介層孔插塞的導線302、金屬層間介電層304及重佈線接觸焊墊305a~305d的數量僅做為實施例,並非用以限定本發明。在本發明一些實施例中,半導體封裝500係使用介層孔插塞218a~218c分別將第一半導體晶片310和第二半導體晶片312的接地焊墊和電源焊墊(例如焊墊202a~202h)連接至重佈線層結構300的導線302(用於半導體晶片的訊號焊墊的介層孔插塞並未顯示於第1圖中)。導線302可設計為從介層孔插塞218a~218c中之一個或多個扇出(fanout),且提供第一半導體晶片310和第二半導體晶片312的焊墊202a~202h以及重佈線接觸焊墊305a~305d之間的電性連接物。因此,相較於第一半導體晶片310和第二半導體晶片312的焊墊202a~202h的焊墊間距,重佈線接觸焊墊305a~305d可以具有較大的焊墊間距,而可適用於球柵陣列(ball grid array)或其他封裝黏著系統(package mounting system)。在本發明一些實施例中,重佈線層結構300可具有將一個或多個介層孔插塞218a~218c連接至重佈線接觸焊墊305a~305d的導線302。舉例來說,其中一個導線302可將第一半導體晶片310的介層孔插塞218b和第二半導體晶片312的介層孔插塞218c電性連接至重佈線接觸焊墊305c和305d。舉例來說,其中一個導線302可將介層孔插塞218a電性連接至重佈線接觸焊墊305a和305b。
如第1圖所示,封裝黏著物306a~306d可分別設置於重佈線接觸焊墊305a~305d上,而後可測試第一半導體晶片310和第二半導體晶片312。封裝黏著物306a~306d可設置於重
佈線層結構300之遠離於第一半導體晶片310和第二半導體晶片312的一表面303上。封裝黏著物306a~306d分別耦接至導線302。在本發明一些實施例中,例如為封裝黏著物306a~306d可配置為包括一球柵陣列(ball grid array,BGA)的焊球。在本發明一些其他實施例中,封裝黏著物306a~306d可為平面網格陣列(land grid array,LGA)、插針網格陣列(pin grid array,PGA)或其他適當的封裝黏著系統。
第2圖顯示本發明一些實施例之一半導體封裝500之一第一半導體晶片310之俯視方向示意圖。第2圖也顯示本發明一些實施例之半導體封裝500之第一半導體晶片310之介層孔插塞218-P和218-G的佈局。注意為了清楚顯示用於第一半導體晶片310的電源和接地焊墊(例如焊墊210a~210d)之介層孔插塞218-P和218-G,用於第一半導體晶片310之訊號焊墊(signal pad)的介層孔插塞在第2圖中不予顯示。注意第二半導體晶片312的介層孔插塞218c的佈局可類似於第一半導體晶片310之介層孔插塞218-P和218-G的佈局。
在如第2圖所示之一些實施例中,介層孔插塞218-P係設計做為用於第一半導體晶片310之電源焊墊的重佈線繞線。在本發明一些實施例中,介層孔插塞218-G係設計做為用於第一半導體晶片310之接地焊墊的重佈線繞線。如第2圖所示,在本發明一些實施例中,第一半導體晶片310之介層孔插塞218-P和218-G係設計設置於接近第一半導體晶片310的一中間區域以連接第一半導體晶片310之相應的電源焊墊或接地焊墊。在本發明一些其他實施例中,第一半導體晶片310之介層
孔插塞218-P和218-G係設計配置於周邊區域(例如如第2圖所示之圍繞介層孔插塞218-P和218-G的區域),且相應於電源焊墊或接地焊墊的配置。
在如第2圖所示之一些實施例中,第一半導體晶片310之介層孔插塞218-P和218-G係設計連接至數個具有相同功能的焊墊。舉例來說,介層孔插塞218-G可設計連接至第一半導體晶片310之相鄰的接地焊墊。在本發明其他實施例中,介層孔插塞218-P可設計連接至第一半導體晶片310之相鄰的電源焊墊,用以提供相同的電壓。因此,介層孔插塞218-P/218-G可設計做為電源/接地傳輸網路,其用以連接至配置於第一半導體晶片310之一中間區域之相鄰的電源/接地焊墊。如第2圖所示,在本發明一些實施例中,配置為第一半導體晶片310之電源/接地傳輸網路的介層孔插塞218-P和218-G可具有網篩形或環形。注意在俯視圖中,第二半導體晶片312的介層孔插塞218c的形狀可類似於如第2圖所示之第一半導體晶片310的介層孔插塞218-P和218-G。
在如第2圖所示之一些實施例中,介層孔插塞218-P可配置為電源傳輸網路,以進一步擴大用於第一半導體晶片310之電源焊墊的繞線面積。當電源信號從第一半導體晶片310至重佈線層結構300或至第二半導體晶片312(如第1圖所示)時,介層孔插塞218-P可改善電源信號的信號完整性。注意當如第1圖所示之介層孔插塞218c設計連接至第二半導體晶片312的電源焊墊時,介層孔插塞218c也可改善電源信號的信號完整性。
在如第2圖所示之一些實施例中,介層孔插塞218-G可配置為接地傳輸網路,以進一步擴大用於第一半導體晶片310之接地焊墊的繞線面積。由介層孔插塞218-G構成的擴大接地傳輸網路可提升對介層孔插塞218-P的屏蔽能力。注意當如第1圖所示之介層孔插塞218c設計連接至第二半導體晶片312的接地焊墊時,介層孔插塞218c也可提升對用於連接電源焊墊的其他介層孔插塞的屏蔽能力。
本發明實施例係提供一種半導體封裝。上述半導體封裝係使用介層孔插塞,每一個介層孔插塞係設計將一半導體晶片的複數個電源焊墊或接地焊墊連接至一重佈線層結構。在本發明一些實施例中,上述介層孔插塞可視為重佈線層圖案或傳輸網路,其用以連接至配置於半導體晶片之一中間區域之相鄰的電源/接地焊墊。在本發明一些實施例中,上述介層孔插塞可配置為半導體晶片的重佈線網路,且在一俯視圖中的形狀為網篩形或環形。在本發明一些實施例中,當電源信號從一半導體晶片至重佈線層結構300或至另一半導體晶片時,配置為電源重佈線網路圖案/傳輸網路的介層孔插塞可改善電源信號的信號完整性。在本發明一些實施例中,配置為接地重佈線網路圖案/傳輸網路的介層孔插塞可提升對用於連接電源焊墊的其他介層孔插塞的屏蔽能力。
雖然本發明已以實施例揭露於上,然其並非用以限定本發明,任何熟習此項技藝者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
500‧‧‧半導體封裝
202a~202h‧‧‧焊墊
212a~212c‧‧‧開口
218a~218c‧‧‧介層孔插塞
300‧‧‧重佈線層結構
302‧‧‧導線
303‧‧‧表面
304‧‧‧金屬層間介電層
305a~305d‧‧‧重佈線接觸焊墊
306a~306d‧‧‧封裝黏著物
308‧‧‧成型基板
308a‧‧‧成型材料
308b‧‧‧側面
310‧‧‧第一半導體晶片
310a、312a‧‧‧背面
310b、312b‧‧‧頂面
312‧‧‧第二半導體晶片
Claims (25)
- 一種半導體封裝,包括:一第一半導體晶片,其上具有複數個焊墊;以及一第一介層孔插塞和一第二介層孔插塞,分別設置於該第一半導體晶片上,其中該第一介層孔插塞連接至該第一半導體晶片的該些焊墊的至少兩個。
- 如申請專利範圍第1項所述之半導體封裝,其中該第二介層孔插塞連接至該第一半導體晶片的該些焊墊的其中一個。
- 如申請專利範圍第1項所述之半導體封裝,其中在一俯視圖中,該第一介層孔插塞的形狀為網篩形或環形。
- 如申請專利範圍第1項所述之半導體封裝,其中該第一介層孔插塞的面積大於該第二介層孔插塞的面積。
- 如申請專利範圍第1項所述之半導體封裝,其中該些焊墊的該至少兩個為電源焊墊或接地焊墊。
- 如申請專利範圍第1項所述之半導體封裝,其中該第一介層孔插塞的面積大於該些焊墊的其中任一個的面積。
- 如申請專利範圍第1項所述之半導體封裝,更包括:一重佈線層結構,其上具有一第一導線和一第二導線,其中該第一介層孔插塞和該第二介層孔插塞分別接觸該第一導線和該第二導線。
- 如申請專利範圍第7項所述之半導體封裝,更包括:一成型材料,圍繞該第一半導體晶片,且接觸該重佈線層結構和該第一半導體晶片;以及一第一封裝黏著物和一第二封裝黏著物,設置於該重佈線 層結構之遠離於該第一半導體晶片的一表面上,其中該第一封裝黏著物和該第二封裝黏著物分別耦接至該第一導線和該第二導線。
- 如申請專利範圍第1項所述之半導體封裝,更包括:一第二半導體晶片,設置於該第一半導體晶片旁或設置於該第一半導體晶片上。
- 一種半導體封裝,包括:一第一半導體晶片,其上具有一第一焊墊和一第二焊墊,其中該第一焊墊和該第二焊墊皆為電源焊墊或接地焊墊;以及一第一介層孔插塞,設置於該第一半導體晶片上,其中該第一介層孔插塞連接至該第一焊墊和該第二焊墊。
- 如申請專利範圍第10項所述之半導體封裝,更包括:一第二介層孔插塞,設置於該第一半導體晶片上,其中該第二介層孔插塞僅連接至該第一半導體晶片的一第三焊墊。
- 如申請專利範圍第10項所述之半導體封裝,其中在一俯視圖中,該第一介層孔插塞的形狀為網篩形或環形。
- 如申請專利範圍第11項所述之半導體封裝,其中該第一介層孔插塞的面積大於該第一焊墊和該第二焊墊的其中任一個的面積。
- 如申請專利範圍第11項所述之半導體封裝,其中該第一介層孔插塞的面積大於該第二介層孔插塞的面積。
- 如申請專利範圍第10項所述之半導體封裝,更包括: 一重佈線層結構,其上具有一第一導線和一第二導線,其中該第一介層孔插塞和該第二介層孔插塞分別接觸該第一導線和該第二導線。
- 如申請專利範圍第15項所述之半導體封裝,更包括:一成型材料,圍繞該第一半導體晶片,且接觸該重佈線層結構和該第一半導體晶片;以及一第一封裝黏著物和一第二封裝黏著物,設置於該重佈線層結構之遠離於該第一半導體晶片的一表面上,其中該第一封裝黏著物和該第二封裝黏著物分別耦接至該第一導線和該第二導線。
- 如申請專利範圍第10項所述之半導體封裝,更包括:一第二半導體晶片,設置於該第一半導體晶片旁或設置於該第一半導體晶片上。
- 一種半導體封裝,包括:一第一半導體晶片,其上具有複數個焊墊;以及一第一介層孔插塞,設置於該第一半導體晶片上,其中該第一介層孔插塞連接至該第一半導體晶片的該些焊墊,其中在一俯視圖中,該第一介層孔插塞的形狀為網篩形或環形。
- 如申請專利範圍第18項所述之半導體封裝,更包括:一第二介層孔插塞,設置於該第一半導體晶片上,其中該第二介層孔插塞僅連接至該第一半導體晶片的一額外的焊墊。
- 如申請專利範圍第19項所述之半導體封裝,其中該些焊墊 為電源焊墊或接地焊墊。
- 如申請專利範圍第19項所述之半導體封裝,其中該第一介層孔插塞的面積大於該些焊墊的其中任一個的面積。
- 如申請專利範圍第19項所述之半導體封裝,其中該第一介層孔插塞的面積大於該第二介層孔插塞的面積。
- 如申請專利範圍第19項所述之半導體封裝,更包括:一重佈線層結構,其上具有一第一導線和一第二導線,其中該第一介層孔插塞和該第二介層孔插塞分別接觸該第一導線和該第二導線。
- 如申請專利範圍第23項所述之半導體封裝,更包括:一成型材料,圍繞該第一半導體晶片,且接觸該重佈線層結構和該第一半導體晶片;以及一第一封裝黏著物和一第二封裝黏著物,設置於該重佈線層結構之遠離於該第一半導體晶片的一表面上,其中該第一封裝黏著物和該第二封裝黏著物分別耦接至該第一導線和該第二導線。
- 如申請專利範圍第18項所述之半導體封裝,更包括:一第二半導體晶片,設置於該第一半導體晶片旁或設置於該第一半導體晶片上。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201461930041P | 2014-01-22 | 2014-01-22 | |
US14/323,107 US20150206855A1 (en) | 2014-01-22 | 2014-07-03 | Semiconductor package |
Publications (1)
Publication Number | Publication Date |
---|---|
TW201530734A true TW201530734A (zh) | 2015-08-01 |
Family
ID=52347200
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW103140935A TW201530734A (zh) | 2014-01-22 | 2014-11-26 | 半導體封裝 |
Country Status (4)
Country | Link |
---|---|
US (1) | US20150206855A1 (zh) |
EP (1) | EP2899755A1 (zh) |
CN (1) | CN104795382A (zh) |
TW (1) | TW201530734A (zh) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI560831B (en) * | 2015-10-15 | 2016-12-01 | Inotera Memories Inc | Wafer level package with tsv-less interposer |
TWI611530B (zh) * | 2016-10-14 | 2018-01-11 | 鈺橋半導體股份有限公司 | 具有散熱座之散熱增益型面朝面半導體組體及製作方法 |
US10720417B2 (en) | 2015-09-17 | 2020-07-21 | Deca Technologies Inc. | Thermally enhanced fully molded fan-out module |
TWI725277B (zh) * | 2017-02-24 | 2021-04-21 | 南韓商愛思開海力士有限公司 | 具有電磁干擾屏蔽或電磁波散射結構的半導體封裝 |
TWI730109B (zh) * | 2016-11-17 | 2021-06-11 | 台灣積體電路製造股份有限公司 | 晶片封裝結構及其形成方法 |
US11309246B2 (en) | 2020-02-05 | 2022-04-19 | Apple Inc. | High density 3D interconnect configuration |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9799592B2 (en) | 2013-11-19 | 2017-10-24 | Amkor Technology, Inc. | Semicondutor device with through-silicon via-less deep wells |
KR101982905B1 (ko) * | 2015-08-11 | 2019-05-27 | 앰코 테크놀로지 인코포레이티드 | 반도체 패키지 및 그 제조 방법 |
US9653406B2 (en) | 2015-04-16 | 2017-05-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Conductive traces in semiconductor devices and methods of forming same |
CN105161468A (zh) * | 2015-10-10 | 2015-12-16 | 中国电子科技集团公司第三十八研究所 | 一种射频芯片及其无源器件的封装结构和封装方法 |
US10679949B2 (en) * | 2016-03-11 | 2020-06-09 | Mediatek Inc. | Semiconductor package assembly with redistribution layer (RDL) trace |
CN106061118B (zh) * | 2016-06-28 | 2018-09-11 | 广东欧珀移动通信有限公司 | 移动终端中印刷电路板pcb的开孔方法和开孔装置 |
CN106373953A (zh) * | 2016-09-23 | 2017-02-01 | 湖北三江航天红峰控制有限公司 | 一种模拟舵机控制装置 |
CN106601702A (zh) * | 2017-01-23 | 2017-04-26 | 合肥雷诚微电子有限责任公司 | 无基板高散热性的多芯片线性功率放大器结构及其制作方法 |
CN108010898A (zh) * | 2017-11-02 | 2018-05-08 | 上海玮舟微电子科技有限公司 | 一种芯片封装结构 |
US10304792B1 (en) | 2017-11-16 | 2019-05-28 | Futurewei Technologies, Inc. | Semiconductor package having reduced internal power pad pitch |
US11233028B2 (en) | 2017-11-29 | 2022-01-25 | Pep Inovation Pte. Ltd. | Chip packaging method and chip structure |
US11114315B2 (en) | 2017-11-29 | 2021-09-07 | Pep Innovation Pte. Ltd. | Chip packaging method and package structure |
US11232957B2 (en) * | 2017-11-29 | 2022-01-25 | Pep Inovation Pte. Ltd. | Chip packaging method and package structure |
US11610855B2 (en) * | 2017-11-29 | 2023-03-21 | Pep Innovation Pte. Ltd. | Chip packaging method and package structure |
US10756038B1 (en) * | 2019-02-21 | 2020-08-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor package and manufacturing method thereof |
US11621236B2 (en) * | 2019-12-27 | 2023-04-04 | Intel Corporation | Electrostatic discharge protection in integrated circuits using positive temperature coefficient material |
CN111785700A (zh) * | 2020-09-07 | 2020-10-16 | 成都知融科技股份有限公司 | 一种超宽带互连结构 |
Family Cites Families (33)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3057975B2 (ja) * | 1993-09-27 | 2000-07-04 | 日本電気株式会社 | 集積回路の配線 |
US6351040B1 (en) * | 1998-01-22 | 2002-02-26 | Micron Technology, Inc. | Method and apparatus for implementing selected functionality on an integrated circuit device |
US6281108B1 (en) * | 1999-10-15 | 2001-08-28 | Silicon Graphics, Inc. | System and method to provide power to a sea of gates standard cell block from an overhead bump grid |
US6912778B2 (en) * | 2001-07-19 | 2005-07-05 | Micron Technology, Inc. | Methods of fabricating full-wafer silicon probe cards for burn-in and testing of semiconductor devices |
JP3860000B2 (ja) * | 2001-09-07 | 2006-12-20 | Necエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
SG107567A1 (en) * | 2001-11-07 | 2004-12-29 | Advanced Systems Automation | Method and apparatus for forming a flip chip semiconductor package and method for producing a substrate for the flip chip semiconductor package |
TW517361B (en) * | 2001-12-31 | 2003-01-11 | Megic Corp | Chip package structure and its manufacture process |
US6730540B2 (en) * | 2002-04-18 | 2004-05-04 | Tru-Si Technologies, Inc. | Clock distribution networks and conductive lines in semiconductor integrated circuits |
US6815812B2 (en) * | 2002-05-08 | 2004-11-09 | Lsi Logic Corporation | Direct alignment of contacts |
JP3580803B2 (ja) * | 2002-08-09 | 2004-10-27 | 沖電気工業株式会社 | 半導体装置 |
US7321167B2 (en) * | 2003-06-04 | 2008-01-22 | Intel Corporation | Flex tape architecture for integrated circuit signal ingress/egress |
CN1601735B (zh) * | 2003-09-26 | 2010-06-23 | 松下电器产业株式会社 | 半导体器件及其制造方法 |
US8853001B2 (en) * | 2003-11-08 | 2014-10-07 | Stats Chippac, Ltd. | Semiconductor device and method of forming pad layout for flipchip semiconductor die |
US7042077B2 (en) * | 2004-04-15 | 2006-05-09 | Intel Corporation | Integrated circuit package with low modulus layer and capacitor/interposer |
US7465654B2 (en) * | 2004-07-09 | 2008-12-16 | Megica Corporation | Structure of gold bumps and gold conductors on one IC die and methods of manufacturing the structures |
US8022544B2 (en) * | 2004-07-09 | 2011-09-20 | Megica Corporation | Chip structure |
US7271479B2 (en) * | 2004-11-03 | 2007-09-18 | Broadcom Corporation | Flip chip package including a non-planar heat spreader and method of making the same |
TWI255518B (en) * | 2005-01-19 | 2006-05-21 | Via Tech Inc | Chip package |
JP2007184449A (ja) * | 2006-01-10 | 2007-07-19 | Renesas Technology Corp | 半導体装置及びその製造方法 |
TWI298532B (en) * | 2006-04-14 | 2008-07-01 | Silicon Integrated Sys Corp | Conductive structure for electronic device |
US7514684B2 (en) * | 2006-08-28 | 2009-04-07 | L-3 Communications Corporation | Surface mounted infrared image detector systems and associated methods |
TWI370515B (en) * | 2006-09-29 | 2012-08-11 | Megica Corp | Circuit component |
US7842542B2 (en) * | 2008-07-14 | 2010-11-30 | Stats Chippac, Ltd. | Embedded semiconductor die package and method of making the same using metal frame carrier |
JP5147677B2 (ja) * | 2008-12-24 | 2013-02-20 | 新光電気工業株式会社 | 樹脂封止パッケージの製造方法 |
CN102439719B (zh) * | 2009-05-14 | 2015-06-24 | 高通股份有限公司 | 系统级封装 |
DE102010045649A1 (de) * | 2010-09-17 | 2012-03-22 | Texas Instruments Deutschland Gmbh | Elektronische Vorrichtung und Verfahren zum direkten Montieren passiver Komponenten |
US8709933B2 (en) * | 2011-04-21 | 2014-04-29 | Tessera, Inc. | Interposer having molded low CTE dielectric |
US8946888B2 (en) * | 2011-09-30 | 2015-02-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package on packaging structure and methods of making same |
JP5729290B2 (ja) * | 2011-12-16 | 2015-06-03 | 富士通株式会社 | 半導体装置の製造方法、電子装置の製造方法及び基板 |
US8742597B2 (en) * | 2012-06-29 | 2014-06-03 | Intel Corporation | Package substrates with multiple dice |
US20140133105A1 (en) * | 2012-11-09 | 2014-05-15 | Nvidia Corporation | Method of embedding cpu/gpu/logic chip into a substrate of a package-on-package structure |
US9478474B2 (en) * | 2012-12-28 | 2016-10-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for forming package-on-packages |
US9070644B2 (en) * | 2013-03-15 | 2015-06-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging mechanisms for dies with different sizes of connectors |
-
2014
- 2014-07-03 US US14/323,107 patent/US20150206855A1/en not_active Abandoned
- 2014-11-26 TW TW103140935A patent/TW201530734A/zh unknown
- 2014-12-17 CN CN201410784429.4A patent/CN104795382A/zh active Pending
-
2015
- 2015-01-15 EP EP15151288.6A patent/EP2899755A1/en not_active Withdrawn
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10720417B2 (en) | 2015-09-17 | 2020-07-21 | Deca Technologies Inc. | Thermally enhanced fully molded fan-out module |
TWI716732B (zh) * | 2015-09-17 | 2021-01-21 | 美商戴卡科技有限公司 | 熱增強型全模製扇出模組 |
TWI560831B (en) * | 2015-10-15 | 2016-12-01 | Inotera Memories Inc | Wafer level package with tsv-less interposer |
US9748184B2 (en) | 2015-10-15 | 2017-08-29 | Micron Technology, Inc. | Wafer level package with TSV-less interposer |
TWI611530B (zh) * | 2016-10-14 | 2018-01-11 | 鈺橋半導體股份有限公司 | 具有散熱座之散熱增益型面朝面半導體組體及製作方法 |
TWI730109B (zh) * | 2016-11-17 | 2021-06-11 | 台灣積體電路製造股份有限公司 | 晶片封裝結構及其形成方法 |
TWI725277B (zh) * | 2017-02-24 | 2021-04-21 | 南韓商愛思開海力士有限公司 | 具有電磁干擾屏蔽或電磁波散射結構的半導體封裝 |
US11309246B2 (en) | 2020-02-05 | 2022-04-19 | Apple Inc. | High density 3D interconnect configuration |
TWI781530B (zh) * | 2020-02-05 | 2022-10-21 | 美商蘋果公司 | 高密度3d互連構形 |
US11735526B2 (en) | 2020-02-05 | 2023-08-22 | Apple Inc. | High density 3D interconnect configuration |
Also Published As
Publication number | Publication date |
---|---|
CN104795382A (zh) | 2015-07-22 |
EP2899755A1 (en) | 2015-07-29 |
US20150206855A1 (en) | 2015-07-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TW201530734A (zh) | 半導體封裝 | |
US11961867B2 (en) | Electronic device package and fabricating method thereof | |
US10566320B2 (en) | Method for fabricating electronic package | |
TWI474461B (zh) | 積體電路及三維堆疊之多重晶片模組 | |
TWI654734B (zh) | 堆疊型半導體封裝 | |
TWI702703B (zh) | 半導體封裝元件 | |
TW201640628A (zh) | 具有較佳散熱效能的半導體晶片封裝構件 | |
US20140021591A1 (en) | Emi shielding semiconductor element and semiconductor stack structure | |
TW201633471A (zh) | 半導體封裝結構 | |
US9324633B2 (en) | Multi-level package assembly having conductive vias coupled to chip carrier for each level and method for manufacturing the same | |
US9443815B2 (en) | Embedded die redistribution layers for active device | |
US20170053884A1 (en) | Structure and layout of ball grid array packages | |
US8637987B2 (en) | Semiconductor assemblies with multi-level substrates and associated methods of manufacturing | |
TW201513291A (zh) | 晶片封裝及其製備方法 | |
US20170345796A1 (en) | Electronic device with stacked electronic chips | |
KR20110056205A (ko) | 반도체 칩 및 이를 갖는 적층 반도체 패키지 | |
US9859187B2 (en) | Ball grid array package with protective circuitry layout and a substrate utilized in the package | |
TWI636537B (zh) | 扇出型多晶片堆疊封裝之電子裝置及形成該裝置之方法 | |
TW201618254A (zh) | 封裝結構及其製法與封裝基板 | |
US10256203B2 (en) | Semiconductor device and semiconductor package | |
TW201637158A (zh) | 電子封裝組件 | |
KR20120031817A (ko) | 반도체 칩 내장 기판 및 이를 포함하는 적층 반도체 패키지 | |
TWI781863B (zh) | 平面式多晶片裝置 | |
CN107017230B (zh) | 多层级芯片互连 | |
TWI602250B (zh) | 半導體元件封裝製程 |